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author | yanhong.wang <yanhong.wang@starfivetech.com> | 2022-04-18 05:29:49 +0300 |
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committer | Yanhong Wang <yanhong.wang@linux.starfivetech.com> | 2022-10-18 11:24:34 +0300 |
commit | d3c8386d64f99863213087335b14be84c378957d (patch) | |
tree | 4ee51e049c940dd7264bc6a045eb848483c60a80 /arch/riscv | |
parent | 461cd1afbed484002536e4f6cf985d47c33b09e8 (diff) | |
download | u-boot-d3c8386d64f99863213087335b14be84c378957d.tar.xz |
board:starfive: add starfive visionfive board support
Add board support for StarFive VisionFive.
Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
Diffstat (limited to 'arch/riscv')
-rw-r--r-- | arch/riscv/Kconfig | 4 | ||||
-rw-r--r-- | arch/riscv/include/asm/arch-jh7110/jh7110-regs.h | 45 |
2 files changed, 49 insertions, 0 deletions
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 52e99e03d3..63b0c328bd 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -23,6 +23,9 @@ config TARGET_SIFIVE_UNLEASHED config TARGET_SIFIVE_UNMATCHED bool "Support SiFive Unmatched Board" +config TARGET_STARFIVE_VISIONFIVE + bool "Support StarFive VisionFive Board" + config TARGET_SIPEED_MAIX bool "Support Sipeed Maix Board" @@ -65,6 +68,7 @@ source "board/sifive/unleashed/Kconfig" source "board/sifive/unmatched/Kconfig" source "board/openpiton/riscv64/Kconfig" source "board/sipeed/maix/Kconfig" +source "board/starfive/visionfive/Kconfig" # platform-specific options below source "arch/riscv/cpu/ax25/Kconfig" diff --git a/arch/riscv/include/asm/arch-jh7110/jh7110-regs.h b/arch/riscv/include/asm/arch-jh7110/jh7110-regs.h new file mode 100644 index 0000000000..9b17e8bfe6 --- /dev/null +++ b/arch/riscv/include/asm/arch-jh7110/jh7110-regs.h @@ -0,0 +1,45 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2022 Starfive, Inc. + * Author: yanhong <yanhong.wang@starfivetech.com> + * + */ + +#ifndef __STARFIVE_JH7110_REGS_H +#define __STARFIVE_JH7110_REGS_H + +/*system control register*/ +#define STG_SYSCON_BASE 0x10240000 +#define SYS_SYSCON_BASE 0x13030000 +#define SYS_IOMUX_BASE 0x13040000 +#define AON_SYSCON_BASE 0x17010000 + +/*gmac cfg*/ +#define AON_SYSCFG_12 0xCU +#define SYS_SYSCON_144 0x90U +#define GMAC5_0_SEL_I_SHIFT 0x12U +#define GMAC5_0_SEL_I_MASK 0x1C0000U +#define GMAC5_1_SEL_I_SHIFT 0x2U +#define GMAC5_1_SEL_I_MASK 0x1CU + +/*usb cfg*/ +#define STG_SYSCON_4 0x4U +#define SYS_SYSCON_24 0x18U +#define SYS_IOMUX_32 0x80U +#define USB_MODE_STRAP_SHIFT 0x10U +#define USB_MODE_STRAP_MASK 0x70000U +#define USB_OTG_SUSPENDM_BYPS_SHIFT 0x14U +#define USB_OTG_SUSPENDM_BYPS_MASK 0x100000U +#define USB_OTG_SUSPENDM_SHIFT 0x13U +#define USB_OTG_SUSPENDM_MASK 0x80000U +#define USB_PLL_EN_SHIFT 0x16U +#define USB_PLL_EN_MASK 0x400000U +#define USB_REFCLK_MODE_SHIFT 0x17U +#define USB_REFCLK_MODE_MASK 0x800000U +#define PDRSTN_SPLIT_SHIFT 0x11U +#define PDRSTN_SPLIT_MASK 0x20000U +#define IOMUX_USB_SHIFT 0x10U +#define IOMUX_USB_MASK 0x7F0000U + +#endif /* __STARFIVE_JH7110_REGS_H */ + |