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authorBin Meng <bmeng.cn@gmail.com>2021-06-04 08:51:11 +0300
committerLeo Yu-Chi Liang <ycliang@andestech.com>2021-06-17 04:39:08 +0300
commitf050dd2b26abb4b107c3cdf7a5f5c420a9e1d4b6 (patch)
treeae5b52256130171b9de341a115d8d7a3d68e96dc /arch/riscv
parent5c267e00332473aeffd34d92d2f75558890de5d3 (diff)
downloadu-boot-f050dd2b26abb4b107c3cdf7a5f5c420a9e1d4b6.tar.xz
riscv: ae350: dts: Remove the unnecessary #address-cells in plic nodes
PLIC nodes don't have child nodes, so #address-cells is not needed. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Diffstat (limited to 'arch/riscv')
-rw-r--r--arch/riscv/dts/ae350_32.dts2
-rw-r--r--arch/riscv/dts/ae350_64.dts2
2 files changed, 0 insertions, 4 deletions
diff --git a/arch/riscv/dts/ae350_32.dts b/arch/riscv/dts/ae350_32.dts
index b90351e87b..0917b83108 100644
--- a/arch/riscv/dts/ae350_32.dts
+++ b/arch/riscv/dts/ae350_32.dts
@@ -135,7 +135,6 @@
plic0: interrupt-controller@e4000000 {
compatible = "riscv,plic0";
- #address-cells = <1>;
#interrupt-cells = <1>;
interrupt-controller;
reg = <0xe4000000 0x2000000>;
@@ -148,7 +147,6 @@
plic1: interrupt-controller@e6400000 {
compatible = "riscv,plic1";
- #address-cells = <1>;
#interrupt-cells = <1>;
interrupt-controller;
reg = <0xe6400000 0x400000>;
diff --git a/arch/riscv/dts/ae350_64.dts b/arch/riscv/dts/ae350_64.dts
index 27ac21c716..564e94a1db 100644
--- a/arch/riscv/dts/ae350_64.dts
+++ b/arch/riscv/dts/ae350_64.dts
@@ -135,7 +135,6 @@
plic0: interrupt-controller@e4000000 {
compatible = "riscv,plic0";
- #address-cells = <2>;
#interrupt-cells = <2>;
interrupt-controller;
reg = <0x0 0xe4000000 0x0 0x2000000>;
@@ -148,7 +147,6 @@
plic1: interrupt-controller@e6400000 {
compatible = "riscv,plic1";
- #address-cells = <2>;
#interrupt-cells = <2>;
interrupt-controller;
reg = <0x0 0xe6400000 0x0 0x400000>;