diff options
| author | yanhong.wang <yanhong.wang@starfivetech.com> | 2022-04-26 12:22:34 +0300 |
|---|---|---|
| committer | Yanhong Wang <yanhong.wang@linux.starfivetech.com> | 2022-10-18 11:24:34 +0300 |
| commit | f95a5cec9fd49737ce570098be96d0c4d5c40ea8 (patch) | |
| tree | 43f44d10017278a23e1a16948fc9ca151bea7b91 /arch/riscv | |
| parent | 3d8b5aeca1e41c1a5632e242db45a59b9a439a04 (diff) | |
| download | u-boot-f95a5cec9fd49737ce570098be96d0c4d5c40ea8.tar.xz | |
board:starfive: add rtc timer init
The rtc timer is used early in kernel, but the clk&reset driver is not
ready,so some clk&reset init is placed here.
Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
Diffstat (limited to 'arch/riscv')
| -rwxr-xr-x[-rw-r--r--] | arch/riscv/include/asm/arch-jh7110/jh7110-regs.h | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/arch/riscv/include/asm/arch-jh7110/jh7110-regs.h b/arch/riscv/include/asm/arch-jh7110/jh7110-regs.h index 9b17e8bfe6..89724813d8 100644..100755 --- a/arch/riscv/include/asm/arch-jh7110/jh7110-regs.h +++ b/arch/riscv/include/asm/arch-jh7110/jh7110-regs.h @@ -13,6 +13,10 @@ #define SYS_SYSCON_BASE 0x13030000 #define SYS_IOMUX_BASE 0x13040000 #define AON_SYSCON_BASE 0x17010000 +#define SYS_CRG_BASE 0x13020000 +#define CLK_ENABLE_MASK 0x80000000U +#define SYS_CRG_RESET_ASSERT3_SHIFT 0X304U +#define SYS_CRG_RESET_STATUS3_SHIFT 0X314U /*gmac cfg*/ #define AON_SYSCFG_12 0xCU @@ -41,5 +45,17 @@ #define IOMUX_USB_SHIFT 0x10U #define IOMUX_USB_MASK 0x7F0000U +/*timer cfg*/ +#define TIMER_CLK_APB_SHIFT 0x1F0U +#define TIMER_CLK_TIMER0_SHIFT 0x1F4U +#define TIMER_CLK_TIMER1_SHIFT 0x1F8U +#define TIMER_CLK_TIMER2_SHIFT 0x1FCU +#define TIMER_CLK_TIMER3_SHIFT 0x200U +#define TIMER_RSTN_APB_SHIFT 21 +#define TIMER_RSTN_TIMER0_SHIFT 22 +#define TIMER_RSTN_TIMER1_SHIFT 23 +#define TIMER_RSTN_TIMER2_SHIFT 24 +#define TIMER_RSTN_TIMER3_SHIFT 25 + #endif /* __STARFIVE_JH7110_REGS_H */ |