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| author | Zong Li <zong.li@sifive.com> | 2021-09-01 10:01:39 +0300 |
|---|---|---|
| committer | Leo Yu-Chi Liang <ycliang@andestech.com> | 2021-09-07 05:34:29 +0300 |
| commit | 43a21839285c1ba3b65534def898a2b5e2d46314 (patch) | |
| tree | 144a34f5e02db8cf905b79c240a337a9bd44eef0 /arch/riscv | |
| parent | 9d84795fc5dcd769cc8a1efedc783863e88cb25d (diff) | |
| download | u-boot-43a21839285c1ba3b65534def898a2b5e2d46314.tar.xz | |
cache: add sifive composable cache driver
This driver is currently responsible for enabling all ccache ways.
Composable cache could be configure as RAM or cache, we will use it as
RAM at the beginning to put the u-boot SPL there. In u-boot proper
phrase, we will use the composable cache as cache, and try to enable the
cache ways.
Signed-off-by: Zong Li <zong.li@sifive.com>
Reviewed-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
Diffstat (limited to 'arch/riscv')
0 files changed, 0 insertions, 0 deletions