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| author | Jagan Teki <jagan@amarulasolutions.com> | 2020-04-29 18:33:53 +0300 |
|---|---|---|
| committer | Jagan Teki <jagan@amarulasolutions.com> | 2020-04-30 20:04:20 +0300 |
| commit | 286bcdb40f11def282117e16401bb85502e426a8 (patch) | |
| tree | 2e679e8951da2f60f2c5f86c702f63d59326a796 /arch/riscv | |
| parent | 0edb066ce56504f84b8d8ff0e6f542fc36d0f3b7 (diff) | |
| download | u-boot-286bcdb40f11def282117e16401bb85502e426a8.tar.xz | |
sifive: fu540: Enable spi-nor flash support
HiFive Unleashed A00 support is25wp256 spi-nor flash,
So enable the same and add test result log for future
reference.
Tested on SiFive FU540 board.
Thanks to Sagar for various use cases and tests.
[QUAD mode in dt with spi-tx-bus-width: <4>]
pp opcode = 0x34 [QUAD MODE]
read opcode = 0x6c [QUAD MODE]
erase opcode = 0x21
SPI-NOR:
1. erase entire flash: Pass
2. write entire flash: Pass
3. read entire flash: Pass
4. cmp 32MiB read back data: Pass
5. MMC: Booted Linux and dtb from mmc
[SPI MODE in dt with spi-tx-bus-width: <1>]
pp opcode = 0x12 [SPI MODE]
read opcode = 0xc [SPI MODE]
erase opcode = 0x21
SPI-NOR:
1. erase entire flash: Pass
2. write entire flash: Pass
3. read entire flash: Pass
4. cmp 32MiB read back data: Pass
5. MMC: Booted Linux and dtb from mmc
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Sagar Kadam <sagar.kadam@sifive.com>
Diffstat (limited to 'arch/riscv')
| -rw-r--r-- | arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi b/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi index 8a784b5661..2aebfab646 100644 --- a/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi +++ b/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi @@ -5,6 +5,7 @@ / { aliases { + spi0 = &qspi0; spi2 = &qspi2; }; }; |