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| author | Leo Yu-Chi Liang <ycliang@andestech.com> | 2023-02-06 11:10:44 +0300 |
|---|---|---|
| committer | Leo Yu-Chi Liang <ycliang@andestech.com> | 2023-02-17 14:07:48 +0300 |
| commit | 55ca747f66742d15829f8706a633849d9013bab5 (patch) | |
| tree | 3340b10e62e06498421b39c15946c97a3dd6b477 /arch/riscv | |
| parent | daf1312b07208f231a5b27a7edecca5a7d50196b (diff) | |
| download | u-boot-55ca747f66742d15829f8706a633849d9013bab5.tar.xz | |
riscv: Remove redundant Kconfig "RISCV_NDS_CACHE"
There is no need for RISCV_NDS_CACHE config to control cache switches.
Signed-off-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Reviewed-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Rick Chen <rick@andestech.com>
Diffstat (limited to 'arch/riscv')
| -rw-r--r-- | arch/riscv/cpu/ax25/Kconfig | 10 | ||||
| -rw-r--r-- | arch/riscv/cpu/ax25/cache.c | 84 |
2 files changed, 2 insertions, 92 deletions
diff --git a/arch/riscv/cpu/ax25/Kconfig b/arch/riscv/cpu/ax25/Kconfig index 4a7295d30c..eca68ea2a7 100644 --- a/arch/riscv/cpu/ax25/Kconfig +++ b/arch/riscv/cpu/ax25/Kconfig @@ -12,13 +12,3 @@ config RISCV_NDS help Run U-Boot on AndeStar V5 platforms and use some specific features which are provided by Andes Technology AndeStar V5 families. - -if RISCV_NDS - -config RISCV_NDS_CACHE - bool "AndeStar V5 families specific cache support" - depends on RISCV_MMODE || SPL_RISCV_MMODE - help - Provide Andes Technology AndeStar V5 families specific cache support. - -endif diff --git a/arch/riscv/cpu/ax25/cache.c b/arch/riscv/cpu/ax25/cache.c index 35f23c748d..1c0c3772a1 100644 --- a/arch/riscv/cpu/ax25/cache.c +++ b/arch/riscv/cpu/ax25/cache.c @@ -67,106 +67,26 @@ void invalidate_dcache_range(unsigned long start, unsigned long end) void icache_enable(void) { -#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF) -#ifdef CONFIG_RISCV_NDS_CACHE -#if CONFIG_IS_ENABLED(RISCV_MMODE) - asm volatile ( - "csrr t1, mcache_ctl\n\t" - "ori t0, t1, 0x1\n\t" - "csrw mcache_ctl, t0\n\t" - ); -#endif -#endif -#endif } void icache_disable(void) { -#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF) -#ifdef CONFIG_RISCV_NDS_CACHE -#if CONFIG_IS_ENABLED(RISCV_MMODE) - asm volatile ( - "fence.i\n\t" - "csrr t1, mcache_ctl\n\t" - "andi t0, t1, ~0x1\n\t" - "csrw mcache_ctl, t0\n\t" - ); -#endif -#endif -#endif } void dcache_enable(void) { -#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) -#ifdef CONFIG_RISCV_NDS_CACHE -#if CONFIG_IS_ENABLED(RISCV_MMODE) - asm volatile ( - "csrr t1, mcache_ctl\n\t" - "ori t0, t1, 0x2\n\t" - "csrw mcache_ctl, t0\n\t" - ); -#endif -#ifdef CONFIG_V5L2_CACHE - _cache_enable(); -#endif -#endif -#endif } void dcache_disable(void) { -#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) -#ifdef CONFIG_RISCV_NDS_CACHE -#if CONFIG_IS_ENABLED(RISCV_MMODE) - csr_write(CCTL_REG_MCCTLCOMMAND_NUM, CCTL_L1D_WBINVAL_ALL); - asm volatile ( - "csrr t1, mcache_ctl\n\t" - "andi t0, t1, ~0x2\n\t" - "csrw mcache_ctl, t0\n\t" - ); -#endif -#ifdef CONFIG_V5L2_CACHE - _cache_disable(); -#endif -#endif -#endif } int icache_status(void) { - int ret = 0; - -#ifdef CONFIG_RISCV_NDS_CACHE -#if CONFIG_IS_ENABLED(RISCV_MMODE) - asm volatile ( - "csrr t1, mcache_ctl\n\t" - "andi %0, t1, 0x01\n\t" - : "=r" (ret) - : - : "memory" - ); -#endif -#endif - - return ret; + return 0; } int dcache_status(void) { - int ret = 0; - -#ifdef CONFIG_RISCV_NDS_CACHE -#if CONFIG_IS_ENABLED(RISCV_MMODE) - asm volatile ( - "csrr t1, mcache_ctl\n\t" - "andi %0, t1, 0x02\n\t" - : "=r" (ret) - : - : "memory" - ); -#endif -#endif - - return ret; + return 0; } |