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author | Samin Guo <samin.guo@starfivetech.com> | 2022-12-14 13:10:59 +0300 |
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committer | Samin Guo <samin.guo@starfivetech.com> | 2022-12-14 13:12:52 +0300 |
commit | 9b71c6f5fa0d96680a3329e24afab8b09ad685fb (patch) | |
tree | a74bf9e820fe867aec37c51ed62e9975d093db21 /arch/riscv | |
parent | 4cc82557a555cc4b99d0d5322122f7af3d798e59 (diff) | |
download | u-boot-9b71c6f5fa0d96680a3329e24afab8b09ad685fb.tar.xz |
board:starfive:jh7110: default cpufreq is 1000Mhz.
The frequency of pll0 is set to 1000Mhz in the bootrom
Signed-off-by: Samin Guo <samin.guo@starfivetech.com>
Diffstat (limited to 'arch/riscv')
-rw-r--r-- | arch/riscv/cpu/jh7110/pll.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/riscv/cpu/jh7110/pll.c b/arch/riscv/cpu/jh7110/pll.c index decb0eede8..563259476a 100644 --- a/arch/riscv/cpu/jh7110/pll.c +++ b/arch/riscv/cpu/jh7110/pll.c @@ -279,7 +279,7 @@ static u64 pll_get_rate(enum starfive_pll_type pll, fbdiv = GET_PLL(PLL0, FBDIV); postdiv1 = 1 << GET_PLL(PLL0, POSTDIV1); frac = GET_PLL(PLL0, FRAC); - deffreq = 1250000000; + deffreq = 1000000000; break; case PLL1: |