diff options
author | andy.hu <andy.hu@starfivetech.com> | 2023-01-06 09:41:29 +0300 |
---|---|---|
committer | andy.hu <andy.hu@starfivetech.com> | 2023-01-06 09:41:29 +0300 |
commit | bfbdce9b86a2a961f953d4a1b7fc4fdf92284cf3 (patch) | |
tree | 4161f9976d95e12b1c48bbed21aae658b4e37327 /arch/riscv | |
parent | ea54199468d02c93c2ed1a5a9d4e5e5303feffdd (diff) | |
parent | 946b2e1ad8b4e436091fd3957492be17618459c6 (diff) | |
download | u-boot-bfbdce9b86a2a961f953d4a1b7fc4fdf92284cf3.tar.xz |
Merge branch 'CR_3049_Hibernation_mason.huo' into 'jh7110-master'
CR_3049 dts: add i2c5 and attach pmic configuration
See merge request sdk/u-boot!22
Diffstat (limited to 'arch/riscv')
-rw-r--r-- | arch/riscv/dts/jh7110.dtsi | 13 | ||||
-rw-r--r-- | arch/riscv/dts/starfive_evb.dts | 7 |
2 files changed, 20 insertions, 0 deletions
diff --git a/arch/riscv/dts/jh7110.dtsi b/arch/riscv/dts/jh7110.dtsi index fd198d01ac..9ab211748b 100644 --- a/arch/riscv/dts/jh7110.dtsi +++ b/arch/riscv/dts/jh7110.dtsi @@ -659,6 +659,19 @@ status = "disabled"; }; + i2c5: i2c5@12050000 { + compatible = "snps,designware-i2c"; + reg = <0x0 0x12050000 0x0 0x10000>; + clocks = <&clkgen JH7110_I2C5_CLK_CORE>, + <&clkgen JH7110_I2C5_CLK_APB>; + clock-names = "ref", "pclk"; + resets = <&rstgen RSTN_U5_DW_I2C_APB>; + interrupts = <50>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + /* unremovable emmc as mmcblk0 */ sdio0: sdio0@16010000 { compatible = "snps,dw-mshc"; diff --git a/arch/riscv/dts/starfive_evb.dts b/arch/riscv/dts/starfive_evb.dts index 1a7b48e684..d3663b6973 100644 --- a/arch/riscv/dts/starfive_evb.dts +++ b/arch/riscv/dts/starfive_evb.dts @@ -171,3 +171,10 @@ &pdm { status = "disabled"; }; + +&i2c5 { + pmic_axp15060: axp15060_reg@36 { + compatible = "stf,axp15060-regulator"; + reg = <0x36>; + }; +}; |