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authorBin Meng <bmeng.cn@gmail.com>2017-10-19 04:20:56 +0300
committerBin Meng <bmeng.cn@gmail.com>2017-10-27 10:13:47 +0300
commitfb2c53091ff457ce8a0b547f37e7374d10d855ea (patch)
treef23702116791721129beca28eb990b8ce725bee9 /arch/x86/Kconfig
parentaa9c5956c9b921f3745e024d1572fd3dcc283091 (diff)
downloadu-boot-fb2c53091ff457ce8a0b547f37e7374d10d855ea.tar.xz
Revert "x86: fsp: Configure SPI opcode registers before SPI is locked down"
This reverts commit 1e6ebee667da47fd3a87839a239a7574c66f5659. It's not appropriate to call the Intel SPI driver specific stuff in the FSP codes. We may add a simple DTS property "intel,spi-lock-down" and let the Intel SPI driver call these stuff instead. Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Diffstat (limited to 'arch/x86/Kconfig')
-rw-r--r--arch/x86/Kconfig9
1 files changed, 0 insertions, 9 deletions
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index b2ae865c72..98c56ad7dc 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -402,15 +402,6 @@ config FSP_BROKEN_HOB
do not overwrite the important boot service data which is used by
FSP, otherwise the subsequent call to fsp_notify() will fail.
-config FSP_LOCKDOWN_SPI
- bool
- depends on HAVE_FSP
- help
- Some Intel FSP (like Braswell) does SPI lock-down during the call
- to fsp_notify(INIT_PHASE_BOOT). This option should be turned on
- for such FSP and U-Boot will configure the SPI opcode registers
- before the lock-down.
-
config ENABLE_MRC_CACHE
bool "Enable MRC cache"
depends on !EFI && !SYS_COREBOOT