diff options
| author | Simon Glass <sjg@chromium.org> | 2020-07-10 03:43:17 +0300 |
|---|---|---|
| committer | Bin Meng <bmeng.cn@gmail.com> | 2020-07-17 09:32:24 +0300 |
| commit | 0990c894cc2e8e94a2b049e4c83d484d0b3afd9c (patch) | |
| tree | e797cbeef5ba4fb68a87501773d48a8fba228351 /arch/x86/cpu | |
| parent | ef5f5f6ca691ac0b08dfae45f8723668a9fc46b6 (diff) | |
| download | u-boot-0990c894cc2e8e94a2b049e4c83d484d0b3afd9c.tar.xz | |
x86: fsp: Support a warning message when DRAM init is slow
With DDR4, Intel SOCs take quite a long time to init their memory. During
this time, if the user is watching, it looks like SPL has hung. Add a
message in this case.
This works by adding a return code to fspm_update_config() that indicates
whether MRC data was found and a new property to the device tree.
Also add one more debug message while starting.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Diffstat (limited to 'arch/x86/cpu')
| -rw-r--r-- | arch/x86/cpu/apollolake/fsp_m.c | 12 |
1 files changed, 10 insertions, 2 deletions
diff --git a/arch/x86/cpu/apollolake/fsp_m.c b/arch/x86/cpu/apollolake/fsp_m.c index 1301100cd5..65461d85b8 100644 --- a/arch/x86/cpu/apollolake/fsp_m.c +++ b/arch/x86/cpu/apollolake/fsp_m.c @@ -16,10 +16,14 @@ int fspm_update_config(struct udevice *dev, struct fspm_upd *upd) { struct fsp_m_config *cfg = &upd->config; struct fspm_arch_upd *arch = &upd->arch; + int cache_ret = 0; ofnode node; + int ret; arch->nvs_buffer_ptr = NULL; - prepare_mrc_cache(upd); + cache_ret = prepare_mrc_cache(upd); + if (cache_ret && cache_ret != -ENOENT) + return log_msg_ret("mrc", cache_ret); arch->stack_base = (void *)0xfef96000; arch->boot_loader_tolum_size = 0; arch->boot_mode = FSP_BOOT_WITH_FULL_CONFIGURATION; @@ -28,7 +32,11 @@ int fspm_update_config(struct udevice *dev, struct fspm_upd *upd) if (!ofnode_valid(node)) return log_msg_ret("fsp-m settings", -ENOENT); - return fsp_m_update_config_from_dtb(node, cfg); + ret = fsp_m_update_config_from_dtb(node, cfg); + if (ret) + return log_msg_ret("dtb", cache_ret); + + return cache_ret; } /* |