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authorSimon Glass <sjg@chromium.org>2020-07-17 17:48:22 +0300
committerBin Meng <bmeng.cn@gmail.com>2020-07-20 04:46:46 +0300
commit240752c612e61222f79c4514210f7be44854f4ca (patch)
tree6286a30c29275ffb1f8223f70f39aa031f0bb2dc /arch/x86/cpu
parent0538d6833cc61722ee506fab4609d9c1cf010491 (diff)
downloadu-boot-240752c612e61222f79c4514210f7be44854f4ca.tar.xz
x86: mtrr: Use MP calls to list the MTRRs
Update the mtrr command to use mp_run_on_cpus() to obtain its information. Since the selected CPU is the boot CPU this does not change the result, but it sets the stage for supporting other CPUs. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Diffstat (limited to 'arch/x86/cpu')
-rw-r--r--arch/x86/cpu/mtrr.c11
1 files changed, 11 insertions, 0 deletions
diff --git a/arch/x86/cpu/mtrr.c b/arch/x86/cpu/mtrr.c
index 7ec0733337..c9b4e7d06e 100644
--- a/arch/x86/cpu/mtrr.c
+++ b/arch/x86/cpu/mtrr.c
@@ -21,6 +21,7 @@
#include <log.h>
#include <asm/cache.h>
#include <asm/io.h>
+#include <asm/mp.h>
#include <asm/msr.h>
#include <asm/mtrr.h>
@@ -63,6 +64,16 @@ static void set_var_mtrr(uint reg, uint type, uint64_t start, uint64_t size)
wrmsrl(MTRR_PHYS_MASK_MSR(reg), mask | MTRR_PHYS_MASK_VALID);
}
+void mtrr_read_all(struct mtrr_info *info)
+{
+ int i;
+
+ for (i = 0; i < MTRR_COUNT; i++) {
+ info->mtrr[i].base = native_read_msr(MTRR_PHYS_BASE_MSR(i));
+ info->mtrr[i].mask = native_read_msr(MTRR_PHYS_MASK_MSR(i));
+ }
+}
+
int mtrr_commit(bool do_caches)
{
struct mtrr_request *req = gd->arch.mtrr_req;