x86: apl: Use devicetree for FSP-S configuration

A the moment the FSP-S configuration is a mix of hard coded values and
devicetree properties.

This patch makes FSP-S full configurable from devicetree by
adding binding properties for all FSP-S parameters.

Co-developed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Signed-off-by: Bernhard Messerklinger <bernhard.messerklinger@br-automation.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org> (Tested on coral)
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>

2 files changed, 1195 insertions, 380 deletions

diff --git a/arch/x86/cpu/apollolake/fsp_bindings.c b/arch/x86/cpu/apollolake/fsp_bindings.c
index 6b97060b6d..9130af9ce0 100644
--- a/arch/x86/cpu/apollolake/fsp_bindings.c
+++ b/arch/x86/cpu/apollolake/fsp_bindings.c
@@ -614,3 +614,1192 @@ int fsp_m_update_config_from_dtb(ofnode node, struct fsp_m_config *cfg)
 	return fsp_update_config_from_dtb(node, (u8 *)cfg, fsp_m_bindings);
 }
 #endif
+
+#if !defined(CONFIG_SPL_BUILD) && !defined(CONFIG_TPL_BUILD)
+const struct fsp_binding fsp_s_bindings[] = {
+	{
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, active_processor_cores),
+	.propname = "fsps,active-processor-cores",
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, disable_core1),
+	.propname = "fsps,disable-core1",
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, disable_core2),
+	.propname = "fsps,disable-core2",
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, disable_core3),
+	.propname = "fsps,disable-core3",
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, vmx_enable),
+	.propname = "fsps,vmx-enable",
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, proc_trace_mem_size),
+	.propname = "fsps,proc-trace-mem-size",
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, proc_trace_enable),
+	.propname = "fsps,proc-trace-enable",
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, eist),
+	.propname = "fsps,eist",
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, boot_p_state),
+	.propname = "fsps,boot-p-state",
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, enable_cx),
+	.propname = "fsps,enable-cx",
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, c1e),
+	.propname = "fsps,c1e",
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, bi_proc_hot),
+	.propname = "fsps,bi-proc-hot",
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, pkg_c_state_limit),
+	.propname = "fsps,pkg-c-state-limit",
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, c_state_auto_demotion),
+	.propname = "fsps,c-state-auto-demotion",
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, c_state_un_demotion),
+	.propname = "fsps,c-state-un-demotion",
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, max_core_c_state),
+	.propname = "fsps,max-core-c-state",
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, pkg_c_state_demotion),
+	.propname = "fsps,pkg-c-state-demotion",
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, pkg_c_state_un_demotion),
+	.propname = "fsps,pkg-c-state-un-demotion",
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, turbo_mode),
+	.propname = "fsps,turbo-mode",
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, hda_verb_table_entry_num),
+	.propname = "fsps,hda-verb-table-entry-num",
+	}, {
+	.type = FSP_UINT32,
+	.offset = offsetof(struct fsp_s_config, hda_verb_table_ptr),
+	.propname = "fsps,hda-verb-table-ptr",
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, p2sb_unhide),
+	.propname = "fsps,p2sb-unhide",
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, ipu_en),
+	.propname = "fsps,ipu-en",
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, ipu_acpi_mode),
+	.propname = "fsps,ipu-acpi-mode",
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, force_wake),
+	.propname = "fsps,force-wake",
+	}, {
+	.type = FSP_UINT32,
+	.offset = offsetof(struct fsp_s_config, gtt_mm_adr),
+	.propname = "fsps,gtt-mm-adr",
+	}, {
+	.type = FSP_UINT32,
+	.offset = offsetof(struct fsp_s_config, gm_adr),
+	.propname = "fsps,gm-adr",
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, pavp_lock),
+	.propname = "fsps,pavp-lock",
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, graphics_freq_modify),
+	.propname = "fsps,graphics-freq-modify",
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, graphics_freq_req),
+	.propname = "fsps,graphics-freq-req",
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, graphics_video_freq),
+	.propname = "fsps,graphics-video-freq",
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, pm_lock),
+	.propname = "fsps,pm-lock",
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, dop_clock_gating),
+	.propname = "fsps,dop-clock-gating",
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, unsolicited_attack_override),
+	.propname = "fsps,unsolicited-attack-override",
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, wopcm_support),
+	.propname = "fsps,wopcm-support",
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, wopcm_size),
+	.propname = "fsps,wopcm-size",
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, power_gating),
+	.propname = "fsps,power-gating",
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, unit_level_clock_gating),
+	.propname = "fsps,unit-level-clock-gating",
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, fast_boot),
+	.propname = "fsps,fast-boot",
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, dyn_sr),
+	.propname = "fsps,dyn-sr",
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, sa_ipu_enable),
+	.propname = "fsps,sa-ipu-enable",
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, pm_support),
+	.propname = "fsps,pm-support",
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, enable_render_standby),
+	.propname = "fsps,enable-render-standby",
+	}, {
+	.type = FSP_UINT32,
+	.offset = offsetof(struct fsp_s_config, logo_size),
+	.propname = "fsps,logo-size",
+	}, {
+	.type = FSP_UINT32,
+	.offset = offsetof(struct fsp_s_config, logo_ptr),
+	.propname = "fsps,logo-ptr",
+	}, {
+	.type = FSP_UINT32,
+	.offset = offsetof(struct fsp_s_config, graphics_config_ptr),
+	.propname = "fsps,graphics-config-ptr",
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, pavp_enable),
+	.propname = "fsps,pavp-enable",
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, pavp_pr3),
+	.propname = "fsps,pavp-pr3",
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, cd_clock),
+	.propname = "fsps,cd-clock",
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, pei_graphics_peim_init),
+	.propname = "fsps,pei-graphics-peim-init",
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, write_protection_enable),
+	.propname = "fsps,write-protection-enable",
+	.count = ARRAY_SIZE_OF_MEMBER(struct fsp_s_config,
+				      write_protection_enable),
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, read_protection_enable),
+	.propname = "fsps,read-protection-enable",
+	.count = ARRAY_SIZE_OF_MEMBER(struct fsp_s_config,
+				      read_protection_enable),
+	}, {
+	.type = FSP_UINT16,
+	.offset = offsetof(struct fsp_s_config, protected_range_limit),
+	.propname = "fsps,protected-range-limit",
+	.count = ARRAY_SIZE_OF_MEMBER(struct fsp_s_config,
+				      protected_range_limit),
+	}, {
+	.type = FSP_UINT16,
+	.offset = offsetof(struct fsp_s_config, protected_range_base),
+	.propname = "fsps,protected-range-base",
+	.count = ARRAY_SIZE_OF_MEMBER(struct fsp_s_config,
+				      protected_range_base),
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, gmm),
+	.propname = "fsps,gmm",
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, clk_gating_pgcb_clk_trunk),
+	.propname = "fsps,clk-gating-pgcb-clk-trunk",
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, clk_gating_sb),
+	.propname = "fsps,clk-gating-sb",
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, clk_gating_sb_clk_trunk),
+	.propname = "fsps,clk-gating-sb-clk-trunk",
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, clk_gating_sb_clk_partition),
+	.propname = "fsps,clk-gating-sb-clk-partition",
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, clk_gating_core),
+	.propname = "fsps,clk-gating-core",
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, clk_gating_dma),
+	.propname = "fsps,clk-gating-dma",
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, clk_gating_reg_access),
+	.propname = "fsps,clk-gating-reg-access",
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, clk_gating_host),
+	.propname = "fsps,clk-gating-host",
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, clk_gating_partition),
+	.propname = "fsps,clk-gating-partition",
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, clk_gating_trunk),
+	.propname = "fsps,clk-gating-trunk",
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, hda_enable),
+	.propname = "fsps,hda-enable",
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, dsp_enable),
+	.propname = "fsps,dsp-enable",
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, pme),
+	.propname = "fsps,pme",
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, hd_audio_io_buffer_ownership),
+	.propname = "fsps,hd-audio-io-buffer-ownership",
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, hd_audio_io_buffer_voltage),
+	.propname = "fsps,hd-audio-io-buffer-voltage",
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, hd_audio_vc_type),
+	.propname = "fsps,hd-audio-vc-type",
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, hd_audio_link_frequency),
+	.propname = "fsps,hd-audio-link-frequency",
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, hd_audio_i_disp_link_frequency),
+	.propname = "fsps,hd-audio-i-disp-link-frequency",
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, hd_audio_i_disp_link_tmode),
+	.propname = "fsps,hd-audio-i-disp-link-tmode",
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, dsp_endpoint_dmic),
+	.propname = "fsps,dsp-endpoint-dmic",
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, dsp_endpoint_bluetooth),
+	.propname = "fsps,dsp-endpoint-bluetooth",
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, dsp_endpoint_i2s_skp),
+	.propname = "fsps,dsp-endpoint-i2s-skp",
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, dsp_endpoint_i2s_hp),
+	.propname = "fsps,dsp-endpoint-i2s-hp",
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, audio_ctl_pwr_gate),
+	.propname = "fsps,audio-ctl-pwr-gate",
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, audio_dsp_pwr_gate),
+	.propname = "fsps,audio-dsp-pwr-gate",
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, mmt),
+	.propname = "fsps,mmt",
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, hmt),
+	.propname = "fsps,hmt",
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, hd_audio_pwr_gate),
+	.propname = "fsps,hd-audio-pwr-gate",
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, hd_audio_clk_gate),
+	.propname = "fsps,hd-audio-clk-gate",
+	}, {
+	.type = FSP_UINT32,
+	.offset = offsetof(struct fsp_s_config, dsp_feature_mask),
+	.propname = "fsps,dsp-feature-mask",
+	}, {
+	.type = FSP_UINT32,
+	.offset = offsetof(struct fsp_s_config, dsp_pp_module_mask),
+	.propname = "fsps,dsp-pp-module-mask",
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, bios_cfg_lock_down),
+	.propname = "fsps,bios-cfg-lock-down",
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, hpet),
+	.propname = "fsps,hpet",
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, hpet_bdf_valid),
+	.propname = "fsps,hpet-bdf-valid",
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, hpet_bus_number),
+	.propname = "fsps,hpet-bus-number",
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, hpet_device_number),
+	.propname = "fsps,hpet-device-number",
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, hpet_function_number),
+	.propname = "fsps,hpet-function-number",
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, io_apic_bdf_valid),
+	.propname = "fsps,io-apic-bdf-valid",
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, io_apic_bus_number),
+	.propname = "fsps,io-apic-bus-number",
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, io_apic_device_number),
+	.propname = "fsps,io-apic-device-number",
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, io_apic_function_number),
+	.propname = "fsps,io-apic-function-number",
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, io_apic_entry24_119),
+	.propname = "fsps,io-apic-entry24-119",
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, io_apic_id),
+	.propname = "fsps,io-apic-id",
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, io_apic_range_select),
+	.propname = "fsps,io-apic-range-select",
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, ish_enable),
+	.propname = "fsps,ish-enable",
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, bios_interface),
+	.propname = "fsps,bios-interface",
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, bios_lock),
+	.propname = "fsps,bios-lock",
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, spi_eiss),
+	.propname = "fsps,spi-eiss",
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, bios_lock_sw_smi_number),
+	.propname = "fsps,bios-lock-sw-smi-number",
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, lpss_s0ix_enable),
+	.propname = "fsps,lpss-s0ix-enable",
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, i2c_clk_gate_cfg),
+	.propname = "fsps,i2c-clk-gate-cfg",
+	.count = ARRAY_SIZE_OF_MEMBER(struct fsp_s_config, i2c_clk_gate_cfg),
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, hsuart_clk_gate_cfg),
+	.propname = "fsps,hsuart-clk-gate-cfg",
+	.count = ARRAY_SIZE_OF_MEMBER(struct fsp_s_config, hsuart_clk_gate_cfg),
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, spi_clk_gate_cfg),
+	.propname = "fsps,spi-clk-gate-cfg",
+	.count = ARRAY_SIZE_OF_MEMBER(struct fsp_s_config, spi_clk_gate_cfg),
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, i2c0_enable),
+	.propname = "fsps,i2c0-enable",
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, i2c1_enable),
+	.propname = "fsps,i2c1-enable",
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, i2c2_enable),
+	.propname = "fsps,i2c2-enable",
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, i2c3_enable),
+	.propname = "fsps,i2c3-enable",
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, i2c4_enable),
+	.propname = "fsps,i2c4-enable",
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, i2c5_enable),
+	.propname = "fsps,i2c5-enable",
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, i2c6_enable),
+	.propname = "fsps,i2c6-enable",
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, i2c7_enable),
+	.propname = "fsps,i2c7-enable",
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, hsuart0_enable),
+	.propname = "fsps,hsuart0-enable",
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, hsuart1_enable),
+	.propname = "fsps,hsuart1-enable",
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, hsuart2_enable),
+	.propname = "fsps,hsuart2-enable",
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, hsuart3_enable),
+	.propname = "fsps,hsuart3-enable",
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, spi0_enable),
+	.propname = "fsps,spi0-enable",
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, spi1_enable),
+	.propname = "fsps,spi1-enable",
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, spi2_enable),
+	.propname = "fsps,spi2-enable",
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, os_dbg_enable),
+	.propname = "fsps,os-dbg-enable",
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, dci_en),
+	.propname = "fsps,dci-en",
+	}, {
+	.type = FSP_UINT32,
+	.offset = offsetof(struct fsp_s_config,
+			   uart2_kernel_debug_base_address),
+	.propname = "fsps,uart2-kernel-debug-base-address",
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, pcie_clock_gating_disabled),
+	.propname = "fsps,pcie-clock-gating-disabled",
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, pcie_root_port8xh_decode),
+	.propname = "fsps,pcie-root-port8xh-decode",
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, pcie8xh_decode_port_index),
+	.propname = "fsps,pcie8xh-decode-port-index",
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config,
+			   pcie_root_port_peer_memory_write_enable),
+	.propname = "fsps,pcie-root-port-peer-memory-write-enable",
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, pcie_aspm_sw_smi_number),
+	.propname = "fsps,pcie-aspm-sw-smi-number",
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, pcie_root_port_en),
+	.propname = "fsps,pcie-root-port-en",
+	.count = ARRAY_SIZE_OF_MEMBER(struct fsp_s_config, pcie_root_port_en),
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, pcie_rp_hide),
+	.propname = "fsps,pcie-rp-hide",
+	.count = ARRAY_SIZE_OF_MEMBER(struct fsp_s_config, pcie_rp_hide),
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, pcie_rp_slot_implemented),
+	.propname = "fsps,pcie-rp-slot-implemented",
+	.count = ARRAY_SIZE_OF_MEMBER(struct fsp_s_config,
+				      pcie_rp_slot_implemented),
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, pcie_rp_hot_plug),
+	.propname = "fsps,pcie-rp-hot-plug",
+	.count = ARRAY_SIZE_OF_MEMBER(struct fsp_s_config, pcie_rp_hot_plug),
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, pcie_rp_pm_sci),
+	.propname = "fsps,pcie-rp-pm-sci",
+	.count = ARRAY_SIZE_OF_MEMBER(struct fsp_s_config, pcie_rp_pm_sci),
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, pcie_rp_ext_sync),
+	.propname = "fsps,pcie-rp-ext-sync",
+	.count = ARRAY_SIZE_OF_MEMBER(struct fsp_s_config, pcie_rp_ext_sync),
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config,
+			   pcie_rp_transmitter_half_swing),
+	.propname = "fsps,pcie-rp-transmitter-half-swing",
+	.count = ARRAY_SIZE_OF_MEMBER(struct fsp_s_config,
+				      pcie_rp_transmitter_half_swing),
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, pcie_rp_acs_enabled),
+	.propname = "fsps,pcie-rp-acs-enabled",
+	.count = ARRAY_SIZE_OF_MEMBER(struct fsp_s_config, pcie_rp_acs_enabled),
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, pcie_rp_clk_req_supported),
+	.propname = "fsps,pcie-rp-clk-req-supported",
+	.count = ARRAY_SIZE_OF_MEMBER(struct fsp_s_config,
+				      pcie_rp_clk_req_supported),
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, pcie_rp_clk_req_number),
+	.propname = "fsps,pcie-rp-clk-req-number",
+	.count = ARRAY_SIZE_OF_MEMBER(struct fsp_s_config,
+				      pcie_rp_clk_req_number),
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, pcie_rp_clk_req_detect),
+	.propname = "fsps,pcie-rp-clk-req-detect",
+	.count = ARRAY_SIZE_OF_MEMBER(struct fsp_s_config,
+				      pcie_rp_clk_req_detect),
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, advanced_error_reporting),
+	.propname = "fsps,advanced-error-reporting",
+	.count = ARRAY_SIZE_OF_MEMBER(struct fsp_s_config,
+				      advanced_error_reporting),
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, pme_interrupt),
+	.propname = "fsps,pme-interrupt",
+	.count = ARRAY_SIZE_OF_MEMBER(struct fsp_s_config, pme_interrupt),
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, unsupported_request_report),
+	.propname = "fsps,unsupported-request-report",
+	.count = ARRAY_SIZE_OF_MEMBER(struct fsp_s_config,
+				      unsupported_request_report),
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, fatal_error_report),
+	.propname = "fsps,fatal-error-report",
+	.count = ARRAY_SIZE_OF_MEMBER(struct fsp_s_config, fatal_error_report),
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, no_fatal_error_report),
+	.propname = "fsps,no-fatal-error-report",
+	.count = ARRAY_SIZE_OF_MEMBER(struct fsp_s_config,
+				      no_fatal_error_report),
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, correctable_error_report),
+	.propname = "fsps,correctable-error-report",
+	.count = ARRAY_SIZE_OF_MEMBER(struct fsp_s_config,
+				      correctable_error_report),
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config,
+			   system_error_on_fatal_error),
+	.propname = "fsps,system-error-on-fatal-error",
+	.count = ARRAY_SIZE_OF_MEMBER(struct fsp_s_config,
+				      system_error_on_fatal_error),
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config,
+			   system_error_on_non_fatal_error),
+	.propname = "fsps,system-error-on-non-fatal-error",
+	.count = ARRAY_SIZE_OF_MEMBER(struct fsp_s_config,
+				      system_error_on_non_fatal_error),
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config,
+			   system_error_on_correctable_error),
+	.propname = "fsps,system-error-on-correctable-error",
+	.count = ARRAY_SIZE_OF_MEMBER(struct fsp_s_config,
+				      system_error_on_correctable_error),
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, pcie_rp_speed),
+	.propname = "fsps,pcie-rp-speed",
+	.count = ARRAY_SIZE_OF_MEMBER(struct fsp_s_config, pcie_rp_speed),
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, physical_slot_number),
+	.propname = "fsps,physical-slot-number",
+	.count = ARRAY_SIZE_OF_MEMBER(struct fsp_s_config,
+				      physical_slot_number),
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, pcie_rp_completion_timeout),
+	.propname = "fsps,pcie-rp-completion-timeout",
+	.count = ARRAY_SIZE_OF_MEMBER(struct fsp_s_config,
+				      pcie_rp_completion_timeout),
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, ptm_enable),
+	.propname = "fsps,ptm-enable",
+	.count = ARRAY_SIZE_OF_MEMBER(struct fsp_s_config, ptm_enable),
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, pcie_rp_aspm),
+	.propname = "fsps,pcie-rp-aspm",
+	.count = ARRAY_SIZE_OF_MEMBER(struct fsp_s_config, pcie_rp_aspm),
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, pcie_rp_l1_substates),
+	.propname = "fsps,pcie-rp-l1-substates",
+	.count = ARRAY_SIZE_OF_MEMBER(struct fsp_s_config,
+				      pcie_rp_l1_substates),
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, pcie_rp_ltr_enable),
+	.propname = "fsps,pcie-rp-ltr-enable",
+	.count = ARRAY_SIZE_OF_MEMBER(struct fsp_s_config, pcie_rp_ltr_enable),
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, pcie_rp_ltr_config_lock),
+	.propname = "fsps,pcie-rp-ltr-config-lock",
+	.count = ARRAY_SIZE_OF_MEMBER(struct fsp_s_config,
+				      pcie_rp_ltr_config_lock),
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, pme_b0_s5_dis),
+	.propname = "fsps,pme-b0-s5-dis",
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, pci_clock_run),
+	.propname = "fsps,pci-clock-run",
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, timer8254_clk_setting),
+	.propname = "fsps,timer8254-clk-setting",
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, enable_sata),
+	.propname = "fsps,enable-sata",
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, sata_mode),
+	.propname = "fsps,sata-mode",
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, sata_salp_support),
+	.propname = "fsps,sata-salp-support",
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, sata_pwr_opt_enable),
+	.propname = "fsps,sata-pwr-opt-enable",
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, e_sata_speed_limit),
+	.propname = "fsps,e-sata-speed-limit",
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, speed_limit),
+	.propname = "fsps,speed-limit",
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, sata_ports_enable),
+	.propname = "fsps,sata-ports-enable",
+	.count = ARRAY_SIZE_OF_MEMBER(struct fsp_s_config, sata_ports_enable),
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, sata_ports_dev_slp),
+	.propname = "fsps,sata-ports-dev-slp",
+	.count = ARRAY_SIZE_OF_MEMBER(struct fsp_s_config, sata_ports_dev_slp),
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, sata_ports_hot_plug),
+	.propname = "fsps,sata-ports-hot-plug",
+	.count = ARRAY_SIZE_OF_MEMBER(struct fsp_s_config, sata_ports_hot_plug),
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, sata_ports_interlock_sw),
+	.propname = "fsps,sata-ports-interlock-sw",
+	.count = ARRAY_SIZE_OF_MEMBER(struct fsp_s_config,
+				      sata_ports_interlock_sw),
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, sata_ports_external),
+	.propname = "fsps,sata-ports-external",
+	.count = ARRAY_SIZE_OF_MEMBER(struct fsp_s_config, sata_ports_external),
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, sata_ports_spin_up),
+	.propname = "fsps,sata-ports-spin-up",
+	.count = ARRAY_SIZE_OF_MEMBER(struct fsp_s_config, sata_ports_spin_up),
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, sata_ports_solid_state_drive),
+	.propname = "fsps,sata-ports-solid-state-drive",
+	.count = ARRAY_SIZE_OF_MEMBER(struct fsp_s_config,
+				      sata_ports_solid_state_drive),
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, sata_ports_enable_dito_config),
+	.propname = "fsps,sata-ports-enable-dito-config",
+	.count = ARRAY_SIZE_OF_MEMBER(struct fsp_s_config,
+				      sata_ports_enable_dito_config),
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, sata_ports_dm_val),
+	.propname = "fsps,sata-ports-dm-val",
+	.count = ARRAY_SIZE_OF_MEMBER(struct fsp_s_config, sata_ports_dm_val),
+	}, {
+	.type = FSP_UINT16,
+	.offset = offsetof(struct fsp_s_config, sata_ports_dito_val),
+	.propname = "fsps,sata-ports-dito-val",
+	.count = ARRAY_SIZE_OF_MEMBER(struct fsp_s_config, sata_ports_dito_val),
+	}, {
+	.type = FSP_UINT16,
+	.offset = offsetof(struct fsp_s_config, sub_system_vendor_id),
+	.propname = "fsps,sub-system-vendor-id",
+	}, {
+	.type = FSP_UINT16,
+	.offset = offsetof(struct fsp_s_config, sub_system_id),
+	.propname = "fsps,sub-system-id",
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, crid_settings),
+	.propname = "fsps,crid-settings",
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, reset_select),
+	.propname = "fsps,reset-select",
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, sdcard_enabled),
+	.propname = "fsps,sdcard-enabled",
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, e_mmc_enabled),
+	.propname = "fsps,e-mmc-enabled",
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, e_mmc_host_max_speed),
+	.propname = "fsps,e-mmc-host-max-speed",
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, ufs_enabled),
+	.propname = "fsps,ufs-enabled",
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, sdio_enabled),
+	.propname = "fsps,sdio-enabled",
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, gpp_lock),
+	.propname = "fsps,gpp-lock",
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, sirq_enable),
+	.propname = "fsps,sirq-enable",
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, sirq_mode),
+	.propname = "fsps,sirq-mode",
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, start_frame_pulse),
+	.propname = "fsps,start-frame-pulse",
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, smbus_enable),
+	.propname = "fsps,smbus-enable",
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, arp_enable),
+	.propname = "fsps,arp-enable",
+	}, {
+	.type = FSP_UINT16,
+	.offset = offsetof(struct fsp_s_config, num_rsvd_smbus_addresses),
+	.propname = "fsps,num-rsvd-smbus-addresses",
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, rsvd_smbus_address_table),
+	.propname = "fsps,rsvd-smbus-address-table",
+	.count = ARRAY_SIZE_OF_MEMBER(struct fsp_s_config,
+				      rsvd_smbus_address_table),
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, disable_compliance_mode),
+	.propname = "fsps,disable-compliance-mode",
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, usb_per_port_ctl),
+	.propname = "fsps,usb-per-port-ctl",
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, usb30_mode),
+	.propname = "fsps,usb30-mode",
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, port_usb20_enable),
+	.propname = "fsps,port-usb20-enable",
+	.count = ARRAY_SIZE_OF_MEMBER(struct fsp_s_config, port_usb20_enable),
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, port_us20b_over_current_pin),
+	.propname = "fsps,port-us20b-over-current-pin",
+	.count = ARRAY_SIZE_OF_MEMBER(struct fsp_s_config,
+				      port_us20b_over_current_pin),
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, usb_otg),
+	.propname = "fsps,usb-otg",
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, hsic_support_enable),
+	.propname = "fsps,hsic-support-enable",
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, port_usb30_enable),
+	.propname = "fsps,port-usb30-enable",
+	.count = ARRAY_SIZE_OF_MEMBER(struct fsp_s_config, port_usb30_enable),
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, port_us30b_over_current_pin),
+	.propname = "fsps,port-us30b-over-current-pin",
+	.count = ARRAY_SIZE_OF_MEMBER(struct fsp_s_config,
+				      port_us30b_over_current_pin),
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, ssic_port_enable),
+	.propname = "fsps,ssic-port-enable",
+	.count = ARRAY_SIZE_OF_MEMBER(struct fsp_s_config, ssic_port_enable),
+	}, {
+	.type = FSP_UINT16,
+	.offset = offsetof(struct fsp_s_config, dlane_pwr_gating),
+	.propname = "fsps,dlane-pwr-gating",
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, vtd_enable),
+	.propname = "fsps,vtd-enable",
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, lock_down_global_smi),
+	.propname = "fsps,lock-down-global-smi",
+	}, {
+	.type = FSP_UINT16,
+	.offset = offsetof(struct fsp_s_config, reset_wait_timer),
+	.propname = "fsps,reset-wait-timer",
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, rtc_lock),
+	.propname = "fsps,rtc-lock",
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, sata_test_mode),
+	.propname = "fsps,sata-test-mode",
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, ssic_rate),
+	.propname = "fsps,ssic-rate",
+	.count = ARRAY_SIZE_OF_MEMBER(struct fsp_s_config, ssic_rate),
+	}, {
+	.type = FSP_UINT16,
+	.offset = offsetof(struct fsp_s_config, dynamic_power_gating),
+	.propname = "fsps,dynamic-power-gating",
+	}, {
+	.type = FSP_UINT16,
+	.offset = offsetof(struct fsp_s_config, pcie_rp_ltr_max_snoop_latency),
+	.propname = "fsps,pcie-rp-ltr-max-snoop-latency",
+	.count = ARRAY_SIZE_OF_MEMBER(struct fsp_s_config,
+				      pcie_rp_ltr_max_snoop_latency),
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config,
+			   pcie_rp_snoop_latency_override_mode),
+	.propname = "fsps,pcie-rp-snoop-latency-override-mode",
+	.count = ARRAY_SIZE_OF_MEMBER(struct fsp_s_config,
+				      pcie_rp_snoop_latency_override_mode),
+	}, {
+	.type = FSP_UINT16,
+	.offset = offsetof(struct fsp_s_config,
+			   pcie_rp_snoop_latency_override_value),
+	.propname = "fsps,pcie-rp-snoop-latency-override-value",
+	.count = ARRAY_SIZE_OF_MEMBER(struct fsp_s_config,
+				      pcie_rp_snoop_latency_override_value),
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config,
+			   pcie_rp_snoop_latency_override_multiplier),
+	.propname = "fsps,pcie-rp-snoop-latency-override-multiplier",
+	.count = ARRAY_SIZE_OF_MEMBER(struct fsp_s_config,
+				      pcie_rp_snoop_latency_override_multiplier),
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, skip_mp_init),
+	.propname = "fsps,skip-mp-init",
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, dci_auto_detect),
+	.propname = "fsps,dci-auto-detect",
+	}, {
+	.type = FSP_UINT16,
+	.offset = offsetof(struct fsp_s_config,
+			   pcie_rp_ltr_max_non_snoop_latency),
+	.propname = "fsps,pcie-rp-ltr-max-non-snoop-latency",
+	.count = ARRAY_SIZE_OF_MEMBER(struct fsp_s_config,
+				      pcie_rp_ltr_max_non_snoop_latency),
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config,
+			   pcie_rp_non_snoop_latency_override_mode),
+	.propname = "fsps,pcie-rp-non-snoop-latency-override-mode",
+	.count = ARRAY_SIZE_OF_MEMBER(struct fsp_s_config,
+				      pcie_rp_non_snoop_latency_override_mode),
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, tco_timer_halt_lock),
+	.propname = "fsps,tco-timer-halt-lock",
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, pwr_btn_override_period),
+	.propname = "fsps,pwr-btn-override-period",
+	}, {
+	.type = FSP_UINT16,
+	.offset = offsetof(struct fsp_s_config,
+			   pcie_rp_non_snoop_latency_override_value),
+	.propname = "fsps,pcie-rp-non-snoop-latency-override-value",
+	.count = ARRAY_SIZE_OF_MEMBER(struct fsp_s_config,
+				      pcie_rp_non_snoop_latency_override_value),
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config,
+			   pcie_rp_non_snoop_latency_override_multiplier),
+	.propname = "fsps,pcie-rp-non-snoop-latency-override-multiplier",
+	.count = ARRAY_SIZE_OF_MEMBER(struct fsp_s_config,
+				pcie_rp_non_snoop_latency_override_multiplier),
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, pcie_rp_slot_power_limit_scale),
+	.propname = "fsps,pcie-rp-slot-power-limit-scale",
+	.count = ARRAY_SIZE_OF_MEMBER(struct fsp_s_config,
+				      pcie_rp_slot_power_limit_scale),
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, pcie_rp_slot_power_limit_value),
+	.propname = "fsps,pcie-rp-slot-power-limit-value",
+	.count = ARRAY_SIZE_OF_MEMBER(struct fsp_s_config,
+				      pcie_rp_slot_power_limit_value),
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, disable_native_power_button),
+	.propname = "fsps,disable-native-power-button",
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, power_butter_debounce_mode),
+	.propname = "fsps,power-butter-debounce-mode",
+	}, {
+	.type = FSP_UINT32,
+	.offset = offsetof(struct fsp_s_config, sdio_tx_cmd_cntl),
+	.propname = "fsps,sdio-tx-cmd-cntl",
+	}, {
+	.type = FSP_UINT32,
+	.offset = offsetof(struct fsp_s_config, sdio_tx_data_cntl1),
+	.propname = "fsps,sdio-tx-data-cntl1",
+	}, {
+	.type = FSP_UINT32,
+	.offset = offsetof(struct fsp_s_config, sdio_tx_data_cntl2),
+	.propname = "fsps,sdio-tx-data-cntl2",
+	}, {
+	.type = FSP_UINT32,
+	.offset = offsetof(struct fsp_s_config, sdio_rx_cmd_data_cntl1),
+	.propname = "fsps,sdio-rx-cmd-data-cntl1",
+	}, {
+	.type = FSP_UINT32,
+	.offset = offsetof(struct fsp_s_config, sdio_rx_cmd_data_cntl2),
+	.propname = "fsps,sdio-rx-cmd-data-cntl2",
+	}, {
+	.type = FSP_UINT32,
+	.offset = offsetof(struct fsp_s_config, sdcard_tx_cmd_cntl),
+	.propname = "fsps,sdcard-tx-cmd-cntl",
+	}, {
+	.type = FSP_UINT32,
+	.offset = offsetof(struct fsp_s_config, sdcard_tx_data_cntl1),
+	.propname = "fsps,sdcard-tx-data-cntl1",
+	}, {
+	.type = FSP_UINT32,
+	.offset = offsetof(struct fsp_s_config, sdcard_tx_data_cntl2),
+	.propname = "fsps,sdcard-tx-data-cntl2",
+	}, {
+	.type = FSP_UINT32,
+	.offset = offsetof(struct fsp_s_config, sdcard_rx_cmd_data_cntl1),
+	.propname = "fsps,sdcard-rx-cmd-data-cntl1",
+	}, {
+	.type = FSP_UINT32,
+	.offset = offsetof(struct fsp_s_config, sdcard_rx_strobe_cntl),
+	.propname = "fsps,sdcard-rx-strobe-cntl",
+	}, {
+	.type = FSP_UINT32,
+	.offset = offsetof(struct fsp_s_config, sdcard_rx_cmd_data_cntl2),
+	.propname = "fsps,sdcard-rx-cmd-data-cntl2",
+	}, {
+	.type = FSP_UINT32,
+	.offset = offsetof(struct fsp_s_config, emmc_tx_cmd_cntl),
+	.propname = "fsps,emmc-tx-cmd-cntl",
+	}, {
+	.type = FSP_UINT32,
+	.offset = offsetof(struct fsp_s_config, emmc_tx_data_cntl1),
+	.propname = "fsps,emmc-tx-data-cntl1",
+	}, {
+	.type = FSP_UINT32,
+	.offset = offsetof(struct fsp_s_config, emmc_tx_data_cntl2),
+	.propname = "fsps,emmc-tx-data-cntl2",
+	}, {
+	.type = FSP_UINT32,
+	.offset = offsetof(struct fsp_s_config, emmc_rx_cmd_data_cntl1),
+	.propname = "fsps,emmc-rx-cmd-data-cntl1",
+	}, {
+	.type = FSP_UINT32,
+	.offset = offsetof(struct fsp_s_config, emmc_rx_strobe_cntl),
+	.propname = "fsps,emmc-rx-strobe-cntl",
+	}, {
+	.type = FSP_UINT32,
+	.offset = offsetof(struct fsp_s_config, emmc_rx_cmd_data_cntl2),
+	.propname = "fsps,emmc-rx-cmd-data-cntl2",
+	}, {
+	.type = FSP_UINT32,
+	.offset = offsetof(struct fsp_s_config, emmc_master_sw_cntl),
+	.propname = "fsps,emmc-master-sw-cntl",
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, pcie_rp_selectable_deemphasis),
+	.propname = "fsps,pcie-rp-selectable-deemphasis",
+	.count = ARRAY_SIZE_OF_MEMBER(struct fsp_s_config,
+				      pcie_rp_selectable_deemphasis),
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, monitor_mwait_enable),
+	.propname = "fsps,monitor-mwait-enable",
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, hd_audio_dsp_uaa_compliance),
+	.propname = "fsps,hd-audio-dsp-uaa-compliance",
+	}, {
+	.type = FSP_UINT32,
+	.offset = offsetof(struct fsp_s_config, ipc),
+	.propname = "fsps,ipc",
+	.count = ARRAY_SIZE_OF_MEMBER(struct fsp_s_config, ipc),
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, sata_ports_disable_dynamic_pg),
+	.propname = "fsps,sata-ports-disable-dynamic-pg",
+	.count = ARRAY_SIZE_OF_MEMBER(struct fsp_s_config,
+				      sata_ports_disable_dynamic_pg),
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, init_s3_cpu),
+	.propname = "fsps,init-s3-cpu",
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, skip_punit_init),
+	.propname = "fsps,skip-punit-init",
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, port_usb20_per_port_tx_pe_half),
+	.propname = "fsps,port-usb20-per-port-tx-pe-half",
+	.count = ARRAY_SIZE_OF_MEMBER(struct fsp_s_config,
+				      port_usb20_per_port_tx_pe_half),
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, port_usb20_per_port_pe_txi_set),
+	.propname = "fsps,port-usb20-per-port-pe-txi-set",
+	.count = ARRAY_SIZE_OF_MEMBER(struct fsp_s_config,
+				      port_usb20_per_port_pe_txi_set),
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, port_usb20_per_port_txi_set),
+	.propname = "fsps,port-usb20-per-port-txi-set",
+	.count = ARRAY_SIZE_OF_MEMBER(struct fsp_s_config,
+				      port_usb20_per_port_txi_set),
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, port_usb20_hs_skew_sel),
+	.propname = "fsps,port-usb20-hs-skew-sel",
+	.count = ARRAY_SIZE_OF_MEMBER(struct fsp_s_config,
+				      port_usb20_hs_skew_sel),
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config,
+			   port_usb20_i_usb_tx_emphasis_en),
+	.propname = "fsps,port-usb20-i-usb-tx-emphasis-en",
+	.count = ARRAY_SIZE_OF_MEMBER(struct fsp_s_config,
+				      port_usb20_i_usb_tx_emphasis_en),
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config,
+			   port_usb20_per_port_rxi_set),
+	.propname = "fsps,port-usb20-per-port-rxi-set",
+	.count = ARRAY_SIZE_OF_MEMBER(struct fsp_s_config,
+				      port_usb20_per_port_rxi_set),
+	}, {
+	.type = FSP_UINT8,
+	.offset = offsetof(struct fsp_s_config, port_usb20_hs_npre_drv_sel),
+	.propname = "fsps,port-usb20-hs-npre-drv-sel",
+	.count = ARRAY_SIZE_OF_MEMBER(struct fsp_s_config,
+				      port_usb20_hs_npre_drv_sel),
+	}, {
+	.propname = NULL
+	}
+};
+
+int fsp_s_update_config_from_dtb(ofnode node, struct fsp_s_config *cfg)
+{
+	return fsp_update_config_from_dtb(node, (u8 *)cfg, fsp_s_bindings);
+}
+#endif
diff --git a/arch/x86/cpu/apollolake/fsp_s.c b/arch/x86/cpu/apollolake/fsp_s.c
index 53ed5041c3..767ddfe680 100644
--- a/arch/x86/cpu/apollolake/fsp_s.c
+++ b/arch/x86/cpu/apollolake/fsp_s.c
@@ -24,313 +24,16 @@
 #include <asm/arch/fsp/fsp_configs.h>
 #include <asm/arch/fsp/fsp_s_upd.h>
 #include <linux/bitops.h>
+#include <asm/arch/fsp_bindings.h>
 
 #define PCH_P2SB_E0		0xe0
 #define HIDE_BIT		BIT(0)
 
-#define INTEL_GSPI_MAX		3
-#define MAX_USB2_PORTS		8
-
-enum {
-	CHIPSET_LOCKDOWN_FSP = 0, /* FSP handles locking per UPDs */
-	CHIPSET_LOCKDOWN_COREBOOT, /* coreboot handles locking */
-};
-
-/* Serial IRQ control. SERIRQ_QUIET is the default (0) */
-enum serirq_mode {
-	SERIRQ_QUIET,
-	SERIRQ_CONTINUOUS,
-	SERIRQ_OFF,
-};
-
-struct gspi_cfg {
-	/* Bus speed in MHz */
-	u32 speed_mhz;
-	/* Bus should be enabled prior to ramstage with temporary base */
-	u8 early_init;
-};
-
-/*
- * This structure will hold data required by common blocks.
- * These are soc specific configurations which will be filled by soc.
- * We'll fill this structure once during init and use the data in common block.
- */
-struct soc_intel_common_config {
-	int chipset_lockdown;
-	struct gspi_cfg gspi[INTEL_GSPI_MAX];
-};
-
-enum pnp_settings {
-	PNP_PERF,
-	PNP_POWER,
-	PNP_PERF_POWER,
-};
-
-struct usb2_eye_per_port {
-	u8 per_port_tx_pe_half;
-	u8 per_port_pe_txi_set;
-	u8 per_port_txi_set;
-	u8 hs_skew_sel;
-	u8 usb_tx_emphasis_en;
-	u8 per_port_rxi_set;
-	u8 hs_npre_drv_sel;
-	u8 override_en;
-};
-
-struct apl_config {
-	/* Common structure containing soc config data required by common code*/
-	struct soc_intel_common_config common_soc_config;
-
-	/*
-	 * Mapping from PCIe root port to CLKREQ input on the SOC. The SOC has
-	 * four CLKREQ inputs, but six root ports. Root ports without an
-	 * associated CLKREQ signal must be marked with "CLKREQ_DISABLED"
-	 */
-	u8 pcie_rp_clkreq_pin[MAX_PCIE_PORTS];
-
-	/* Enable/disable hot-plug for root ports (0 = disable, 1 = enable) */
-	u8 pcie_rp_hotplug_enable[MAX_PCIE_PORTS];
-
-	/* De-emphasis enable configuration for each PCIe root port */
-	u8 pcie_rp_deemphasis_enable[MAX_PCIE_PORTS];
-
-	/*
-	 * [14:8] DDR mode Number of dealy elements.Each = 125pSec.
-	 * [6:0] SDR mode Number of dealy elements.Each = 125pSec.
-	 */
-	u32 emmc_tx_cmd_cntl;
-
-	/*
-	 * [14:8] HS400 mode Number of dealy elements.Each = 125pSec.
-	 * [6:0] SDR104/HS200 mode Number of dealy elements.Each = 125pSec.
-	 */
-	u32 emmc_tx_data_cntl1;
-
-	/*
-	 * [30:24] SDR50 mode Number of dealy elements.Each = 125pSec.
-	 * [22:16] DDR50 mode Number of dealy elements.Each = 125pSec.
-	 * [14:8] SDR25/HS50 mode Number of dealy elements.Each = 125pSec.
-	 * [6:0] SDR12/Compatibility mode Number of dealy elements.
-	 *       Each = 125pSec.
-	 */
-	u32 emmc_tx_data_cntl2;
-
-	/*
-	 * [30:24] SDR50 mode Number of dealy elements.Each = 125pSec.
-	 * [22:16] DDR50 mode Number of dealy elements.Each = 125pSec.
-	 * [14:8] SDR25/HS50 mode Number of dealy elements.Each = 125pSec.
-	 * [6:0] SDR12/Compatibility mode Number of dealy elements.
-	 *       Each = 125pSec.
-	 */
-	u32 emmc_rx_cmd_data_cntl1;
-
-	/*
-	 * [14:8] HS400 mode 1 Number of dealy elements.Each = 125pSec.
-	 * [6:0] HS400 mode 2 Number of dealy elements.Each = 125pSec.
-	 */
-	u32 emmc_rx_strobe_cntl;
-
-	/*
-	 * [13:8] Auto Tuning mode Number of dealy elements.Each = 125pSec.
-	 * [6:0] SDR104/HS200 Number of dealy elements.Each = 125pSec.
-	 */
-	u32 emmc_rx_cmd_data_cntl2;
-
-	/* Select the eMMC max speed allowed */
-	u32 emmc_host_max_speed;
-
-	/* Specifies on which IRQ the SCI will internally appear */
-	u32 sci_irq;
-
-	/* Configure serial IRQ (SERIRQ) line */
-	enum serirq_mode serirq_mode;
-
-	/* Configure LPSS S0ix Enable */
-	bool lpss_s0ix_enable;
-
-	/* Enable DPTF support */
-	bool dptf_enable;
-
-	/* TCC activation offset value in degrees Celsius */
-	int tcc_offset;
-
-	/*
-	 * Configure Audio clk gate and power gate
-	 * IOSF-SB port ID 92 offset 0x530 [5] and [3]
-	 */
-	bool hdaudio_clk_gate_enable;
-	bool hdaudio_pwr_gate_enable;
-	bool hdaudio_bios_config_lockdown;
-
-	/* SLP S3 minimum assertion width */
-	int slp_s3_assertion_width_usecs;
-
-	/* GPIO pin for PERST_0 */
-	u32 prt0_gpio;
-
-	/* USB2 eye diagram settings per port */
-	struct usb2_eye_per_port usb2eye[MAX_USB2_PORTS];
-
-	/* GPIO SD card detect pin */
-	unsigned int sdcard_cd_gpio;
-
-	/*
-	 * PRMRR size setting with three options
-	 *  0x02000000 - 32MiB
-	 *  0x04000000 - 64MiB
-	 *  0x08000000 - 128MiB
-	 */
-	u32 PrmrrSize;
-
-	/*
-	 * Enable SGX feature.
-	 * Enabling SGX feature is 2 step process,
-	 * (1) set sgx_enable = 1
-	 * (2) set PrmrrSize to supported size
-	 */
-	bool sgx_enable;
-
-	/*
-	 * Select PNP Settings.
-	 * (0) Performance,
-	 * (1) Power
-	 * (2) Power & Performance
-	 */
-	enum pnp_settings pnp_settings;
-
-	/*
-	 * PMIC PCH_PWROK delay configuration - IPC Configuration
-	 * Upd for changing PCH_PWROK delay configuration : I2C_Slave_Address
-	 * (31:24) + Register_Offset (23:16) + OR Value (15:8) + AND Value (7:0)
-	 */
-	u32 pmic_pmc_ipc_ctrl;
-
-	/*
-	 * Options to disable XHCI Link Compliance Mode. Default is FALSE to not
-	 * disable Compliance Mode. Set TRUE to disable Compliance Mode.
-	 * 0:FALSE(Default), 1:True.
-	 */
-	bool disable_compliance_mode;
-
-	/*
-	 * Options to change USB3 ModPhy setting for the Integrated Filter (IF)
-	 * value. Default is 0 to not changing default IF value (0x12). Set
-	 * value with the range from 0x01 to 0xff to change IF value.
-	 */
-	u32 mod_phy_if_value;
-
-	/*
-	 * Options to bump USB3 LDO voltage. Default is FALSE to not increasing
-	 * LDO voltage. Set TRUE to increase LDO voltage with 40mV.
-	 * 0:FALSE (default), 1:True.
-	 */
-	bool mod_phy_voltage_bump;
-
-	/*
-	 * Options to adjust PMIC Vdd2 voltage. Default is 0 to not adjusting
-	 * the PMIC Vdd2 default voltage 1.20v. Upd for changing Vdd2 Voltage
-	 * configuration: I2C_Slave_Address (31:23) + Register_Offset (23:16)
-	 * + OR Value (15:8) + AND Value (7:0) through BUCK5_VID[3:2]:
-	 * 00=1.10v, 01=1.15v, 10=1.24v, 11=1.20v (default).
-	 */
-	u32 pmic_vdd2_voltage;
-
-	/* Option to enable VTD feature */
-	bool enable_vtd;
-};
-
-static int get_config(struct udevice *dev, struct apl_config *apl)
-{
-	const u8 *ptr;
-	ofnode node;
-	u32 emmc[4];
-	int ret;
-
-	memset(apl, '\0', sizeof(*apl));
-
-	node = dev_read_subnode(dev, "fsp-s");
-	if (!ofnode_valid(node))
-		return log_msg_ret("fsp-s settings", -ENOENT);
-
-	ptr = ofnode_read_u8_array_ptr(node, "pcie-rp-clkreq-pin",
-				       MAX_PCIE_PORTS);
-	if (!ptr)
-		return log_msg_ret("pcie-rp-clkreq-pin", -EINVAL);
-	memcpy(apl->pcie_rp_clkreq_pin, ptr, MAX_PCIE_PORTS);
-
-	ret = ofnode_read_u32(node, "prt0-gpio", &apl->prt0_gpio);
-	if (ret)
-		return log_msg_ret("prt0-gpio", ret);
-	ret = ofnode_read_u32(node, "sdcard-cd-gpio", &apl->sdcard_cd_gpio);
-	if (ret)
-		return log_msg_ret("sdcard-cd-gpio", ret);
-
-	ret = ofnode_read_u32_array(node, "emmc", emmc, ARRAY_SIZE(emmc));
-	if (ret)
-		return log_msg_ret("emmc", ret);
-	apl->emmc_tx_data_cntl1 = emmc[0];
-	apl->emmc_tx_data_cntl2 = emmc[1];
-	apl->emmc_rx_cmd_data_cntl1 = emmc[2];
-	apl->emmc_rx_cmd_data_cntl2 = emmc[3];
-
-	apl->dptf_enable = ofnode_read_bool(node, "dptf-enable");
-
-	apl->hdaudio_clk_gate_enable = ofnode_read_bool(node,
-						"hdaudio-clk-gate-enable");
-	apl->hdaudio_pwr_gate_enable = ofnode_read_bool(node,
-						"hdaudio-pwr-gate-enable");
-	apl->hdaudio_bios_config_lockdown = ofnode_read_bool(node,
-					     "hdaudio-bios-config-lockdown");
-	apl->lpss_s0ix_enable = ofnode_read_bool(node, "lpss-s0ix-enable");
-
-	/* Santa */
-	apl->usb2eye[1].per_port_pe_txi_set = 7;
-	apl->usb2eye[1].per_port_txi_set = 2;
-
-	return 0;
-}
-
-static void apl_fsp_silicon_init_params_cb(struct apl_config *apl,
-					   struct fsp_s_config *cfg)
-{
-	u8 port;
-
-	for (port = 0; port < MAX_USB2_PORTS; port++) {
-		if (apl->usb2eye[port].per_port_tx_pe_half)
-			cfg->port_usb20_per_port_tx_pe_half[port] =
-				apl->usb2eye[port].per_port_tx_pe_half;
-
-		if (apl->usb2eye[port].per_port_pe_txi_set)
-			cfg->port_usb20_per_port_pe_txi_set[port] =
-				apl->usb2eye[port].per_port_pe_txi_set;
-
-		if (apl->usb2eye[port].per_port_txi_set)
-			cfg->port_usb20_per_port_txi_set[port] =
-				apl->usb2eye[port].per_port_txi_set;
-
-		if (apl->usb2eye[port].hs_skew_sel)
-			cfg->port_usb20_hs_skew_sel[port] =
-				apl->usb2eye[port].hs_skew_sel;
-
-		if (apl->usb2eye[port].usb_tx_emphasis_en)
-			cfg->port_usb20_i_usb_tx_emphasis_en[port] =
-				apl->usb2eye[port].usb_tx_emphasis_en;
-
-		if (apl->usb2eye[port].per_port_rxi_set)
-			cfg->port_usb20_per_port_rxi_set[port] =
-				apl->usb2eye[port].per_port_rxi_set;
-
-		if (apl->usb2eye[port].hs_npre_drv_sel)
-			cfg->port_usb20_hs_npre_drv_sel[port] =
-				apl->usb2eye[port].hs_npre_drv_sel;
-	}
-}
-
 int fsps_update_config(struct udevice *dev, ulong rom_offset,
 		       struct fsps_upd *upd)
 {
 	struct fsp_s_config *cfg = &upd->config;
-	struct apl_config *apl;
+	ofnode node;
 
 	if (IS_ENABLED(CONFIG_HAVE_VBT)) {
 		struct binman_entry vbt;
@@ -358,88 +61,11 @@ int fsps_update_config(struct udevice *dev, ulong rom_offset,
 		cfg->graphics_config_ptr = (ulong)vbt_buf;
 	}
 
-	apl = malloc(sizeof(*apl));
-	if (!apl)
-		return log_msg_ret("config", -ENOMEM);
-	get_config(dev, apl);
-
-	cfg->ish_enable = 0;
-	cfg->enable_sata = 0;
-	cfg->pcie_root_port_en[2] = 0;
-	cfg->pcie_rp_hot_plug[2] = 0;
-	cfg->pcie_root_port_en[3] = 0;
-	cfg->pcie_rp_hot_plug[3] = 0;
-	cfg->pcie_root_port_en[4] = 0;
-	cfg->pcie_rp_hot_plug[4] = 0;
-	cfg->pcie_root_port_en[5] = 0;
-	cfg->pcie_rp_hot_plug[5] = 0;
-	cfg->pcie_root_port_en[1] = 0;
-	cfg->pcie_rp_hot_plug[1] = 0;
-	cfg->usb_otg = 0;
-	cfg->i2c6_enable = 0;
-	cfg->i2c7_enable = 0;
-	cfg->hsuart3_enable = 0;
-	cfg->spi1_enable = 0;
-	cfg->spi2_enable = 0;
-	cfg->sdio_enabled = 0;
-
-	memcpy(cfg->pcie_rp_clk_req_number, apl->pcie_rp_clkreq_pin,
-	       sizeof(cfg->pcie_rp_clk_req_number));
-
-	memcpy(cfg->pcie_rp_hot_plug, apl->pcie_rp_hotplug_enable,
-	       sizeof(cfg->pcie_rp_hot_plug));
-
-	switch (apl->serirq_mode) {
-	case SERIRQ_QUIET:
-		cfg->sirq_enable = 1;
-		cfg->sirq_mode = 0;
-		break;
-	case SERIRQ_CONTINUOUS:
-		cfg->sirq_enable = 1;
-		cfg->sirq_mode = 1;
-		break;
-	case SERIRQ_OFF:
-	default:
-		cfg->sirq_enable = 0;
-		break;
-	}
-
-	if (apl->emmc_tx_cmd_cntl)
-		cfg->emmc_tx_cmd_cntl = apl->emmc_tx_cmd_cntl;
-	if (apl->emmc_tx_data_cntl1)
-		cfg->emmc_tx_data_cntl1 = apl->emmc_tx_data_cntl1;
-	if (apl->emmc_tx_data_cntl2)
-		cfg->emmc_tx_data_cntl2 = apl->emmc_tx_data_cntl2;
-	if (apl->emmc_rx_cmd_data_cntl1)
-		cfg->emmc_rx_cmd_data_cntl1 = apl->emmc_rx_cmd_data_cntl1;
-	if (apl->emmc_rx_strobe_cntl)
-		cfg->emmc_rx_strobe_cntl = apl->emmc_rx_strobe_cntl;
-	if (apl->emmc_rx_cmd_data_cntl2)
-		cfg->emmc_rx_cmd_data_cntl2 = apl->emmc_rx_cmd_data_cntl2;
-	if (apl->emmc_host_max_speed)
-		cfg->e_mmc_host_max_speed = apl->emmc_host_max_speed;
-
-	cfg->lpss_s0ix_enable = apl->lpss_s0ix_enable;
-
-	cfg->skip_mp_init = true;
-
-	/* Disable setting of EISS bit in FSP */
-	cfg->spi_eiss = 0;
-
-	/* Disable FSP from locking access to the RTC NVRAM */
-	cfg->rtc_lock = 0;
-
-	/* Enable Audio clk gate and power gate */
-	cfg->hd_audio_clk_gate = apl->hdaudio_clk_gate_enable;
-	cfg->hd_audio_pwr_gate = apl->hdaudio_pwr_gate_enable;
-	/* Bios config lockdown Audio clk and power gate */
-	cfg->bios_cfg_lock_down = apl->hdaudio_bios_config_lockdown;
-	apl_fsp_silicon_init_params_cb(apl, cfg);
-
-	cfg->usb_otg = true;
-	cfg->vtd_enable = apl->enable_vtd;
+	node = dev_read_subnode(dev, "fsp-s");
+	if (!ofnode_valid(node))
+		return log_msg_ret("fsp-s settings", -ENOENT);
 
-	return 0;
+	return fsp_s_update_config_from_dtb(node, cfg);
 }
 
 static void p2sb_set_hide_bit(pci_dev_t dev, int hide)