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| author | Bernhard Messerklinger <bernhard.messerklinger@br-automation.com> | 2020-05-18 13:33:34 +0300 |
|---|---|---|
| committer | Bin Meng <bmeng.cn@gmail.com> | 2020-05-27 09:40:09 +0300 |
| commit | 1fa6305fd605635781b66abd5c6170ee29624743 (patch) | |
| tree | 459d3127bd0c418947b323152909c06314d74367 /arch/x86/dts | |
| parent | 832fee864c6417efa9f39c41d23eb6c73da9e7b2 (diff) | |
| download | u-boot-1fa6305fd605635781b66abd5c6170ee29624743.tar.xz | |
x86: apl: Use devicetree for FSP-M configuration
A the moment the FSP-M configuration is a mix of hard coded values and
devicetree properties.
This patch makes FSP-M full configurable from devicetree by adding
binding properties for all FSP-M parameters.
Co-developed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Signed-off-by: Bernhard Messerklinger <bernhard.messerklinger@br-automation.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org> (Tested on coral)
[sjg: Fix a build error for coral]
Signed-off-by: Simon Glass <sjg@chromium.org>
[bmeng: Add __maybe_unused to fsp_update_config_from_dtb()]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Diffstat (limited to 'arch/x86/dts')
| -rw-r--r-- | arch/x86/dts/chromebook_coral.dts | 38 |
1 files changed, 37 insertions, 1 deletions
diff --git a/arch/x86/dts/chromebook_coral.dts b/arch/x86/dts/chromebook_coral.dts index d48ef3573e..a34e2d78cd 100644 --- a/arch/x86/dts/chromebook_coral.dts +++ b/arch/x86/dts/chromebook_coral.dts @@ -21,6 +21,7 @@ #include <asm/arch-apollolake/iomap.h> #include <asm/arch-apollolake/pm.h> #include <dt-bindings/clock/intel-clock.h> +#include <asm/arch-apollolake/fsp/fsp_m_upd.h> / { model = "Google Coral"; @@ -436,7 +437,42 @@ PAD_CFG_NF(LPC_FRAMEB, NATIVE, DEEP, NF1) /* LPC_FRAME_N */ >; - lpddr4-swizzle = /bits/ 8 < + fspm,package = <PACKAGE_BGA>; + fspm,profile = <PROFILE_LPDDR4_2400_24_22_22>; + fspm,memory-down = <MEMORY_DOWN_YES>; + fspm,scrambler-support = <1>; + fspm,interleaved-mode = <INTERLEAVED_MODE_ENABLE>; + fspm,channel-hash-mask = <0x36>; + fspm,slice-hash-mask = <0x9>; + fspm,dual-rank-support-enable = <1>; + fspm,low-memory-max-value = <2048>; + fspm,ch0-rank-enable = <1>; + fspm,ch0-device-width = <CHX_DEVICE_WIDTH_X16>; + fspm,ch0-dram-density = <CHX_DEVICE_DENSITY_8GB>; + fspm,ch0-option = <(CHX_OPTION_RANK_INTERLEAVING | + CHX_OPTION_BANK_ADDRESS_HASHING_ENABLE)>; + fspm,ch0-odt-config = <CHX_ODT_CONFIG_DDR4_CA_ODT>; + fspm,ch1-rank-enable = <1>; + fspm,ch1-device-width = <CHX_DEVICE_WIDTH_X16>; + fspm,ch1-dram-density = <CHX_DEVICE_DENSITY_8GB>; + fspm,ch1-option = <(CHX_OPTION_RANK_INTERLEAVING | + CHX_OPTION_BANK_ADDRESS_HASHING_ENABLE)>; + fspm,ch1-odt-config = <CHX_ODT_CONFIG_DDR4_CA_ODT>; + fspm,ch2-rank-enable = <1>; + fspm,ch2-device-width = <CHX_DEVICE_WIDTH_X16>; + fspm,ch2-dram-density = <CHX_DEVICE_DENSITY_8GB>; + fspm,ch2-option = <(CHX_OPTION_RANK_INTERLEAVING | + CHX_OPTION_BANK_ADDRESS_HASHING_ENABLE)>; + fspm,ch2-odt-config = <CHX_ODT_CONFIG_DDR4_CA_ODT>; + fspm,ch3-rank-enable = <1>; + fspm,ch3-device-width = <CHX_DEVICE_WIDTH_X16>; + fspm,ch3-dram-density = <CHX_DEVICE_DENSITY_8GB>; + fspm,ch3-option = <(CHX_OPTION_RANK_INTERLEAVING | + CHX_OPTION_BANK_ADDRESS_HASHING_ENABLE)>; + fspm,ch3-odt-config = <CHX_ODT_CONFIG_DDR4_CA_ODT>; + fspm,fspm,skip-cse-rbp = <1>; + + fspm,ch-bit-swizzling = /bits/ 8 < /* LP4_PHYS_CH0A */ /* DQA[0:7] pins of LPDDR4 module */ |