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| author | Wolfgang Wallner <wolfgang.wallner@br-automation.com> | 2020-07-21 14:01:45 +0300 |
|---|---|---|
| committer | Bin Meng <bmeng.cn@gmail.com> | 2020-08-03 05:46:56 +0300 |
| commit | 491135805e087d4aa05aed1c53722154d8ec5ad2 (patch) | |
| tree | 19062b19756f42f81e85d2875aad9560ff0774b5 /arch/x86/include/asm | |
| parent | a2d051e7b6a8f87add1067d936bb0c805a47b0df (diff) | |
| download | u-boot-491135805e087d4aa05aed1c53722154d8ec5ad2.tar.xz | |
x86: irq: Fix some typos
Fix some typos in arch/x86/include/asm/irq.h.
Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Diffstat (limited to 'arch/x86/include/asm')
| -rw-r--r-- | arch/x86/include/asm/irq.h | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/arch/x86/include/asm/irq.h b/arch/x86/include/asm/irq.h index e5c916070c..bee0760c2d 100644 --- a/arch/x86/include/asm/irq.h +++ b/arch/x86/include/asm/irq.h @@ -12,8 +12,8 @@ * Intel interrupt router configuration mechanism * * There are two known ways of Intel interrupt router configuration mechanism - * so far. On most cases, the IRQ routing configuraiton is controlled by PCI - * configuraiton registers on the legacy bridge, normally PCI BDF(0, 31, 0). + * so far. On most cases, the IRQ routing configuration is controlled by PCI + * configuration registers on the legacy bridge, normally PCI BDF(0, 31, 0). * On some newer platforms like BayTrail and Braswell, the IRQ routing is now * in the IBASE register block where IBASE is memory-mapped. */ @@ -36,7 +36,7 @@ struct pirq_regmap { * @link_base: link value base number * @link_num: number of PIRQ links supported * @has_regmap: has mapping table between PIRQ link and routing register offset - * @irq_mask: IRQ mask reprenting the 16 IRQs in 8259, bit N is 1 means + * @irq_mask: IRQ mask representing the 16 IRQs in 8259, bit N is 1 means * IRQ N is available to be routed * @lb_bdf: irq router's PCI bus/device/function number encoding * @ibase: IBASE register block base address |