diff options
| author | Simon Glass <sjg@chromium.org> | 2021-01-21 23:57:07 +0300 |
|---|---|---|
| committer | Simon Glass <sjg@chromium.org> | 2021-01-31 00:25:41 +0300 |
| commit | 442e6305b5b02d689774a0bf73311643ffa0df6f (patch) | |
| tree | 9a02dc0eb54ecce032b4fa8cf9ce6b2c7a19f01f /arch/x86/include | |
| parent | 1426174f3fb0727321531504afbde110ef716573 (diff) | |
| download | u-boot-442e6305b5b02d689774a0bf73311643ffa0df6f.tar.xz | |
x86: coral: Support TPM and RTC in SPL
Update the devicetree so that the TPM and RTC can be used in SPL. Also
enable the pins used for getting the memory configuration settings while
we are here.
Signed-off-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'arch/x86/include')
| -rw-r--r-- | arch/x86/include/asm/arch-apollolake/iomap.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/arch/x86/include/asm/arch-apollolake/iomap.h b/arch/x86/include/asm/arch-apollolake/iomap.h index 21c5f33021..a4ea150707 100644 --- a/arch/x86/include/asm/arch-apollolake/iomap.h +++ b/arch/x86/include/asm/arch-apollolake/iomap.h @@ -33,6 +33,9 @@ #define SRAM_SIZE_2 (4 * KiB) #endif +/* Early address for I2C port 2 */ +#define IOMAP_I2C2_BASE (0xfe020000 + 2 * 0x1000) + /* * Use UART2. To use UART1 you need to set '2' to '1', change device tree serial * node name and 'reg' property, and update CONFIG_DEBUG_UART_BASE. |