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authorSimon Glass <sjg@chromium.org>2019-12-07 07:42:58 +0300
committerBin Meng <bmeng.cn@gmail.com>2019-12-15 06:44:26 +0300
commit7656582378a3ff166080713d44cfc6fdc8cec6b0 (patch)
treec807bfc08a7c545d67cf621c5a685d047277f7db /arch/x86/include
parent28eefefccfaa695fb44935ce8b04d50548d78b13 (diff)
downloadu-boot-7656582378a3ff166080713d44cfc6fdc8cec6b0.tar.xz
x86: apl: Add UART driver
Add a driver for the Apollo Lake UART. It uses the standard ns16550 device but also sets up the input clock with LPSS and supports configuration via of-platdata. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Diffstat (limited to 'arch/x86/include')
-rw-r--r--arch/x86/include/asm/arch-apollolake/uart.h20
1 files changed, 20 insertions, 0 deletions
diff --git a/arch/x86/include/asm/arch-apollolake/uart.h b/arch/x86/include/asm/arch-apollolake/uart.h
new file mode 100644
index 0000000000..d4fffe6525
--- /dev/null
+++ b/arch/x86/include/asm/arch-apollolake/uart.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright 2019 Google LLC
+ */
+
+#ifndef _ASM_ARCH_UART_H
+#define _ASM_ARCH_UART_H
+
+/**
+ * apl_uart_init() - Set up the APL UART device and clock
+ *
+ * This enables the PCI device, sets up the MMIO region and turns on the clock
+ * using LPSS.
+ *
+ * The UART won't actually work unless the GPIO settings are correct and the
+ * signals actually exit the SoC. See board_debug_uart_init() for that.
+ */
+int apl_uart_init(pci_dev_t bdf, ulong base);
+
+#endif