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authorSimon Glass <sjg@chromium.org>2019-09-25 17:11:30 +0300
committerBin Meng <bmeng.cn@gmail.com>2019-10-08 08:54:01 +0300
commitb2d544a15d2edf8199e45e06c44b3e99ace906bc (patch)
treeace40793ea4223e4e00989a0afe0a9cd5e90e383 /arch/x86/lib/fsp1
parente9de4a7cd31a08d7bd2afa842db5aca57b3a37cb (diff)
downloadu-boot-b2d544a15d2edf8199e45e06c44b3e99ace906bc.tar.xz
x86: Move common fsp functions into a common file
Some of this file can be shared between FSP1 and FSP2. Move it into a shared file. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
Diffstat (limited to 'arch/x86/lib/fsp1')
-rw-r--r--arch/x86/lib/fsp1/fsp_common.c87
1 files changed, 0 insertions, 87 deletions
diff --git a/arch/x86/lib/fsp1/fsp_common.c b/arch/x86/lib/fsp1/fsp_common.c
index bfd76dccba..285ef72ebf 100644
--- a/arch/x86/lib/fsp1/fsp_common.c
+++ b/arch/x86/lib/fsp1/fsp_common.c
@@ -18,93 +18,6 @@
DECLARE_GLOBAL_DATA_PTR;
-int checkcpu(void)
-{
- return 0;
-}
-
-int print_cpuinfo(void)
-{
- post_code(POST_CPU_INFO);
- return default_print_cpuinfo();
-}
-
-int fsp_init_phase_pci(void)
-{
- u32 status;
-
- /* call into FspNotify */
- debug("Calling into FSP (notify phase INIT_PHASE_PCI): ");
- status = fsp_notify(NULL, INIT_PHASE_PCI);
- if (status)
- debug("fail, error code %x\n", status);
- else
- debug("OK\n");
-
- return status ? -EPERM : 0;
-}
-
-void board_final_cleanup(void)
-{
- u32 status;
-
- /* call into FspNotify */
- debug("Calling into FSP (notify phase INIT_PHASE_BOOT): ");
- status = fsp_notify(NULL, INIT_PHASE_BOOT);
- if (status)
- debug("fail, error code %x\n", status);
- else
- debug("OK\n");
-
- return;
-}
-
-static __maybe_unused void *fsp_prepare_mrc_cache(void)
-{
- struct mrc_data_container *cache;
- struct mrc_region entry;
- int ret;
-
- ret = mrccache_get_region(NULL, &entry);
- if (ret)
- return NULL;
-
- cache = mrccache_find_current(&entry);
- if (!cache)
- return NULL;
-
- debug("%s: mrc cache at %p, size %x checksum %04x\n", __func__,
- cache->data, cache->data_size, cache->checksum);
-
- return cache->data;
-}
-
-#ifdef CONFIG_HAVE_ACPI_RESUME
-int fsp_save_s3_stack(void)
-{
- struct udevice *dev;
- int ret;
-
- if (gd->arch.prev_sleep_state == ACPI_S3)
- return 0;
-
- ret = uclass_get_device(UCLASS_RTC, 0, &dev);
- if (ret) {
- debug("Cannot find RTC: err=%d\n", ret);
- return -ENODEV;
- }
-
- /* Save the stack address to CMOS */
- ret = rtc_write32(dev, CMOS_FSP_STACK_ADDR, gd->start_addr_sp);
- if (ret) {
- debug("Save stack address to CMOS: err=%d\n", ret);
- return -EIO;
- }
-
- return 0;
-}
-#endif
-
int arch_fsp_init(void)
{
void *nvs;