diff options
| author | Simon Glass <sjg@chromium.org> | 2023-07-16 06:39:13 +0300 |
|---|---|---|
| committer | Bin Meng <bmeng@tinylab.org> | 2023-07-17 12:23:15 +0300 |
| commit | dac1fa5c197ae30a60b2ce7489051359b9c8ebea (patch) | |
| tree | f7b265d83a64c1e39c9f9e9dffede6a5041fa378 /arch/x86/lib/spl.c | |
| parent | df1bb2cb0b57be734cfc70f5ab7e4712a32ee83f (diff) | |
| download | u-boot-dac1fa5c197ae30a60b2ce7489051359b9c8ebea.tar.xz | |
x86: Make sure that the LPC is active before SDRAM init
Some boards need to access GPIOs to determine which SDRAM is fitted to the
board, for example chromebook_link. Probe this device (if it exists) to
make sure that this works as expected.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Diffstat (limited to 'arch/x86/lib/spl.c')
| -rw-r--r-- | arch/x86/lib/spl.c | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/arch/x86/lib/spl.c b/arch/x86/lib/spl.c index ba3434b055..b6812bb8ca 100644 --- a/arch/x86/lib/spl.c +++ b/arch/x86/lib/spl.c @@ -65,6 +65,8 @@ static int set_max_freq(void) static int x86_spl_init(void) { + struct udevice *dev; + #ifndef CONFIG_TPL /* * TODO(sjg@chromium.org): We use this area of RAM for the stack @@ -114,6 +116,13 @@ static int x86_spl_init(void) return ret; } #endif + /* probe the LPC so we get the GPIO_BASE set up correctly */ + ret = uclass_first_device_err(UCLASS_LPC, &dev); + if (ret && ret != -ENODEV) { + log_debug("lpc probe failed\n"); + return ret; + } + ret = dram_init(); if (ret) { log_debug("dram_init() failed (err=%d)\n", ret); |