diff options
| author | Simon Glass <sjg@chromium.org> | 2020-07-10 03:43:17 +0300 |
|---|---|---|
| committer | Bin Meng <bmeng.cn@gmail.com> | 2020-07-17 09:32:24 +0300 |
| commit | 0990c894cc2e8e94a2b049e4c83d484d0b3afd9c (patch) | |
| tree | e797cbeef5ba4fb68a87501773d48a8fba228351 /arch/x86/lib | |
| parent | ef5f5f6ca691ac0b08dfae45f8723668a9fc46b6 (diff) | |
| download | u-boot-0990c894cc2e8e94a2b049e4c83d484d0b3afd9c.tar.xz | |
x86: fsp: Support a warning message when DRAM init is slow
With DDR4, Intel SOCs take quite a long time to init their memory. During
this time, if the user is watching, it looks like SPL has hung. Add a
message in this case.
This works by adding a return code to fspm_update_config() that indicates
whether MRC data was found and a new property to the device tree.
Also add one more debug message while starting.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Diffstat (limited to 'arch/x86/lib')
| -rw-r--r-- | arch/x86/lib/fsp2/fsp_meminit.c | 24 |
1 files changed, 19 insertions, 5 deletions
diff --git a/arch/x86/lib/fsp2/fsp_meminit.c b/arch/x86/lib/fsp2/fsp_meminit.c index faf9c29aef..ce0b0aff76 100644 --- a/arch/x86/lib/fsp2/fsp_meminit.c +++ b/arch/x86/lib/fsp2/fsp_meminit.c @@ -9,6 +9,7 @@ #include <common.h> #include <binman.h> #include <bootstage.h> +#include <dm.h> #include <log.h> #include <asm/mrccache.h> #include <asm/fsp/fsp_infoheader.h> @@ -63,8 +64,10 @@ int fsp_memory_init(bool s3wake, bool use_spi_flash) struct fsp_header *hdr; struct hob_header *hob; struct udevice *dev; + int delay; int ret; + log_debug("Locating FSP\n"); ret = fsp_locate_fsp(FSP_M, &entry, use_spi_flash, &dev, &hdr, NULL); if (ret) return log_msg_ret("locate FSP", ret); @@ -76,21 +79,32 @@ int fsp_memory_init(bool s3wake, bool use_spi_flash) return log_msg_ret("Bad UPD signature", -EPERM); memcpy(&upd, fsp_upd, sizeof(upd)); + delay = dev_read_u32_default(dev, "fspm,training-delay", 0); ret = fspm_update_config(dev, &upd); - if (ret) - return log_msg_ret("Could not setup config", ret); - - debug("SDRAM init..."); + if (ret) { + if (ret != -ENOENT) + return log_msg_ret("Could not setup config", ret); + } else { + delay = 0; + } + + if (delay) + printf("SDRAM training (%d seconds)...", delay); + else + log_debug("SDRAM init..."); bootstage_start(BOOTSTAGE_ID_ACCUM_FSP_M, "fsp-m"); func = (fsp_memory_init_func)(hdr->img_base + hdr->fsp_mem_init); ret = func(&upd, &hob); bootstage_accum(BOOTSTAGE_ID_ACCUM_FSP_M); cpu_reinit_fpu(); + if (delay) + printf("done\n"); + else + log_debug("done\n"); if (ret) return log_msg_ret("SDRAM init fail\n", ret); gd->arch.hob_list = hob; - debug("done\n"); ret = fspm_done(dev); if (ret) |