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author | Tom Rini <trini@konsulko.com> | 2021-08-03 04:35:50 +0300 |
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committer | Tom Rini <trini@konsulko.com> | 2021-08-03 04:35:50 +0300 |
commit | 3b64774323298362f9833aac75bb4639b4f98999 (patch) | |
tree | 34a6428754d442d5559a7131ff27225ec7c0663a /arch/x86/lib | |
parent | 51aef405550e603ff702c034f0e2cd0f15bdf2bb (diff) | |
parent | 9feb5bdcc07b27806df07fd6b9260bb5cdef072d (diff) | |
download | u-boot-3b64774323298362f9833aac75bb4639b4f98999.tar.xz |
Merge https://source.denx.de/u-boot/custodians/u-boot-x86
- Fixed broken ICH SPI driver in software sequencer mode
- Added "m25p,fast-read" to SPI flash node for x86 boards
- Drop ROM_NEEDS_BLOBS and BUILD_ROM for x86 ROM builds
- Define a default TSC timer frequency for all x86 boards
- x86 MTRR MSR programming codes bug fixes
- x86 "hob" command bug fixes
- Don't program MTRR for DRAM for FSP1
- Move INIT_PHASE_END_FIRMWARE to FSP2
- Use external graphics card by default on Intel Crown Bay
- tangier: Fix DMA controller IRQ polarity in CSRT
Diffstat (limited to 'arch/x86/lib')
-rw-r--r-- | arch/x86/lib/fsp/fsp_common.c | 16 | ||||
-rw-r--r-- | arch/x86/lib/fsp/fsp_dram.c | 27 | ||||
-rw-r--r-- | arch/x86/lib/fsp2/fsp_common.c | 17 |
3 files changed, 40 insertions, 20 deletions
diff --git a/arch/x86/lib/fsp/fsp_common.c b/arch/x86/lib/fsp/fsp_common.c index 6365b0a50a..82f7d3ab5f 100644 --- a/arch/x86/lib/fsp/fsp_common.c +++ b/arch/x86/lib/fsp/fsp_common.c @@ -61,22 +61,6 @@ void board_final_init(void) debug("OK\n"); } -void board_final_cleanup(void) -{ - u32 status; - - /* TODO(sjg@chromium.org): This causes Linux to crash */ - return; - - /* call into FspNotify */ - debug("Calling into FSP (notify phase INIT_PHASE_END_FIRMWARE): "); - status = fsp_notify(NULL, INIT_PHASE_END_FIRMWARE); - if (status) - debug("fail, error code %x\n", status); - else - debug("OK\n"); -} - int fsp_save_s3_stack(void) { struct udevice *dev; diff --git a/arch/x86/lib/fsp/fsp_dram.c b/arch/x86/lib/fsp/fsp_dram.c index 8ad9aeedac..2bd408d0c5 100644 --- a/arch/x86/lib/fsp/fsp_dram.c +++ b/arch/x86/lib/fsp/fsp_dram.c @@ -48,12 +48,28 @@ int dram_init_banksize(void) phys_addr_t mtrr_top; phys_addr_t low_end; uint bank; + bool update_mtrr; + + /* + * For FSP1, the system memory and reserved memory used by FSP are + * already programmed in the MTRR by FSP. Also it is observed that + * FSP on Intel Queensbay platform reports the TSEG memory range + * that has the same RES_MEM_RESERVED resource type whose address + * is programmed by FSP to be near the top of 4 GiB space, which is + * not what we want for DRAM. + * + * However it seems FSP2's behavior is different. We need to add the + * DRAM range in MTRR otherwise the boot process goes very slowly, + * which was observed on Chrromebook Coral with FSP2. + */ + update_mtrr = CONFIG_IS_ENABLED(FSP_VERSION2); if (!ll_boot_init()) { gd->bd->bi_dram[0].start = 0; gd->bd->bi_dram[0].size = gd->ram_size; - mtrr_add_request(MTRR_TYPE_WRBACK, 0, gd->ram_size); + if (update_mtrr) + mtrr_add_request(MTRR_TYPE_WRBACK, 0, gd->ram_size); return 0; } @@ -76,8 +92,10 @@ int dram_init_banksize(void) } else { gd->bd->bi_dram[bank].start = res_desc->phys_start; gd->bd->bi_dram[bank].size = res_desc->len; - mtrr_add_request(MTRR_TYPE_WRBACK, res_desc->phys_start, - res_desc->len); + if (update_mtrr) + mtrr_add_request(MTRR_TYPE_WRBACK, + res_desc->phys_start, + res_desc->len); log_debug("ram %llx %llx\n", gd->bd->bi_dram[bank].start, gd->bd->bi_dram[bank].size); @@ -92,7 +110,8 @@ int dram_init_banksize(void) * Set up an MTRR to the top of low, reserved memory. This is necessary * for graphics to run at full speed in U-Boot. */ - mtrr_add_request(MTRR_TYPE_WRBACK, 0, mtrr_top); + if (update_mtrr) + mtrr_add_request(MTRR_TYPE_WRBACK, 0, mtrr_top); return 0; } diff --git a/arch/x86/lib/fsp2/fsp_common.c b/arch/x86/lib/fsp2/fsp_common.c index f69456e43a..20c3f6406a 100644 --- a/arch/x86/lib/fsp2/fsp_common.c +++ b/arch/x86/lib/fsp2/fsp_common.c @@ -6,8 +6,25 @@ #include <common.h> #include <init.h> +#include <asm/fsp/fsp_support.h> int arch_fsp_init(void) { return 0; } + +void board_final_cleanup(void) +{ + u32 status; + + /* TODO(sjg@chromium.org): This causes Linux to crash */ + return; + + /* call into FspNotify */ + debug("Calling into FSP (notify phase INIT_PHASE_END_FIRMWARE): "); + status = fsp_notify(NULL, INIT_PHASE_END_FIRMWARE); + if (status) + debug("fail, error code %x\n", status); + else + debug("OK\n"); +} |