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| author | Bin Meng <bmeng.cn@gmail.com> | 2017-07-19 16:50:10 +0300 |
|---|---|---|
| committer | Marek Vasut <marex@denx.de> | 2017-07-29 00:34:27 +0300 |
| commit | c9621012a6f86500d60648a5e714b1c36e9111b9 (patch) | |
| tree | 2f5c5e854b6c777ba09a7a9de5e42cb2fb7f0c41 /arch/x86 | |
| parent | 6e4d039aaaf87dcc83c743948c6bbcb49739e6a2 (diff) | |
| download | u-boot-c9621012a6f86500d60648a5e714b1c36e9111b9.tar.xz | |
x86: minnowmax: Enable USB xHCI support
BayTrail SoC supports both EHCI and xHCI controllers. However only
one host controller (either EHCI or xHCI) can be used. To enable
HSIC and SS ports, xHCI must be used. This turns on xHCI support on
Intel MinnowMax board.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'arch/x86')
| -rw-r--r-- | arch/x86/dts/minnowmax.dts | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/arch/x86/dts/minnowmax.dts b/arch/x86/dts/minnowmax.dts index 4c0a8fe26f..a0ad03ce23 100644 --- a/arch/x86/dts/minnowmax.dts +++ b/arch/x86/dts/minnowmax.dts @@ -272,6 +272,9 @@ fsp,enable-spi; fsp,enable-sata; fsp,sata-mode = <SATA_MODE_AHCI>; +#ifdef CONFIG_USB_XHCI_HCD + fsp,enable-xhci; +#endif fsp,lpe-mode = <LPE_MODE_PCI>; fsp,lpss-sio-mode = <LPSS_SIO_MODE_PCI>; fsp,enable-dma0; |