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author | Chris Zankel <chris@zankel.net> | 2016-08-10 18:36:44 +0300 |
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committer | Tom Rini <trini@konsulko.com> | 2016-08-16 01:46:38 +0300 |
commit | c978b52410016b0ab5a213f235596340af8d45f7 (patch) | |
tree | b01e9a8ea9a92fe962a545974339677b87dcc1ba /arch/xtensa/include/asm/cache.h | |
parent | de5e5cea022ab44006ff1edf45a39f0943fb9dff (diff) | |
download | u-boot-c978b52410016b0ab5a213f235596340af8d45f7.tar.xz |
xtensa: add support for the xtensa processor architecture [2/2]
The Xtensa processor architecture is a configurable, extensible,
and synthesizable 32-bit RISC processor core provided by Tensilica, inc.
This is the second part of the basic architecture port, adding the
'arch/xtensa' directory and a readme file.
Signed-off-by: Chris Zankel <chris@zankel.net>
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
Diffstat (limited to 'arch/xtensa/include/asm/cache.h')
-rw-r--r-- | arch/xtensa/include/asm/cache.h | 25 |
1 files changed, 25 insertions, 0 deletions
diff --git a/arch/xtensa/include/asm/cache.h b/arch/xtensa/include/asm/cache.h new file mode 100644 index 0000000000..08c534ca01 --- /dev/null +++ b/arch/xtensa/include/asm/cache.h @@ -0,0 +1,25 @@ +/* + * Copyright (C) 2009 Tensilica Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef _XTENSA_CACHE_H +#define _XTENSA_CACHE_H + +#include <asm/arch/core.h> + +#define ARCH_DMA_MINALIGN XCHAL_DCACHE_LINESIZE + +#ifndef __ASSEMBLY__ + +void __flush_dcache_all(void); +void __flush_invalidate_dcache_range(unsigned long addr, unsigned long size); +void __invalidate_dcache_all(void); +void __invalidate_dcache_range(unsigned long addr, unsigned long size); + +void __invalidate_icache_all(void); +void __invalidate_icache_range(unsigned long addr, unsigned long size); + +#endif + +#endif /* _XTENSA_CACHE_H */ |