Merge tag 'uniphier-v2020.04-3' of https://gitlab.denx.de/u-boot/custodians/u-boot-uniphier

UniPhier SoC updates for v2020.04 (3rd)

 - Enable ADMA and HS400 for the eMMC driver on 64-bit SoCs

 - Add some convenient environment variables to handle SD card

 - Sanitize the NAND controller reset sequence and its WP handling

 - Sync DT with Linux

21 files changed, 169 insertions, 95 deletions

diff --git a/arch/arm/dts/uniphier-ld11-global.dts b/arch/arm/dts/uniphier-ld11-global.dts
index 744b36e28a..7968d52435 100644
--- a/arch/arm/dts/uniphier-ld11-global.dts
+++ b/arch/arm/dts/uniphier-ld11-global.dts
@@ -132,7 +132,7 @@
 	};
 
 	eeprom@50 {
-		compatible = "st,24c64", "atmel,24c64", "i2c-eeprom";
+		compatible = "st,24c64", "atmel,24c64";
 		reg = <0x50>;
 		pagesize = <32>;
 	};
diff --git a/arch/arm/dts/uniphier-ld11.dtsi b/arch/arm/dts/uniphier-ld11.dtsi
index 337a3537ed..e0737ac7f0 100644
--- a/arch/arm/dts/uniphier-ld11.dtsi
+++ b/arch/arm/dts/uniphier-ld11.dtsi
@@ -433,7 +433,7 @@
 			};
 		};
 
-		emmc: sdhc@5a000000 {
+		emmc: mmc@5a000000 {
 			compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc";
 			reg = <0x5a000000 0x400>;
 			interrupts = <0 78 4>;
@@ -566,7 +566,7 @@
 			};
 		};
 
-		aidet: aidet@5fc20000 {
+		aidet: interrupt-controller@5fc20000 {
 			compatible = "socionext,uniphier-ld11-aidet";
 			reg = <0x5fc20000 0x200>;
 			interrupt-controller;
@@ -621,7 +621,7 @@
 			};
 		};
 
-		nand: nand@68000000 {
+		nand: nand-controller@68000000 {
 			compatible = "socionext,uniphier-denali-nand-v5b";
 			status = "disabled";
 			reg-names = "nand_data", "denali_reg";
@@ -631,7 +631,8 @@
 			pinctrl-0 = <&pinctrl_nand>;
 			clock-names = "nand", "nand_x", "ecc";
 			clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
-			resets = <&sys_rst 2>;
+			reset-names = "nand", "reg";
+			resets = <&sys_rst 2>, <&sys_rst 2>;
 		};
 	};
 };
diff --git a/arch/arm/dts/uniphier-ld20.dtsi b/arch/arm/dts/uniphier-ld20.dtsi
index 3721110b17..59e4191dfc 100644
--- a/arch/arm/dts/uniphier-ld20.dtsi
+++ b/arch/arm/dts/uniphier-ld20.dtsi
@@ -559,7 +559,7 @@
 			};
 		};
 
-		emmc: sdhc@5a000000 {
+		emmc: mmc@5a000000 {
 			compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc";
 			reg = <0x5a000000 0x400>;
 			interrupts = <0 78 4>;
@@ -578,7 +578,7 @@
 			cdns,phy-dll-delay-sdclk-hsmmc = <21>;
 		};
 
-		sd: sdhc@5a400000 {
+		sd: mmc@5a400000 {
 			compatible = "socionext,uniphier-sd-v3.1.1";
 			status = "disabled";
 			reg = <0x5a400000 0x800>;
@@ -664,7 +664,7 @@
 			};
 		};
 
-		aidet: aidet@5fc20000 {
+		aidet: interrupt-controller@5fc20000 {
 			compatible = "socionext,uniphier-ld20-aidet";
 			reg = <0x5fc20000 0x200>;
 			interrupt-controller;
@@ -944,7 +944,7 @@
 			socionext,syscon = <&soc_glue>;
 		};
 
-		nand: nand@68000000 {
+		nand: nand-controller@68000000 {
 			compatible = "socionext,uniphier-denali-nand-v5b";
 			status = "disabled";
 			reg-names = "nand_data", "denali_reg";
@@ -954,7 +954,8 @@
 			pinctrl-0 = <&pinctrl_nand>;
 			clock-names = "nand", "nand_x", "ecc";
 			clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
-			resets = <&sys_rst 2>;
+			reset-names = "nand", "reg";
+			resets = <&sys_rst 2>, <&sys_rst 2>;
 		};
 	};
 };
diff --git a/arch/arm/dts/uniphier-ld4.dtsi b/arch/arm/dts/uniphier-ld4.dtsi
index c2706cef0b..1eebc7fa3b 100644
--- a/arch/arm/dts/uniphier-ld4.dtsi
+++ b/arch/arm/dts/uniphier-ld4.dtsi
@@ -51,7 +51,7 @@
 		ranges;
 		interrupt-parent = <&intc>;
 
-		l2: l2-cache@500c0000 {
+		l2: cache-controller@500c0000 {
 			compatible = "socionext,uniphier-system-cache";
 			reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
 			      <0x506c0000 0x400>;
@@ -245,7 +245,7 @@
 			#dma-cells = <1>;
 		};
 
-		sd: sdhc@5a400000 {
+		sd: mmc@5a400000 {
 			compatible = "socionext,uniphier-sd-v2.91";
 			status = "disabled";
 			reg = <0x5a400000 0x200>;
@@ -265,7 +265,7 @@
 			sd-uhs-sdr50;
 		};
 
-		emmc: sdhc@5a500000 {
+		emmc: mmc@5a500000 {
 			compatible = "socionext,uniphier-sd-v2.91";
 			status = "disabled";
 			reg = <0x5a500000 0x200>;
@@ -375,7 +375,7 @@
 			interrupt-controller;
 		};
 
-		aidet: aidet@61830000 {
+		aidet: interrupt-controller@61830000 {
 			compatible = "socionext,uniphier-ld4-aidet";
 			reg = <0x61830000 0x200>;
 			interrupt-controller;
@@ -398,7 +398,7 @@
 			};
 		};
 
-		nand: nand@68000000 {
+		nand: nand-controller@68000000 {
 			compatible = "socionext,uniphier-denali-nand-v5a";
 			status = "disabled";
 			reg-names = "nand_data", "denali_reg";
@@ -408,7 +408,8 @@
 			pinctrl-0 = <&pinctrl_nand2cs>;
 			clock-names = "nand", "nand_x", "ecc";
 			clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
-			resets = <&sys_rst 2>;
+			reset-names = "nand", "reg";
+			resets = <&sys_rst 2>, <&sys_rst 2>;
 		};
 	};
 };
diff --git a/arch/arm/dts/uniphier-pro4-ace.dts b/arch/arm/dts/uniphier-pro4-ace.dts
index ce8ea7b79b..92cc48dd86 100644
--- a/arch/arm/dts/uniphier-pro4-ace.dts
+++ b/arch/arm/dts/uniphier-pro4-ace.dts
@@ -50,10 +50,9 @@
 	status = "okay";
 
 	eeprom@54 {
-		compatible = "st,24c64", "atmel,24c64", "i2c-eeprom";
+		compatible = "st,24c64", "atmel,24c64";
 		reg = <0x54>;
 		pagesize = <32>;
-		u-boot,i2c-offset-len = <2>;
 	};
 };
 
diff --git a/arch/arm/dts/uniphier-pro4-sanji.dts b/arch/arm/dts/uniphier-pro4-sanji.dts
index 686dd3af7e..3b68a7c605 100644
--- a/arch/arm/dts/uniphier-pro4-sanji.dts
+++ b/arch/arm/dts/uniphier-pro4-sanji.dts
@@ -45,10 +45,9 @@
 	status = "okay";
 
 	eeprom@54 {
-		compatible = "st,24c64", "atmel,24c64", "i2c-eeprom";
+		compatible = "st,24c64", "atmel,24c64";
 		reg = <0x54>;
 		pagesize = <32>;
-		u-boot,i2c-offset-len = <2>;
 	};
 };
 
diff --git a/arch/arm/dts/uniphier-pro4.dtsi b/arch/arm/dts/uniphier-pro4.dtsi
index d090fc7e2d..d006b45f7a 100644
--- a/arch/arm/dts/uniphier-pro4.dtsi
+++ b/arch/arm/dts/uniphier-pro4.dtsi
@@ -59,7 +59,7 @@
 		ranges;
 		interrupt-parent = <&intc>;
 
-		l2: l2-cache@500c0000 {
+		l2: cache-controller@500c0000 {
 			compatible = "socionext,uniphier-system-cache";
 			reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
 			      <0x506c0000 0x400>;
@@ -279,7 +279,7 @@
 			#dma-cells = <1>;
 		};
 
-		sd: sdhc@5a400000 {
+		sd: mmc@5a400000 {
 			compatible = "socionext,uniphier-sd-v2.91";
 			status = "disabled";
 			reg = <0x5a400000 0x200>;
@@ -299,7 +299,7 @@
 			sd-uhs-sdr50;
 		};
 
-		emmc: sdhc@5a500000 {
+		emmc: mmc@5a500000 {
 			compatible = "socionext,uniphier-sd-v2.91";
 			status = "disabled";
 			reg = <0x5a500000 0x200>;
@@ -317,7 +317,7 @@
 			non-removable;
 		};
 
-		sd1: sdhc@5a600000 {
+		sd1: mmc@5a600000 {
 			compatible = "socionext,uniphier-sd-v2.91";
 			status = "disabled";
 			reg = <0x5a600000 0x200>;
@@ -426,7 +426,7 @@
 			};
 		};
 
-		aidet: aidet@5fc20000 {
+		aidet: interrupt-controller@5fc20000 {
 			compatible = "socionext,uniphier-pro4-aidet";
 			reg = <0x5fc20000 0x200>;
 			interrupt-controller;
@@ -626,7 +626,7 @@
 			};
 		};
 
-		nand: nand@68000000 {
+		nand: nand-controller@68000000 {
 			compatible = "socionext,uniphier-denali-nand-v5a";
 			status = "disabled";
 			reg-names = "nand_data", "denali_reg";
@@ -636,7 +636,8 @@
 			pinctrl-0 = <&pinctrl_nand>;
 			clock-names = "nand", "nand_x", "ecc";
 			clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
-			resets = <&sys_rst 2>;
+			reset-names = "nand", "reg";
+			resets = <&sys_rst 2>, <&sys_rst 2>;
 		};
 	};
 };
diff --git a/arch/arm/dts/uniphier-pro5.dtsi b/arch/arm/dts/uniphier-pro5.dtsi
index 9cad79d086..ba7e224b38 100644
--- a/arch/arm/dts/uniphier-pro5.dtsi
+++ b/arch/arm/dts/uniphier-pro5.dtsi
@@ -131,7 +131,7 @@
 		ranges;
 		interrupt-parent = <&intc>;
 
-		l2: l2-cache@500c0000 {
+		l2: cache-controller@500c0000 {
 			compatible = "socionext,uniphier-system-cache";
 			reg = <0x500c0000 0x2000>, <0x503c0100 0x8>,
 			      <0x506c0000 0x400>;
@@ -144,7 +144,7 @@
 			next-level-cache = <&l3>;
 		};
 
-		l3: l3-cache@500c8000 {
+		l3: cache-controller@500c8000 {
 			compatible = "socionext,uniphier-system-cache";
 			reg = <0x500c8000 0x2000>, <0x503c8100 0x8>,
 			      <0x506c8000 0x400>;
@@ -408,7 +408,7 @@
 			};
 		};
 
-		aidet: aidet@5fc20000 {
+		aidet: interrupt-controller@5fc20000 {
 			compatible = "socionext,uniphier-pro5-aidet";
 			reg = <0x5fc20000 0x200>;
 			interrupt-controller;
@@ -489,7 +489,7 @@
 			};
 		};
 
-		nand: nand@68000000 {
+		nand: nand-controller@68000000 {
 			compatible = "socionext,uniphier-denali-nand-v5b";
 			status = "disabled";
 			reg-names = "nand_data", "denali_reg";
@@ -499,10 +499,11 @@
 			pinctrl-0 = <&pinctrl_nand2cs>;
 			clock-names = "nand", "nand_x", "ecc";
 			clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
-			resets = <&sys_rst 2>;
+			reset-names = "nand", "reg";
+			resets = <&sys_rst 2>, <&sys_rst 2>;
 		};
 
-		emmc: sdhc@68400000 {
+		emmc: mmc@68400000 {
 			compatible = "socionext,uniphier-sd-v3.1";
 			status = "disabled";
 			reg = <0x68400000 0x800>;
@@ -518,7 +519,7 @@
 			non-removable;
 		};
 
-		sd: sdhc@68800000 {
+		sd: mmc@68800000 {
 			compatible = "socionext,uniphier-sd-v3.1";
 			status = "disabled";
 			reg = <0x68800000 0x800>;
diff --git a/arch/arm/dts/uniphier-pxs2-gentil.dts b/arch/arm/dts/uniphier-pxs2-gentil.dts
index b13d6277bf..e27fd4f2a5 100644
--- a/arch/arm/dts/uniphier-pxs2-gentil.dts
+++ b/arch/arm/dts/uniphier-pxs2-gentil.dts
@@ -48,10 +48,9 @@
 	status = "okay";
 
 	eeprom@54 {
-		compatible = "st,24c64", "atmel,24c64", "i2c-eeprom";
+		compatible = "st,24c64", "atmel,24c64";
 		reg = <0x54>;
 		pagesize = <32>;
-		u-boot,i2c-offset-len = <2>;
 	};
 };
 
diff --git a/arch/arm/dts/uniphier-pxs2.dtsi b/arch/arm/dts/uniphier-pxs2.dtsi
index 4e11e85d8d..8d968d3681 100644
--- a/arch/arm/dts/uniphier-pxs2.dtsi
+++ b/arch/arm/dts/uniphier-pxs2.dtsi
@@ -157,7 +157,7 @@
 		ranges;
 		interrupt-parent = <&intc>;
 
-		l2: l2-cache@500c0000 {
+		l2: cache-controller@500c0000 {
 			compatible = "socionext,uniphier-system-cache";
 			reg = <0x500c0000 0x2000>, <0x503c0100 0x8>,
 			      <0x506c0000 0x400>;
@@ -446,7 +446,7 @@
 			};
 		};
 
-		emmc: sdhc@5a000000 {
+		emmc: mmc@5a000000 {
 			compatible = "socionext,uniphier-sd-v3.1.1";
 			status = "disabled";
 			reg = <0x5a000000 0x800>;
@@ -462,7 +462,7 @@
 			non-removable;
 		};
 
-		sd: sdhc@5a400000 {
+		sd: mmc@5a400000 {
 			compatible = "socionext,uniphier-sd-v3.1.1";
 			status = "disabled";
 			reg = <0x5a400000 0x800>;
@@ -508,7 +508,7 @@
 			};
 		};
 
-		aidet: aidet@5fc20000 {
+		aidet: interrupt-controller@5fc20000 {
 			compatible = "socionext,uniphier-pxs2-aidet";
 			reg = <0x5fc20000 0x200>;
 			interrupt-controller;
@@ -799,7 +799,7 @@
 			};
 		};
 
-		nand: nand@68000000 {
+		nand: nand-controller@68000000 {
 			compatible = "socionext,uniphier-denali-nand-v5b";
 			status = "disabled";
 			reg-names = "nand_data", "denali_reg";
@@ -809,7 +809,8 @@
 			pinctrl-0 = <&pinctrl_nand2cs>;
 			clock-names = "nand", "nand_x", "ecc";
 			clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
-			resets = <&sys_rst 2>;
+			reset-names = "nand", "reg";
+			resets = <&sys_rst 2>, <&sys_rst 2>;
 		};
 	};
 };
diff --git a/arch/arm/dts/uniphier-pxs3.dtsi b/arch/arm/dts/uniphier-pxs3.dtsi
index b1aff285c8..ed079c1711 100644
--- a/arch/arm/dts/uniphier-pxs3.dtsi
+++ b/arch/arm/dts/uniphier-pxs3.dtsi
@@ -353,7 +353,7 @@
 			};
 		};
 
-		emmc: sdhc@5a000000 {
+		emmc: mmc@5a000000 {
 			compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc";
 			reg = <0x5a000000 0x400>;
 			interrupts = <0 78 4>;
@@ -372,7 +372,7 @@
 			cdns,phy-dll-delay-sdclk-hsmmc = <21>;
 		};
 
-		sd: sdhc@5a400000 {
+		sd: mmc@5a400000 {
 			compatible = "socionext,uniphier-sd-v3.1.1";
 			status = "disabled";
 			reg = <0x5a400000 0x800>;
@@ -462,7 +462,7 @@
 			};
 		};
 
-		aidet: aidet@5fc20000 {
+		aidet: interrupt-controller@5fc20000 {
 			compatible = "socionext,uniphier-pxs3-aidet";
 			reg = <0x5fc20000 0x200>;
 			interrupt-controller;
@@ -821,7 +821,7 @@
 			socionext,syscon = <&soc_glue>;
 		};
 
-		nand: nand@68000000 {
+		nand: nand-controller@68000000 {
 			compatible = "socionext,uniphier-denali-nand-v5b";
 			status = "disabled";
 			reg-names = "nand_data", "denali_reg";
@@ -831,7 +831,8 @@
 			pinctrl-0 = <&pinctrl_nand>;
 			clock-names = "nand", "nand_x", "ecc";
 			clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
-			resets = <&sys_rst 2>;
+			reset-names = "nand", "reg";
+			resets = <&sys_rst 2>, <&sys_rst 2>;
 		};
 	};
 };
diff --git a/arch/arm/dts/uniphier-ref-daughter.dtsi b/arch/arm/dts/uniphier-ref-daughter.dtsi
index 9240a313b9..a11897669c 100644
--- a/arch/arm/dts/uniphier-ref-daughter.dtsi
+++ b/arch/arm/dts/uniphier-ref-daughter.dtsi
@@ -7,9 +7,8 @@
 
 &i2c0 {
 	eeprom@50 {
-		compatible = "microchip,24lc128", "i2c-eeprom";
+		compatible = "microchip,24lc128", "atmel,24c128";
 		reg = <0x50>;
 		pagesize = <64>;
-		u-boot,i2c-offset-len = <2>;
 	};
 };
diff --git a/arch/arm/dts/uniphier-sld8.dtsi b/arch/arm/dts/uniphier-sld8.dtsi
index efce02768b..393157eb14 100644
--- a/arch/arm/dts/uniphier-sld8.dtsi
+++ b/arch/arm/dts/uniphier-sld8.dtsi
@@ -51,7 +51,7 @@
 		ranges;
 		interrupt-parent = <&intc>;
 
-		l2: l2-cache@500c0000 {
+		l2: cache-controller@500c0000 {
 			compatible = "socionext,uniphier-system-cache";
 			reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
 			      <0x506c0000 0x400>;
@@ -249,7 +249,7 @@
 			#dma-cells = <1>;
 		};
 
-		sd: sdhc@5a400000 {
+		sd: mmc@5a400000 {
 			compatible = "socionext,uniphier-sd-v2.91";
 			status = "disabled";
 			reg = <0x5a400000 0x200>;
@@ -269,7 +269,7 @@
 			sd-uhs-sdr50;
 		};
 
-		emmc: sdhc@5a500000 {
+		emmc: mmc@5a500000 {
 			compatible = "socionext,uniphier-sd-v2.91";
 			status = "disabled";
 			reg = <0x5a500000 0x200>;
@@ -379,7 +379,7 @@
 			interrupt-controller;
 		};
 
-		aidet: aidet@61830000 {
+		aidet: interrupt-controller@61830000 {
 			compatible = "socionext,uniphier-sld8-aidet";
 			reg = <0x61830000 0x200>;
 			interrupt-controller;
@@ -402,7 +402,7 @@
 			};
 		};
 
-		nand: nand@68000000 {
+		nand: nand-controller@68000000 {
 			compatible = "socionext,uniphier-denali-nand-v5a";
 			status = "disabled";
 			reg-names = "nand_data", "denali_reg";
@@ -412,7 +412,8 @@
 			pinctrl-0 = <&pinctrl_nand2cs>;
 			clock-names = "nand", "nand_x", "ecc";
 			clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
-			resets = <&sys_rst 2>;
+			reset-names = "nand", "reg";
+			resets = <&sys_rst 2>, <&sys_rst 2>;
 		};
 	};
 };
diff --git a/arch/arm/mach-uniphier/Makefile b/arch/arm/mach-uniphier/Makefile
index 115af244cd..769778cf50 100644
--- a/arch/arm/mach-uniphier/Makefile
+++ b/arch/arm/mach-uniphier/Makefile
@@ -22,6 +22,7 @@ endif
 obj-$(CONFIG_MICRO_SUPPORT_CARD) += micro-support-card.o
 obj-y += pinctrl-glue.o
 obj-$(CONFIG_MMC) += mmc-first-dev.o
+obj-$(CONFIG_NAND_DENALI) += nand-reset.o
 obj-y += fdt-fixup.o
 
 endif
diff --git a/arch/arm/mach-uniphier/board_init.c b/arch/arm/mach-uniphier/board_init.c
index 99727a3004..4f9cd6e722 100644
--- a/arch/arm/mach-uniphier/board_init.c
+++ b/arch/arm/mach-uniphier/board_init.c
@@ -141,6 +141,10 @@ int board_init(void)
 
 	support_card_late_init();
 
+	led_puts("U4");
+
+	uniphier_nand_reset_assert();
+
 	led_puts("Uboo");
 
 	return 0;
diff --git a/arch/arm/mach-uniphier/board_late_init.c b/arch/arm/mach-uniphier/board_late_init.c
index 793283058c..378aad0c9c 100644
--- a/arch/arm/mach-uniphier/board_late_init.c
+++ b/arch/arm/mach-uniphier/board_late_init.c
@@ -14,25 +14,9 @@
 #include <stdio.h>
 #include <linux/io.h>
 #include <linux/printk.h>
-#include <../drivers/mtd/nand/raw/denali.h>
 
 #include "init.h"
 
-static void nand_denali_wp_disable(void)
-{
-#ifdef CONFIG_NAND_DENALI
-	/*
-	 * Since the boot rom enables the write protection for NAND boot mode,
-	 * it must be disabled somewhere for "nand write", "nand erase", etc.
-	 * The workaround is here to not disturb the Denali NAND controller
-	 * driver just for a really SoC-specific thing.
-	 */
-	void __iomem *denali_reg = (void __iomem *)CONFIG_SYS_NAND_REGS_BASE;
-
-	writel(WRITE_PROTECT__FLAG, denali_reg + WRITE_PROTECT);
-#endif
-}
-
 static void uniphier_set_env_fdt_file(void)
 {
 	DECLARE_GLOBAL_DATA_PTR;
@@ -114,7 +98,6 @@ int board_late_init(void)
 	case BOOT_DEVICE_NAND:
 		printf("NAND Boot");
 		env_set("bootdev", "nand");
-		nand_denali_wp_disable();
 		break;
 	case BOOT_DEVICE_NOR:
 		printf("NOR Boot");
diff --git a/arch/arm/mach-uniphier/clk/clk-early-ld4.c b/arch/arm/mach-uniphier/clk/clk-early-ld4.c
index f32f78dd26..0f9ce65097 100644
--- a/arch/arm/mach-uniphier/clk/clk-early-ld4.c
+++ b/arch/arm/mach-uniphier/clk/clk-early-ld4.c
@@ -15,13 +15,6 @@ void uniphier_ld4_early_clk_init(void)
 {
 	u32 tmp;
 
-	/* deassert reset */
-	if (spl_boot_device() != BOOT_DEVICE_NAND) {
-		tmp = readl(sc_base + SC_RSTCTRL);
-		tmp &= ~SC_RSTCTRL_NRST_NAND;
-		writel(tmp, sc_base + SC_RSTCTRL);
-	};
-
 	/* provide clocks */
 	tmp = readl(sc_base + SC_CLKCTRL);
 	tmp |= SC_CLKCTRL_CEN_SBC | SC_CLKCTRL_CEN_PERI;
diff --git a/arch/arm/mach-uniphier/init.h b/arch/arm/mach-uniphier/init.h
index 9dc5b885a5..3c77f48853 100644
--- a/arch/arm/mach-uniphier/init.h
+++ b/arch/arm/mach-uniphier/init.h
@@ -101,6 +101,14 @@ unsigned int uniphier_boot_device_raw(void);
 int uniphier_have_internal_stm(void);
 int uniphier_boot_from_backend(void);
 int uniphier_pin_init(const char *pinconfig_name);
+
+#ifdef CONFIG_NAND_DENALI
+void uniphier_nand_reset_assert(void);
+#else
+static inline void uniphier_nand_reset_assert(void)
+{
+}
+#endif
 #ifdef CONFIG_ARM64
 void uniphier_mem_map_init(unsigned long dram_base, unsigned long dram_size);
 #else
diff --git a/arch/arm/mach-uniphier/micro-support-card.c b/arch/arm/mach-uniphier/micro-support-card.c
index 46879019fd..c71470a204 100644
--- a/arch/arm/mach-uniphier/micro-support-card.c
+++ b/arch/arm/mach-uniphier/micro-support-card.c
@@ -1,39 +1,58 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright (C) 2012-2015 Panasonic Corporation
- * Copyright (C) 2015-2016 Socionext Inc.
+ * Copyright (C) 2015-2020 Socionext Inc.
  *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
  */
 
 #include <common.h>
+#include <dm/of.h>
+#include <fdt_support.h>
 #include <linux/ctype.h>
 #include <linux/io.h>
 
 #include "micro-support-card.h"
 
-#define MICRO_SUPPORT_CARD_BASE		0x43f00000
-#define SMC911X_BASE			((MICRO_SUPPORT_CARD_BASE) + 0x00000)
-#define LED_BASE			((MICRO_SUPPORT_CARD_BASE) + 0x90000)
-#define NS16550A_BASE			((MICRO_SUPPORT_CARD_BASE) + 0xb0000)
-#define MICRO_SUPPORT_CARD_RESET	((MICRO_SUPPORT_CARD_BASE) + 0xd0034)
-#define MICRO_SUPPORT_CARD_REVISION	((MICRO_SUPPORT_CARD_BASE) + 0xd00E0)
+#define SMC911X_OFFSET			0x00000
+#define LED_OFFSET			0x90000
+#define NS16550A_OFFSET			0xb0000
+#define MICRO_SUPPORT_CARD_RESET	0xd0034
+#define MICRO_SUPPORT_CARD_REVISION	0xd00e0
 
 static bool support_card_found;
+static void __iomem *support_card_base;
 
 static void support_card_detect(void)
 {
 	DECLARE_GLOBAL_DATA_PTR;
 	const void *fdt = gd->fdt_blob;
 	int offset;
+	u64 addr, addr2;
 
 	offset = fdt_node_offset_by_compatible(fdt, 0, "smsc,lan9118");
 	if (offset < 0)
 		return;
 
+	addr = fdt_get_base_address(fdt, offset);
+	if (addr == OF_BAD_ADDR)
+		return;
+	addr -= SMC911X_OFFSET;
+
 	offset = fdt_node_offset_by_compatible(fdt, 0, "ns16550a");
 	if (offset < 0)
 		return;
 
+	addr2 = fdt_get_base_address(fdt, offset);
+	if (addr2 == OF_BAD_ADDR)
+		return;
+	addr2 -= NS16550A_OFFSET;
+
+	/* sanity check */
+	if (addr != addr2)
+		return;
+
+	support_card_base = ioremap(addr, 0x100000);
+
 	support_card_found = true;
 }
 
@@ -45,19 +64,19 @@ static void support_card_detect(void)
  */
 static void support_card_reset_deassert(void)
 {
-	writel(0x00010000, MICRO_SUPPORT_CARD_RESET);
+	writel(0x00010000, support_card_base + MICRO_SUPPORT_CARD_RESET);
 }
 
 static void support_card_reset(void)
 {
-	writel(0x00020003, MICRO_SUPPORT_CARD_RESET);
+	writel(0x00020003, support_card_base + MICRO_SUPPORT_CARD_RESET);
 }
 
 static int support_card_show_revision(void)
 {
 	u32 revision;
 
-	revision = readl(MICRO_SUPPORT_CARD_REVISION);
+	revision = readl(support_card_base + MICRO_SUPPORT_CARD_REVISION);
 	revision &= 0xff;
 
 	/* revision 3.6.x card changed the revision format */
@@ -94,7 +113,7 @@ int board_eth_init(bd_t *bis)
 	if (!support_card_found)
 		return 0;
 
-	return smc911x_initialize(0, SMC911X_BASE);
+	return smc911x_initialize(0, (unsigned long)support_card_base + SMC911X_OFFSET);
 }
 #endif
 
@@ -264,5 +283,5 @@ void led_puts(const char *s)
 			s++;
 	}
 
-	writel(~val, LED_BASE);
+	writel(~val, support_card_base + LED_OFFSET);
 }
diff --git a/arch/arm/mach-uniphier/mmc-first-dev.c b/arch/arm/mach-uniphier/mmc-first-dev.c
index 149e662070..e2f4f4eb5c 100644
--- a/arch/arm/mach-uniphier/mmc-first-dev.c
+++ b/arch/arm/mach-uniphier/mmc-first-dev.c
@@ -9,13 +9,14 @@
 #include <mmc.h>
 #include <linux/errno.h>
 
-static int find_first_mmc_device(void)
+static int find_first_mmc_device(bool is_sd)
 {
 	struct mmc *mmc;
 	int i;
 
 	for (i = 0; (mmc = find_mmc_device(i)); i++) {
-		if (!mmc_init(mmc) && IS_MMC(mmc))
+		if (!mmc_init(mmc) &&
+		    ((is_sd && IS_SD(mmc)) || (!is_sd && IS_MMC(mmc))))
 			return i;
 	}
 
@@ -24,14 +25,14 @@ static int find_first_mmc_device(void)
 
 int mmc_get_env_dev(void)
 {
-	return find_first_mmc_device();
+	return find_first_mmc_device(false);
 }
 
 static int do_mmcsetn(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
 	int dev;
 
-	dev = find_first_mmc_device();
+	dev = find_first_mmc_device(false);
 	if (dev < 0)
 		return CMD_RET_FAILURE;
 
@@ -44,3 +45,21 @@ U_BOOT_CMD(
 	"Set the first MMC (not SD) dev number to \"mmc_first_dev\" environment",
 	""
 );
+
+static int do_sdsetn(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	int dev;
+
+	dev = find_first_mmc_device(true);
+	if (dev < 0)
+		return CMD_RET_FAILURE;
+
+	env_set_ulong("sd_first_dev", dev);
+	return CMD_RET_SUCCESS;
+}
+
+U_BOOT_CMD(
+	sdsetn,	1,	1,	do_sdsetn,
+	"Set the first SD dev number to \"sd_first_dev\" environment",
+	""
+);
diff --git a/arch/arm/mach-uniphier/nand-reset.c b/arch/arm/mach-uniphier/nand-reset.c
new file mode 100644
index 0000000000..11cadaabd8
--- /dev/null
+++ b/arch/arm/mach-uniphier/nand-reset.c
@@ -0,0 +1,43 @@
+// SPDX-License-Identifier: GPL-2.0 or later
+/*
+ * Copyright (C) 2020 Socionext Inc.
+ *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ */
+
+#include <linux/errno.h>
+#include <dm.h>
+#include <dm/uclass-internal.h>
+#include <reset.h>
+
+#include "init.h"
+
+/*
+ * Assert the Denali NAND controller reset if found.
+ *
+ * On LD4, the bootstrap process starts running after power-on reset regardless
+ * of the boot mode, here the pin-mux is not necessarily set up for NAND, then
+ * the controller is stuck. Assert the controller reset here, and should be
+ * deasserted in the driver after the pin-mux is correctly handled. For other
+ * SoCs, the bootstrap runs only when the boot mode selects ONFi, but it is yet
+ * effective when the boot swap is on. So, the reset should be asserted anyway.
+ */
+void uniphier_nand_reset_assert(void)
+{
+	struct udevice *dev;
+	struct reset_ctl_bulk resets;
+	int ret;
+
+	ret = uclass_find_first_device(UCLASS_MTD, &dev);
+	if (ret || !dev)
+		return;
+
+	/* make sure this is the Denali NAND controller */
+	if (strcmp(dev->driver->name, "denali-nand-dt"))
+		return;
+
+	ret = reset_get_bulk(dev, &resets);
+	if (ret)
+		return;
+
+	reset_assert_bulk(&resets);
+}