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| author | Marek Vasut <marex@denx.de> | 2020-03-31 20:51:28 +0300 |
|---|---|---|
| committer | Patrick Delaunay <patrick.delaunay@st.com> | 2020-04-01 12:57:31 +0300 |
| commit | 2f0b5d930d3b2100917077ef7217e77c3c9ae956 (patch) | |
| tree | 577944e8de8ff6de7dc7f0ece735f5c47979a02a /arch | |
| parent | df7f49ca27b8951e440a36dd0ef10b1af2a68c6a (diff) | |
| download | u-boot-2f0b5d930d3b2100917077ef7217e77c3c9ae956.tar.xz | |
ARM: dts: stm32: Add QSPI NOR on AV96
The DH Electronics DHCOR SOM has QSPI NOR on the SoM itself, add it
into the DT.
Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Change-Id: Ia7c454c496f50e3fc4851ec1154f3641c416e98e
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/dts/stm32mp157a-avenger96.dts | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/arch/arm/dts/stm32mp157a-avenger96.dts b/arch/arm/dts/stm32mp157a-avenger96.dts index 3fca1ed56d..023390a662 100644 --- a/arch/arm/dts/stm32mp157a-avenger96.dts +++ b/arch/arm/dts/stm32mp157a-avenger96.dts @@ -20,6 +20,7 @@ mmc0 = &sdmmc1; serial0 = &uart4; serial1 = &uart7; + spi0 = &qspi; }; chosen { @@ -300,6 +301,25 @@ vdd_3v3_usbfs-supply = <&vdd_usb>; }; +&qspi { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a>; + pinctrl-1 = <&qspi_clk_sleep_pins_a &qspi_bk1_sleep_pins_a>; + reg = <0x58003000 0x1000>, <0x70000000 0x200000>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + flash0: spi-flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-rx-bus-width = <4>; + spi-max-frequency = <108000000>; + #address-cells = <1>; + #size-cells = <1>; + }; +}; + &rng1 { status = "okay"; }; |