diff options
| author | yanhong.wang <yanhong.wang@starfivetech.com> | 2022-05-25 08:55:58 +0300 |
|---|---|---|
| committer | Yanhong Wang <yanhong.wang@linux.starfivetech.com> | 2022-10-18 11:24:36 +0300 |
| commit | 5531f12c6efc79817914bf96f5b755840402e8c7 (patch) | |
| tree | 33e78ded34d43d9209dfd94df149d4e7f6c31389 /arch | |
| parent | 0b2572d9978f265b51a218f334434ab9fde41552 (diff) | |
| download | u-boot-5531f12c6efc79817914bf96f5b755840402e8c7.tar.xz | |
board:starfive:evb: add usb init config
Add usb init config for starfive EVB board. Default set to USB2.0
Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
Diffstat (limited to 'arch')
| -rwxr-xr-x | arch/riscv/include/asm/arch-jh7110/jh7110-regs.h | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/arch/riscv/include/asm/arch-jh7110/jh7110-regs.h b/arch/riscv/include/asm/arch-jh7110/jh7110-regs.h index 7ebe23adef..0672ee0d8d 100755 --- a/arch/riscv/include/asm/arch-jh7110/jh7110-regs.h +++ b/arch/riscv/include/asm/arch-jh7110/jh7110-regs.h @@ -30,6 +30,10 @@ /*usb cfg*/ #define STG_SYSCON_4 0x4U +#define STG_SYSCON_196 0xC4U +#define STG_SYSCON_328 0x148U +#define STG_SYSCON_500 0x1F4U + #define SYS_SYSCON_24 0x18U #define SYS_SYSCON_28 0x1CU #define SYS_SYSCON_32 0x20U @@ -49,6 +53,20 @@ #define PDRSTN_SPLIT_MASK 0x20000U #define IOMUX_USB_SHIFT 0x10U #define IOMUX_USB_MASK 0x7F0000U +#define PCIE_CKREF_SRC_SHIFT 0x12U +#define PCIE_CKREF_SRC_MASK 0xC0000U +#define PCIE_CLK_SEL_SHIFT 0x14U +#define PCIE_CLK_SEL_MASK 0x300000U +#define PCIE_PHY_MODE_SHIFT 0x14U +#define PCIE_PHY_MODE_MASK 0x300000U +#define PCIE_USB3_BUS_WIDTH_SHIFT 0x2U +#define PCIE_USB3_BUS_WIDTH_MASK 0xCU +#define PCIE_USB3_RATE_SHIFT 0x5U +#define PCIE_USB3_RATE_MASK 0x60U +#define PCIE_USB3_RX_STANDBY_SHIFT 0x7U +#define PCIE_USB3_RX_STANDBY_MASK 0x80U +#define PCIE_USB3_PHY_ENABLE_SHIFT 0x4U +#define PCIE_USB3_PHY_ENABLE_MASK 0x10U /*timer cfg*/ #define TIMER_CLK_APB_SHIFT 0x1F0U |