Merge branch 'master' of https://gitlab.denx.de/u-boot/custodians/u-boot-tegra

- Add support for Jetson Nano, plus miscellaneous other fixes found
  during Nano bringup.
- Add Igor's update_uboot wrapper patches.

13 files changed, 273 insertions, 249 deletions

diff --git a/arch/arm/cpu/armv8/cpu.c b/arch/arm/cpu/armv8/cpu.c
index 2467e0b87b..35752037bc 100644
--- a/arch/arm/cpu/armv8/cpu.c
+++ b/arch/arm/cpu/armv8/cpu.c
@@ -32,6 +32,8 @@ void sdelay(unsigned long loops)
 			  "b.ne 1b" : "=r" (loops) : "0"(loops) : "cc");
 }
 
+void __weak board_cleanup_before_linux(void){}
+
 int cleanup_before_linux(void)
 {
 	/*
@@ -40,6 +42,9 @@ int cleanup_before_linux(void)
 	 *
 	 * disable interrupt and turn off caches etc ...
 	 */
+
+	board_cleanup_before_linux();
+
 	disable_interrupts();
 
 	/*
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 9c593b2c98..820ee9733a 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -180,7 +180,8 @@ dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \
 	tegra210-e2220-1170.dtb \
 	tegra210-p2371-0000.dtb \
 	tegra210-p2371-2180.dtb \
-	tegra210-p2571.dtb
+	tegra210-p2571.dtb \
+	tegra210-p3450-0000.dtb
 
 dtb-$(CONFIG_ARCH_MVEBU) +=			\
 	armada-3720-db.dtb			\
diff --git a/arch/arm/dts/tegra210-p2371-2180.dts b/arch/arm/dts/tegra210-p2371-2180.dts
index c2f497c524..649c163152 100644
--- a/arch/arm/dts/tegra210-p2371-2180.dts
+++ b/arch/arm/dts/tegra210-p2371-2180.dts
@@ -12,6 +12,8 @@
 
 	aliases {
 		i2c0 = "/i2c@7000d000";
+		i2c2 = "/i2c@7000c400";
+		i2c3 = "/i2c@7000c500";
 		mmc0 = "/sdhci@700b0600";
 		mmc1 = "/sdhci@700b0000";
 		usb0 = "/usb@7d000000";
@@ -85,6 +87,16 @@
 		non-removable;
 	};
 
+	i2c@7000c400 {
+		status = "okay";
+		clock-frequency = <400000>;
+	};
+
+	i2c@7000c500 {
+		status = "okay";
+		clock-frequency = <400000>;
+	};
+
 	i2c@7000d000 {
 		status = "okay";
 		clock-frequency = <400000>;
diff --git a/arch/arm/dts/tegra210-p3450-0000.dts b/arch/arm/dts/tegra210-p3450-0000.dts
new file mode 100644
index 0000000000..9ef744ac8b
--- /dev/null
+++ b/arch/arm/dts/tegra210-p3450-0000.dts
@@ -0,0 +1,147 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ *  (C) Copyright 2019-2020 NVIDIA Corporation <www.nvidia.com>
+ */
+/dts-v1/;
+
+#include "tegra210.dtsi"
+
+/ {
+	model = "NVIDIA Jetson Nano Developer Kit";
+	compatible = "nvidia,p3450-0000", "nvidia,tegra210";
+
+	chosen {
+		stdout-path = &uarta;
+	};
+
+	aliases {
+		ethernet = "/pcie@1003000/pci@2,0/ethernet@0,0";
+		i2c0 = "/i2c@7000d000";
+		i2c2 = "/i2c@7000c400";
+		i2c3 = "/i2c@7000c500";
+		i2c4 = "/i2c@7000c700";
+		mmc0 = "/sdhci@700b0600";
+		mmc1 = "/sdhci@700b0000";
+		spi0 = "/spi@70410000";
+		usb0 = "/usb@7d000000";
+	};
+
+	memory {
+		reg = <0x0 0x80000000 0x0 0xc0000000>;
+	};
+
+	pcie@1003000 {
+		status = "okay";
+
+		pci@1,0 {
+			status = "okay";
+		};
+
+		pci@2,0 {
+			status = "okay";
+
+			ethernet@0,0 {
+				reg = <0x000000 0 0 0 0>;
+				local-mac-address = [ 00 00 00 00 00 00 ];
+			};
+		};
+	};
+
+	serial@70006000 {
+		status = "okay";
+	};
+
+	padctl@7009f000 {
+		pinctrl-0 = <&padctl_default>;
+		pinctrl-names = "default";
+
+		padctl_default: pinmux {
+			xusb {
+				nvidia,lanes = "otg-1", "otg-2";
+				nvidia,function = "xusb";
+				nvidia,iddq = <0>;
+			};
+
+			usb3 {
+				nvidia,lanes = "pcie-5", "pcie-6";
+				nvidia,function = "usb3";
+				nvidia,iddq = <0>;
+			};
+
+			pcie-x1 {
+				nvidia,lanes = "pcie-0";
+				nvidia,function = "pcie-x1";
+				nvidia,iddq = <0>;
+			};
+
+			pcie-x4 {
+				nvidia,lanes = "pcie-1", "pcie-2",
+					       "pcie-3", "pcie-4";
+				nvidia,function = "pcie-x4";
+				nvidia,iddq = <0>;
+			};
+
+			sata {
+				nvidia,lanes = "sata-0";
+				nvidia,function = "sata";
+				nvidia,iddq = <0>;
+			};
+		};
+	};
+
+	sdhci@700b0000 {
+		status = "okay";
+		cd-gpios = <&gpio TEGRA_GPIO(Z, 1) GPIO_ACTIVE_LOW>;
+		power-gpios = <&gpio TEGRA_GPIO(Z, 3) GPIO_ACTIVE_HIGH>;
+		bus-width = <4>;
+	};
+
+	sdhci@700b0600 {
+		status = "okay";
+		bus-width = <8>;
+		non-removable;
+	};
+
+	i2c@7000c400 {
+		status = "okay";
+		clock-frequency = <400000>;
+	};
+
+	i2c@7000c500 {
+		status = "okay";
+		clock-frequency = <400000>;
+	};
+
+	i2c@7000c700 {
+		status = "okay";
+		clock-frequency = <400000>;
+	};
+
+	i2c@7000d000 {
+		status = "okay";
+		clock-frequency = <400000>;
+	};
+
+	spi@70410000 {
+		status = "okay";
+		spi-max-frequency = <80000000>;
+	};
+
+	usb@7d000000 {
+		status = "okay";
+		dr_mode = "peripheral";
+	};
+
+	clocks {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		clk32k_in: clock@0 {
+			compatible = "fixed-clock";
+			reg = <0>;
+			#clock-cells = <0>;
+			clock-frequency = <32768>;
+		};
+	};
+};
diff --git a/arch/arm/include/asm/arch-tegra/tegra_mmc.h b/arch/arm/include/asm/arch-tegra/tegra_mmc.h
index a2b6f63ff0..70dcf4aa66 100644
--- a/arch/arm/include/asm/arch-tegra/tegra_mmc.h
+++ b/arch/arm/include/asm/arch-tegra/tegra_mmc.h
@@ -2,7 +2,7 @@
 /*
  * (C) Copyright 2009 SAMSUNG Electronics
  * Minkyu Kang <mk7.kang@samsung.com>
- * Portions Copyright (C) 2011-2012 NVIDIA Corporation
+ * Portions Copyright (C) 2011-2012,2019 NVIDIA Corporation
  */
 
 #ifndef __TEGRA_MMC_H_
@@ -52,7 +52,7 @@ struct tegra_mmc {
 	unsigned char	admaerr;	/* offset 54h */
 	unsigned char	res4[3];	/* RESERVED, offset 55h-57h */
 	unsigned long	admaaddr;	/* offset 58h-5Fh */
-	unsigned char	res5[0xa0];	/* RESERVED, offset 60h-FBh */
+	unsigned char	res5[0x9c];	/* RESERVED, offset 60h-FBh */
 	unsigned short	slotintstatus;	/* offset FCh */
 	unsigned short	hcver;		/* HOST Version */
 	unsigned int	venclkctl;	/* _VENDOR_CLOCK_CNTRL_0,    100h */
@@ -127,11 +127,23 @@ struct tegra_mmc {
 
 #define TEGRA_MMC_NORINTSIGEN_XFER_COMPLETE			(1 << 1)
 
-/* SDMMC1/3 settings from section 24.6 of T30 TRM */
+/* SDMMC1/3 settings from SDMMCx Initialization Sequence of TRM */
 #define MEMCOMP_PADCTRL_VREF	7
-#define AUTO_CAL_ENABLED	(1 << 29)
+#define AUTO_CAL_ENABLE		(1 << 29)
+#define AUTO_CAL_ACTIVE		(1 << 31)
+#define AUTO_CAL_START		(1 << 31)
+#if defined(CONFIG_TEGRA210)
+#define AUTO_CAL_PD_OFFSET	(0x7D << 8)
+#define AUTO_CAL_PU_OFFSET	(0 << 0)
+#define IO_TRIM_BYPASS_MASK	(1 << 2)
+#define TRIM_VAL_SHIFT		24
+#define TRIM_VAL_MASK		(0x1F << TRIM_VAL_SHIFT)
+#define TAP_VAL_SHIFT		16
+#define TAP_VAL_MASK		(0xFF << TAP_VAL_SHIFT)
+#else
 #define AUTO_CAL_PD_OFFSET	(0x70 << 8)
 #define AUTO_CAL_PU_OFFSET	(0x62 << 0)
+#endif
 
 #endif	/* __ASSEMBLY__ */
 #endif	/* __TEGRA_MMC_H_ */
diff --git a/arch/arm/include/asm/arch-tegra/xusb-padctl.h b/arch/arm/include/asm/arch-tegra/xusb-padctl.h
index deccdf455d..7e14d8109d 100644
--- a/arch/arm/include/asm/arch-tegra/xusb-padctl.h
+++ b/arch/arm/include/asm/arch-tegra/xusb-padctl.h
@@ -16,6 +16,7 @@ struct tegra_xusb_phy;
 struct tegra_xusb_phy *tegra_xusb_phy_get(unsigned int type);
 
 void tegra_xusb_padctl_init(void);
+void tegra_xusb_padctl_exit(void);
 int tegra_xusb_phy_prepare(struct tegra_xusb_phy *phy);
 int tegra_xusb_phy_enable(struct tegra_xusb_phy *phy);
 int tegra_xusb_phy_disable(struct tegra_xusb_phy *phy);
diff --git a/arch/arm/mach-tegra/board2.c b/arch/arm/mach-tegra/board2.c
index d3497a2673..224efc97c5 100644
--- a/arch/arm/mach-tegra/board2.c
+++ b/arch/arm/mach-tegra/board2.c
@@ -181,6 +181,12 @@ int board_init(void)
 	return nvidia_board_init();
 }
 
+void board_cleanup_before_linux(void)
+{
+	/* power down UPHY PLL */
+	tegra_xusb_padctl_exit();
+}
+
 #ifdef CONFIG_BOARD_EARLY_INIT_F
 static void __gpio_early_init(void)
 {
@@ -211,6 +217,31 @@ int board_early_init_f(void)
 		arch_timer_init();
 #endif
 
+#if defined(CONFIG_DISABLE_SDMMC1_EARLY)
+	/*
+	 * Turn off (reset/disable) SDMMC1 on Nano here, before GPIO INIT.
+	 * We do this because earlier bootloaders have enabled power to
+	 * SDMMC1 on Nano, and toggling power-gpio (PZ3) in pinmux_init()
+	 * results in power being back-driven into the SD-card and SDMMC1
+	 * HW, which is 'bad' as per the HW team.
+	 *
+	 * From the HW team: "LDO2 from the PMIC has already been set to 3.3v in
+	 * nvtboot/CBoot on Nano (for SD-card boot). So when U-Boot's GPIO_INIT
+	 * table sets PZ3 to OUT0 as per the pinmux spreadsheet, it turns off
+	 * the loadswitch. When PZ3 is 0 and not driving, essentially the SDCard
+	 * voltage turns off. Since the SDCard voltage is no longer there, the
+	 * SDMMC CLK/DAT lines are backdriving into what essentially is a
+	 * powered-off SDCard, that's why the voltage drops from 3.3V to ~1.6V"
+	 *
+	 * Note that this can probably be removed when we change over to storing
+	 * all BL components on QSPI on Nano, and U-Boot then becomes the first
+	 * one to turn on SDMMC1 power. Another fix would be to have CBoot
+	 * disable power/gate SDMMC1 off before handing off to U-Boot/kernel.
+	 */
+	reset_set_enable(PERIPH_ID_SDMMC1, 1);
+	clock_set_enable(PERIPH_ID_SDMMC1, 0);
+#endif	/* CONFIG_DISABLE_SDMMC1_EARLY */
+
 	pinmux_init();
 	board_init_uart_f();
 
diff --git a/arch/arm/mach-tegra/tegra210/Kconfig b/arch/arm/mach-tegra/tegra210/Kconfig
index 3637473051..97ed8e05f4 100644
--- a/arch/arm/mach-tegra/tegra210/Kconfig
+++ b/arch/arm/mach-tegra/tegra210/Kconfig
@@ -35,6 +35,12 @@ config TARGET_P2571
 	help
 	  P2571 is a P2530 married to a P1963 I/O board
 
+config TARGET_P3450_0000
+	bool "NVIDIA Jetson Nano Developer Kit"
+	select BOARD_LATE_INIT
+	help
+	  P3450-0000 is a P3448 CPU board married to a P3449 I/O board.
+
 endchoice
 
 config SYS_SOC
@@ -44,5 +50,6 @@ source "board/nvidia/e2220-1170/Kconfig"
 source "board/nvidia/p2371-0000/Kconfig"
 source "board/nvidia/p2371-2180/Kconfig"
 source "board/nvidia/p2571/Kconfig"
+source "board/nvidia/p3450-0000/Kconfig"
 
 endif
diff --git a/arch/arm/mach-tegra/tegra210/Makefile b/arch/arm/mach-tegra/tegra210/Makefile
index b6012fc7ba..cfcba5b68f 100644
--- a/arch/arm/mach-tegra/tegra210/Makefile
+++ b/arch/arm/mach-tegra/tegra210/Makefile
@@ -1,5 +1,5 @@
 #
-# (C) Copyright 2013-2015
+# (C) Copyright 2013-2020
 # NVIDIA Corporation <www.nvidia.com>
 #
 # SPDX-License-Identifier:     GPL-2.0+
@@ -7,6 +7,5 @@
 
 obj-y	+= clock.o
 obj-y	+= funcmux.o
-obj-y	+= pinmux.o
 obj-y	+= xusb-padctl.o
 obj-y	+= ../xusb-padctl-common.o
diff --git a/arch/arm/mach-tegra/tegra210/clock.c b/arch/arm/mach-tegra/tegra210/clock.c
index b240860f08..00c65c281f 100644
--- a/arch/arm/mach-tegra/tegra210/clock.c
+++ b/arch/arm/mach-tegra/tegra210/clock.c
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
- * (C) Copyright 2013-2015
+ * (C) Copyright 2013-2020
  * NVIDIA Corporation <www.nvidia.com>
  */
 
@@ -333,7 +333,7 @@ static enum clock_type_id clock_periph_type[PERIPHC_COUNT] = {
 	TYPE(PERIPHC_DMIC3,	CLOCK_TYPE_NONE),
 	TYPE(PERIPHC_APE,	CLOCK_TYPE_NONE),
 	TYPE(PERIPHC_QSPI,	CLOCK_TYPE_PC01C00_C42C41TC40),
-	TYPE(PERIPHC_VI_I2C,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_VI_I2C,	CLOCK_TYPE_PC2CC3M_T16),
 	TYPE(PERIPHC_USB2_HSIC_TRK, CLOCK_TYPE_NONE),
 	TYPE(PERIPHC_PEX_SATA_USB_RX_BYP, CLOCK_TYPE_NONE),
 
@@ -739,7 +739,7 @@ int get_periph_clock_info(enum periph_id periph_id, int *mux_bits,
 	if (!clock_periph_id_isvalid(periph_id))
 		return -1;
 
-	internal_id = periph_id_to_internal_id[periph_id];
+	internal_id = INTERNAL_ID(periph_id_to_internal_id[periph_id]);
 	if (!periphc_internal_id_isvalid(internal_id))
 		return -1;
 
@@ -765,7 +765,7 @@ enum clock_id get_periph_clock_id(enum periph_id periph_id, int source)
 	if (!clock_periph_id_isvalid(periph_id))
 		return CLOCK_ID_NONE;
 
-	internal_id = periph_id_to_internal_id[periph_id];
+	internal_id = INTERNAL_ID(periph_id_to_internal_id[periph_id]);
 	if (!periphc_internal_id_isvalid(internal_id))
 		return CLOCK_ID_NONE;
 
@@ -1235,25 +1235,6 @@ int tegra_plle_enable(void)
 	value &= ~PLLE_SS_CNTL_INTERP_RESET;
 	writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
 
-	/* 7. Enable HW power sequencer for PLLE */
-
-	value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC);
-	value &= ~PLLE_MISC_IDDQ_SWCTL;
-	writel(value, NV_PA_CLK_RST_BASE + PLLE_MISC);
-
-	value = readl(NV_PA_CLK_RST_BASE + PLLE_AUX);
-	value &= ~PLLE_AUX_SS_SWCTL;
-	value &= ~PLLE_AUX_ENABLE_SWCTL;
-	value |= PLLE_AUX_SS_SEQ_INCLUDE;
-	value |= PLLE_AUX_USE_LOCKDET;
-	writel(value, NV_PA_CLK_RST_BASE + PLLE_AUX);
-
-	/* 8. Wait 1 us */
-
-	udelay(1);
-	value |= PLLE_AUX_SEQ_ENABLE;
-	writel(value, NV_PA_CLK_RST_BASE + PLLE_AUX);
-
 	return 0;
 }
 
diff --git a/arch/arm/mach-tegra/tegra210/pinmux.c b/arch/arm/mach-tegra/tegra210/pinmux.c
deleted file mode 100644
index 615809990b..0000000000
--- a/arch/arm/mach-tegra/tegra210/pinmux.c
+++ /dev/null
@@ -1,194 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/pinmux.h>
-
-#define PIN(pin, f0, f1, f2, f3)	\
-	{				\
-		.funcs = {		\
-			PMUX_FUNC_##f0,	\
-			PMUX_FUNC_##f1,	\
-			PMUX_FUNC_##f2,	\
-			PMUX_FUNC_##f3,	\
-		},			\
-	}
-
-#define PIN_RESERVED {}
-
-static const struct pmux_pingrp_desc tegra210_pingroups[] = {
-	/*  pin,                  f0,         f1,     f2,    f3 */
-	/* Offset 0x3000 */
-	PIN(SDMMC1_CLK_PM0,       SDMMC1,     RSVD1,  RSVD2, RSVD3),
-	PIN(SDMMC1_CMD_PM1,       SDMMC1,     SPI3,   RSVD2, RSVD3),
-	PIN(SDMMC1_DAT3_PM2,      SDMMC1,     SPI3,   RSVD2, RSVD3),
-	PIN(SDMMC1_DAT2_PM3,      SDMMC1,     SPI3,   RSVD2, RSVD3),
-	PIN(SDMMC1_DAT1_PM4,      SDMMC1,     SPI3,   RSVD2, RSVD3),
-	PIN(SDMMC1_DAT0_PM5,      SDMMC1,     RSVD1,  RSVD2, RSVD3),
-	PIN_RESERVED,
-	/* Offset 0x301c */
-	PIN(SDMMC3_CLK_PP0,       SDMMC3,     RSVD1,  RSVD2, RSVD3),
-	PIN(SDMMC3_CMD_PP1,       SDMMC3,     RSVD1,  RSVD2, RSVD3),
-	PIN(SDMMC3_DAT0_PP5,      SDMMC3,     RSVD1,  RSVD2, RSVD3),
-	PIN(SDMMC3_DAT1_PP4,      SDMMC3,     RSVD1,  RSVD2, RSVD3),
-	PIN(SDMMC3_DAT2_PP3,      SDMMC3,     RSVD1,  RSVD2, RSVD3),
-	PIN(SDMMC3_DAT3_PP2,      SDMMC3,     RSVD1,  RSVD2, RSVD3),
-	PIN_RESERVED,
-	/* Offset 0x3038 */
-	PIN(PEX_L0_RST_N_PA0,     PE0,        RSVD1,  RSVD2, RSVD3),
-	PIN(PEX_L0_CLKREQ_N_PA1,  PE0,        RSVD1,  RSVD2, RSVD3),
-	PIN(PEX_WAKE_N_PA2,       PE,         RSVD1,  RSVD2, RSVD3),
-	PIN(PEX_L1_RST_N_PA3,     PE1,        RSVD1,  RSVD2, RSVD3),
-	PIN(PEX_L1_CLKREQ_N_PA4,  PE1,        RSVD1,  RSVD2, RSVD3),
-	PIN(SATA_LED_ACTIVE_PA5,  SATA,       RSVD1,  RSVD2, RSVD3),
-	PIN(SPI1_MOSI_PC0,        SPI1,       RSVD1,  RSVD2, RSVD3),
-	PIN(SPI1_MISO_PC1,        SPI1,       RSVD1,  RSVD2, RSVD3),
-	PIN(SPI1_SCK_PC2,         SPI1,       RSVD1,  RSVD2, RSVD3),
-	PIN(SPI1_CS0_PC3,         SPI1,       RSVD1,  RSVD2, RSVD3),
-	PIN(SPI1_CS1_PC4,         SPI1,       RSVD1,  RSVD2, RSVD3),
-	PIN(SPI2_MOSI_PB4,        SPI2,       DTV,    RSVD2, RSVD3),
-	PIN(SPI2_MISO_PB5,        SPI2,       DTV,    RSVD2, RSVD3),
-	PIN(SPI2_SCK_PB6,         SPI2,       DTV,    RSVD2, RSVD3),
-	PIN(SPI2_CS0_PB7,         SPI2,       DTV,    RSVD2, RSVD3),
-	PIN(SPI2_CS1_PDD0,        SPI2,       RSVD1,  RSVD2, RSVD3),
-	PIN(SPI4_MOSI_PC7,        SPI4,       RSVD1,  RSVD2, RSVD3),
-	PIN(SPI4_MISO_PD0,        SPI4,       RSVD1,  RSVD2, RSVD3),
-	PIN(SPI4_SCK_PC5,         SPI4,       RSVD1,  RSVD2, RSVD3),
-	PIN(SPI4_CS0_PC6,         SPI4,       RSVD1,  RSVD2, RSVD3),
-	PIN(QSPI_SCK_PEE0,        QSPI,       RSVD1,  RSVD2, RSVD3),
-	PIN(QSPI_CS_N_PEE1,       QSPI,       RSVD1,  RSVD2, RSVD3),
-	PIN(QSPI_IO0_PEE2,        QSPI,       RSVD1,  RSVD2, RSVD3),
-	PIN(QSPI_IO1_PEE3,        QSPI,       RSVD1,  RSVD2, RSVD3),
-	PIN(QSPI_IO2_PEE4,        QSPI,       RSVD1,  RSVD2, RSVD3),
-	PIN(QSPI_IO3_PEE5,        QSPI,       RSVD1,  RSVD2, RSVD3),
-	PIN_RESERVED,
-	/* Offset 0x30a4 */
-	PIN(DMIC1_CLK_PE0,        DMIC1,      I2S3,   RSVD2, RSVD3),
-	PIN(DMIC1_DAT_PE1,        DMIC1,      I2S3,   RSVD2, RSVD3),
-	PIN(DMIC2_CLK_PE2,        DMIC2,      I2S3,   RSVD2, RSVD3),
-	PIN(DMIC2_DAT_PE3,        DMIC2,      I2S3,   RSVD2, RSVD3),
-	PIN(DMIC3_CLK_PE4,        DMIC3,      I2S5A,  RSVD2, RSVD3),
-	PIN(DMIC3_DAT_PE5,        DMIC3,      I2S5A,  RSVD2, RSVD3),
-	PIN(GEN1_I2C_SCL_PJ1,     I2C1,       RSVD1,  RSVD2, RSVD3),
-	PIN(GEN1_I2C_SDA_PJ0,     I2C1,       RSVD1,  RSVD2, RSVD3),
-	PIN(GEN2_I2C_SCL_PJ2,     I2C2,       RSVD1,  RSVD2, RSVD3),
-	PIN(GEN2_I2C_SDA_PJ3,     I2C2,       RSVD1,  RSVD2, RSVD3),
-	PIN(GEN3_I2C_SCL_PF0,     I2C3,       RSVD1,  RSVD2, RSVD3),
-	PIN(GEN3_I2C_SDA_PF1,     I2C3,       RSVD1,  RSVD2, RSVD3),
-	PIN(CAM_I2C_SCL_PS2,      I2C3,       I2CVI,  RSVD2, RSVD3),
-	PIN(CAM_I2C_SDA_PS3,      I2C3,       I2CVI,  RSVD2, RSVD3),
-	PIN(PWR_I2C_SCL_PY3,      I2CPMU,     RSVD1,  RSVD2, RSVD3),
-	PIN(PWR_I2C_SDA_PY4,      I2CPMU,     RSVD1,  RSVD2, RSVD3),
-	PIN(UART1_TX_PU0,         UARTA,      RSVD1,  RSVD2, RSVD3),
-	PIN(UART1_RX_PU1,         UARTA,      RSVD1,  RSVD2, RSVD3),
-	PIN(UART1_RTS_PU2,        UARTA,      RSVD1,  RSVD2, RSVD3),
-	PIN(UART1_CTS_PU3,        UARTA,      RSVD1,  RSVD2, RSVD3),
-	PIN(UART2_TX_PG0,         UARTB,      I2S4A,  SPDIF, UART),
-	PIN(UART2_RX_PG1,         UARTB,      I2S4A,  SPDIF, UART),
-	PIN(UART2_RTS_PG2,        UARTB,      I2S4A,  RSVD2, UART),
-	PIN(UART2_CTS_PG3,        UARTB,      I2S4A,  RSVD2, UART),
-	PIN(UART3_TX_PD1,         UARTC,      SPI4,   RSVD2, RSVD3),
-	PIN(UART3_RX_PD2,         UARTC,      SPI4,   RSVD2, RSVD3),
-	PIN(UART3_RTS_PD3,        UARTC,      SPI4,   RSVD2, RSVD3),
-	PIN(UART3_CTS_PD4,        UARTC,      SPI4,   RSVD2, RSVD3),
-	PIN(UART4_TX_PI4,         UARTD,      UART,   RSVD2, RSVD3),
-	PIN(UART4_RX_PI5,         UARTD,      UART,   RSVD2, RSVD3),
-	PIN(UART4_RTS_PI6,        UARTD,      UART,   RSVD2, RSVD3),
-	PIN(UART4_CTS_PI7,        UARTD,      UART,   RSVD2, RSVD3),
-	PIN(DAP1_FS_PB0,          I2S1,       RSVD1,  RSVD2, RSVD3),
-	PIN(DAP1_DIN_PB1,         I2S1,       RSVD1,  RSVD2, RSVD3),
-	PIN(DAP1_DOUT_PB2,        I2S1,       RSVD1,  RSVD2, RSVD3),
-	PIN(DAP1_SCLK_PB3,        I2S1,       RSVD1,  RSVD2, RSVD3),
-	PIN(DAP2_FS_PAA0,         I2S2,       RSVD1,  RSVD2, RSVD3),
-	PIN(DAP2_DIN_PAA2,        I2S2,       RSVD1,  RSVD2, RSVD3),
-	PIN(DAP2_DOUT_PAA3,       I2S2,       RSVD1,  RSVD2, RSVD3),
-	PIN(DAP2_SCLK_PAA1,       I2S2,       RSVD1,  RSVD2, RSVD3),
-	PIN(DAP4_FS_PJ4,          I2S4B,      RSVD1,  RSVD2, RSVD3),
-	PIN(DAP4_DIN_PJ5,         I2S4B,      RSVD1,  RSVD2, RSVD3),
-	PIN(DAP4_DOUT_PJ6,        I2S4B,      RSVD1,  RSVD2, RSVD3),
-	PIN(DAP4_SCLK_PJ7,        I2S4B,      RSVD1,  RSVD2, RSVD3),
-	PIN(CAM1_MCLK_PS0,        EXTPERIPH3, RSVD1,  RSVD2, RSVD3),
-	PIN(CAM2_MCLK_PS1,        EXTPERIPH3, RSVD1,  RSVD2, RSVD3),
-	PIN(JTAG_RTCK,            JTAG,       RSVD1,  RSVD2, RSVD3),
-	PIN(CLK_32K_IN,           CLK,        RSVD1,  RSVD2, RSVD3),
-	PIN(CLK_32K_OUT_PY5,      SOC,        BLINK,  RSVD2, RSVD3),
-	PIN(BATT_BCL,             BCL,        RSVD1,  RSVD2, RSVD3),
-	PIN(CLK_REQ,              SYS,        RSVD1,  RSVD2, RSVD3),
-	PIN(CPU_PWR_REQ,          CPU,        RSVD1,  RSVD2, RSVD3),
-	PIN(PWR_INT_N,            PMI,        RSVD1,  RSVD2, RSVD3),
-	PIN(SHUTDOWN,             SHUTDOWN,   RSVD1,  RSVD2, RSVD3),
-	PIN(CORE_PWR_REQ,         CORE,       RSVD1,  RSVD2, RSVD3),
-	PIN(AUD_MCLK_PBB0,        AUD,        RSVD1,  RSVD2, RSVD3),
-	PIN(DVFS_PWM_PBB1,        RSVD0,      CLDVFS, SPI3,  RSVD3),
-	PIN(DVFS_CLK_PBB2,        RSVD0,      CLDVFS, SPI3,  RSVD3),
-	PIN(GPIO_X1_AUD_PBB3,     RSVD0,      RSVD1,  SPI3,  RSVD3),
-	PIN(GPIO_X3_AUD_PBB4,     RSVD0,      RSVD1,  SPI3,  RSVD3),
-	PIN(PCC7,                 RSVD0,      RSVD1,  RSVD2, RSVD3),
-	PIN(HDMI_CEC_PCC0,        CEC,        RSVD1,  RSVD2, RSVD3),
-	PIN(HDMI_INT_DP_HPD_PCC1, DP,         RSVD1,  RSVD2, RSVD3),
-	PIN(SPDIF_OUT_PCC2,       SPDIF,      RSVD1,  RSVD2, RSVD3),
-	PIN(SPDIF_IN_PCC3,        SPDIF,      RSVD1,  RSVD2, RSVD3),
-	PIN(USB_VBUS_EN0_PCC4,    USB,        RSVD1,  RSVD2, RSVD3),
-	PIN(USB_VBUS_EN1_PCC5,    USB,        RSVD1,  RSVD2, RSVD3),
-	PIN(DP_HPD0_PCC6,         DP,         RSVD1,  RSVD2, RSVD3),
-	PIN(WIFI_EN_PH0,          RSVD0,      RSVD1,  RSVD2, RSVD3),
-	PIN(WIFI_RST_PH1,         RSVD0,      RSVD1,  RSVD2, RSVD3),
-	PIN(WIFI_WAKE_AP_PH2,     RSVD0,      RSVD1,  RSVD2, RSVD3),
-	PIN(AP_WAKE_BT_PH3,       RSVD0,      UARTB,  SPDIF, RSVD3),
-	PIN(BT_RST_PH4,           RSVD0,      UARTB,  SPDIF, RSVD3),
-	PIN(BT_WAKE_AP_PH5,       RSVD0,      RSVD1,  RSVD2, RSVD3),
-	PIN(AP_WAKE_NFC_PH7,      RSVD0,      RSVD1,  RSVD2, RSVD3),
-	PIN(NFC_EN_PI0,           RSVD0,      RSVD1,  RSVD2, RSVD3),
-	PIN(NFC_INT_PI1,          RSVD0,      RSVD1,  RSVD2, RSVD3),
-	PIN(GPS_EN_PI2,           RSVD0,      RSVD1,  RSVD2, RSVD3),
-	PIN(GPS_RST_PI3,          RSVD0,      RSVD1,  RSVD2, RSVD3),
-	PIN(CAM_RST_PS4,          VGP1,       RSVD1,  RSVD2, RSVD3),
-	PIN(CAM_AF_EN_PS5,        VIMCLK,     VGP2,   RSVD2, RSVD3),
-	PIN(CAM_FLASH_EN_PS6,     VIMCLK,     VGP3,   RSVD2, RSVD3),
-	PIN(CAM1_PWDN_PS7,        VGP4,       RSVD1,  RSVD2, RSVD3),
-	PIN(CAM2_PWDN_PT0,        VGP5,       RSVD1,  RSVD2, RSVD3),
-	PIN(CAM1_STROBE_PT1,      VGP6,       RSVD1,  RSVD2, RSVD3),
-	PIN(LCD_TE_PY2,           DISPLAYA,   RSVD1,  RSVD2, RSVD3),
-	PIN(LCD_BL_PWM_PV0,       DISPLAYA,   PWM0,   SOR0,  RSVD3),
-	PIN(LCD_BL_EN_PV1,        RSVD0,      RSVD1,  RSVD2, RSVD3),
-	PIN(LCD_RST_PV2,          RSVD0,      RSVD1,  RSVD2, RSVD3),
-	PIN(LCD_GPIO1_PV3,        DISPLAYB,   RSVD1,  RSVD2, RSVD3),
-	PIN(LCD_GPIO2_PV4,        DISPLAYB,   PWM1,   RSVD2, SOR1),
-	PIN(AP_READY_PV5,         RSVD0,      RSVD1,  RSVD2, RSVD3),
-	PIN(TOUCH_RST_PV6,        RSVD0,      RSVD1,  RSVD2, RSVD3),
-	PIN(TOUCH_CLK_PV7,        TOUCH,      RSVD1,  RSVD2, RSVD3),
-	PIN(MODEM_WAKE_AP_PX0,    RSVD0,      RSVD1,  RSVD2, RSVD3),
-	PIN(TOUCH_INT_PX1,        RSVD0,      RSVD1,  RSVD2, RSVD3),
-	PIN(MOTION_INT_PX2,       RSVD0,      RSVD1,  RSVD2, RSVD3),
-	PIN(ALS_PROX_INT_PX3,     RSVD0,      RSVD1,  RSVD2, RSVD3),
-	PIN(TEMP_ALERT_PX4,       RSVD0,      RSVD1,  RSVD2, RSVD3),
-	PIN(BUTTON_POWER_ON_PX5,  RSVD0,      RSVD1,  RSVD2, RSVD3),
-	PIN(BUTTON_VOL_UP_PX6,    RSVD0,      RSVD1,  RSVD2, RSVD3),
-	PIN(BUTTON_VOL_DOWN_PX7,  RSVD0,      RSVD1,  RSVD2, RSVD3),
-	PIN(BUTTON_SLIDE_SW_PY0,  RSVD0,      RSVD1,  RSVD2, RSVD3),
-	PIN(BUTTON_HOME_PY1,      RSVD0,      RSVD1,  RSVD2, RSVD3),
-	PIN(PA6,                  SATA,       RSVD1,  RSVD2, RSVD3),
-	PIN(PE6,                  RSVD0,      I2S5A,  PWM2,  RSVD3),
-	PIN(PE7,                  RSVD0,      I2S5A,  PWM3,  RSVD3),
-	PIN(PH6,                  RSVD0,      RSVD1,  RSVD2, RSVD3),
-	PIN(PK0,                  IQC0,       I2S5B,  RSVD2, RSVD3),
-	PIN(PK1,                  IQC0,       I2S5B,  RSVD2, RSVD3),
-	PIN(PK2,                  IQC0,       I2S5B,  RSVD2, RSVD3),
-	PIN(PK3,                  IQC0,       I2S5B,  RSVD2, RSVD3),
-	PIN(PK4,                  IQC1,       RSVD1,  RSVD2, RSVD3),
-	PIN(PK5,                  IQC1,       RSVD1,  RSVD2, RSVD3),
-	PIN(PK6,                  IQC1,       RSVD1,  RSVD2, RSVD3),
-	PIN(PK7,                  IQC1,       RSVD1,  RSVD2, RSVD3),
-	PIN(PL0,                  RSVD0,      RSVD1,  RSVD2, RSVD3),
-	PIN(PL1,                  SOC,        RSVD1,  RSVD2, RSVD3),
-	PIN(PZ0,                  VIMCLK2,    RSVD1,  RSVD2, RSVD3),
-	PIN(PZ1,                  VIMCLK2,    SDMMC1, RSVD2, RSVD3),
-	PIN(PZ2,                  SDMMC3,     CCLA,   RSVD2, RSVD3),
-	PIN(PZ3,                  SDMMC3,     RSVD1,  RSVD2, RSVD3),
-	PIN(PZ4,                  SDMMC1,     RSVD1,  RSVD2, RSVD3),
-	PIN(PZ5,                  SOC,        RSVD1,  RSVD2, RSVD3),
-};
-const struct pmux_pingrp_desc *tegra_soc_pingroups = tegra210_pingroups;
diff --git a/arch/arm/mach-tegra/tegra210/xusb-padctl.c b/arch/arm/mach-tegra/tegra210/xusb-padctl.c
index ab6684f027..64dc297ae2 100644
--- a/arch/arm/mach-tegra/tegra210/xusb-padctl.c
+++ b/arch/arm/mach-tegra/tegra210/xusb-padctl.c
@@ -170,6 +170,17 @@ static int phy_unprepare(struct tegra_xusb_phy *phy)
 	return tegra_xusb_padctl_disable(phy->padctl);
 }
 
+#define XUSB_PADCTL_USB3_PAD_MUX 0x28
+#define  XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE (1 << 0)
+#define  XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK0 (1 << 1)
+#define  XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK1 (1 << 2)
+#define  XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK2 (1 << 3)
+#define  XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK3 (1 << 4)
+#define  XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK4 (1 << 5)
+#define  XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK5 (1 << 6)
+#define  XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK6 (1 << 7)
+#define  XUSB_PADCTL_USB3_PAD_MUX_FORCE_SATA_PAD_IDDQ_DISABLE_MASK0 (1 << 8)
+
 #define XUSB_PADCTL_UPHY_PLL_P0_CTL1 0x360
 #define  XUSB_PADCTL_UPHY_PLL_P0_CTL1_FREQ_NDIV_MASK (0xff << 20)
 #define  XUSB_PADCTL_UPHY_PLL_P0_CTL1_FREQ_NDIV(x) (((x) & 0xff) << 20)
@@ -366,31 +377,6 @@ static int pcie_phy_enable(struct tegra_xusb_phy *phy)
 	value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_CLK_EN;
 	padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
 
-	value = readl(NV_PA_CLK_RST_BASE + CLK_RST_XUSBIO_PLL_CFG0);
-	value &= ~CLK_RST_XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL;
-	value &= ~CLK_RST_XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL;
-	value |= CLK_RST_XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET;
-	value |= CLK_RST_XUSBIO_PLL_CFG0_PADPLL_SLEEP_IDDQ;
-	writel(value, NV_PA_CLK_RST_BASE + CLK_RST_XUSBIO_PLL_CFG0);
-
-	value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
-	value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL1_PWR_OVRD;
-	padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
-
-	value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
-	value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_OVRD;
-	padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
-
-	value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
-	value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_OVRD;
-	padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
-
-	udelay(1);
-
-	value = readl(NV_PA_CLK_RST_BASE + CLK_RST_XUSBIO_PLL_CFG0);
-	value |= CLK_RST_XUSBIO_PLL_CFG0_SEQ_ENABLE;
-	writel(value, NV_PA_CLK_RST_BASE + CLK_RST_XUSBIO_PLL_CFG0);
-
 	debug("< %s()\n", __func__);
 	return 0;
 }
@@ -454,3 +440,35 @@ void tegra_xusb_padctl_init(void)
 	ret = tegra_xusb_process_nodes(nodes, count, &tegra210_socdata);
 	debug("%s: done, ret=%d\n", __func__, ret);
 }
+
+void tegra_xusb_padctl_exit(void)
+{
+	u32 value;
+
+	debug("> %s\n", __func__);
+
+	value = padctl_readl(&padctl, XUSB_PADCTL_USB3_PAD_MUX);
+	value &= ~XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE;
+	value &= ~XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK0;
+	value &= ~XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK1;
+	value &= ~XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK2;
+	value &= ~XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK3;
+	value &= ~XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK4;
+	value &= ~XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK5;
+	value &= ~XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK6;
+	value &= ~XUSB_PADCTL_USB3_PAD_MUX_FORCE_SATA_PAD_IDDQ_DISABLE_MASK0;
+	padctl_writel(&padctl, value, XUSB_PADCTL_USB3_PAD_MUX);
+
+	value = padctl_readl(&padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
+	value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL1_IDDQ;
+	value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL1_SLEEP_MASK;
+	value |= XUSB_PADCTL_UPHY_PLL_P0_CTL1_SLEEP(3);
+	value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL1_ENABLE;
+	padctl_writel(&padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
+
+	reset_set_enable(PERIPH_ID_PEX_USB_UPHY, 1);
+	while (padctl.enable)
+		tegra_xusb_padctl_disable(&padctl);
+
+	debug("< %s()\n", __func__);
+}
diff --git a/arch/arm/mach-tegra/xusb-padctl-dummy.c b/arch/arm/mach-tegra/xusb-padctl-dummy.c
index 3ec27a2e3a..f2d90302f6 100644
--- a/arch/arm/mach-tegra/xusb-padctl-dummy.c
+++ b/arch/arm/mach-tegra/xusb-padctl-dummy.c
@@ -36,3 +36,7 @@ int __weak tegra_xusb_phy_unprepare(struct tegra_xusb_phy *phy)
 void __weak tegra_xusb_padctl_init(void)
 {
 }
+
+void __weak tegra_xusb_padctl_exit(void)
+{
+}