diff options
| author | yanhong.wang <yanhong.wang@starfivetech.com> | 2022-06-09 05:32:22 +0300 |
|---|---|---|
| committer | Yanhong Wang <yanhong.wang@linux.starfivetech.com> | 2022-10-18 11:24:37 +0300 |
| commit | 61f294b11cd12981b93a3a2deb8036f705332ae2 (patch) | |
| tree | ff95b6e1c2165b870613ffe1d97349ddef8f7926 /arch | |
| parent | abd35ca6d33fb5df1f413b5466b315a92fa36f4f (diff) | |
| download | u-boot-61f294b11cd12981b93a3a2deb8036f705332ae2.tar.xz | |
board:starfive:evb: update uart3-uart5 resets
Add SPL_DM_RESET to defconfig, and update uart3-uart5 reset for StarFive
JH7110 SoC.
Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/riscv/dts/jh7110.dtsi | 18 |
1 files changed, 12 insertions, 6 deletions
diff --git a/arch/riscv/dts/jh7110.dtsi b/arch/riscv/dts/jh7110.dtsi index 81a36f61a4..415d8995e0 100644 --- a/arch/riscv/dts/jh7110.dtsi +++ b/arch/riscv/dts/jh7110.dtsi @@ -407,7 +407,8 @@ clocks = <&clkgen JH7110_UART0_CLK_CORE>, <&clkgen JH7110_UART0_CLK_APB>; clock-names = "baudclk", "apb_pclk"; - resets = <&rstgen RSTN_U0_DW_UART_APB>; + resets = <&rstgen RSTN_U0_DW_UART_APB>, + <&rstgen RSTN_U0_DW_UART_CORE>; interrupts = <32>; status = "disabled"; }; @@ -420,7 +421,8 @@ clocks = <&clkgen JH7110_UART1_CLK_CORE>, <&clkgen JH7110_UART1_CLK_APB>; clock-names = "baudclk", "apb_pclk"; - resets = <&rstgen RSTN_U1_DW_UART_APB>; + resets = <&rstgen RSTN_U1_DW_UART_APB>, + <&rstgen RSTN_U1_DW_UART_CORE>; interrupts = <33>; status = "disabled"; }; @@ -433,7 +435,8 @@ clocks = <&clkgen JH7110_UART2_CLK_CORE>, <&clkgen JH7110_UART2_CLK_APB>; clock-names = "baudclk", "apb_pclk"; - resets = <&rstgen RSTN_U2_DW_UART_APB>; + resets = <&rstgen RSTN_U2_DW_UART_APB>, + <&rstgen RSTN_U2_DW_UART_CORE>; interrupts = <34>; status = "disabled"; }; @@ -446,7 +449,8 @@ clocks = <&clkgen JH7110_UART3_CLK_CORE>, <&clkgen JH7110_UART3_CLK_APB>; clock-names = "baudclk", "apb_pclk"; - resets = <&rstgen RSTN_U3_DW_UART_APB>; + resets = <&rstgen RSTN_U3_DW_UART_APB>, + <&rstgen RSTN_U3_DW_UART_CORE>; interrupts = <45>; status = "disabled"; }; @@ -459,7 +463,8 @@ clocks = <&clkgen JH7110_UART4_CLK_CORE>, <&clkgen JH7110_UART4_CLK_APB>; clock-names = "baudclk", "apb_pclk"; - resets = <&rstgen RSTN_U4_DW_UART_APB>; + resets = <&rstgen RSTN_U4_DW_UART_APB>, + <&rstgen RSTN_U4_DW_UART_CORE>; interrupts = <46>; status = "disabled"; }; @@ -472,7 +477,8 @@ clocks = <&clkgen JH7110_UART5_CLK_CORE>, <&clkgen JH7110_UART5_CLK_APB>; clock-names = "baudclk", "apb_pclk"; - resets = <&rstgen RSTN_U5_DW_UART_APB>; + resets = <&rstgen RSTN_U5_DW_UART_APB>, + <&rstgen RSTN_U5_DW_UART_CORE>; interrupts = <47>; status = "disabled"; }; |