diff options
| author | Ye Li <ye.li@nxp.com> | 2021-08-07 11:00:50 +0300 |
|---|---|---|
| committer | Stefano Babic <sbabic@denx.de> | 2021-08-09 15:46:51 +0300 |
| commit | aadd6ca158c9dbc21521d6ae870ff716f4b66b87 (patch) | |
| tree | 4b05a9d0f115a117c5889df99c6acde9540e59b9 /arch | |
| parent | 3a01f723ab028a09b2c750de43b0ccb024ff0b4f (diff) | |
| download | u-boot-aadd6ca158c9dbc21521d6ae870ff716f4b66b87.tar.xz | |
arm: imx8ulp: Update the reset vector in u-boot
Because we have set reset vector to ATF in SPL, have to set it back
to ROM for any reset in u-boot
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/mach-imx/imx8ulp/soc.c | 35 |
1 files changed, 22 insertions, 13 deletions
diff --git a/arch/arm/mach-imx/imx8ulp/soc.c b/arch/arm/mach-imx/imx8ulp/soc.c index 051dec1a5a..5e7bf57a62 100644 --- a/arch/arm/mach-imx/imx8ulp/soc.c +++ b/arch/arm/mach-imx/imx8ulp/soc.c @@ -321,21 +321,10 @@ void get_board_serial(struct tag_serialnr *serialnr) } #endif -int arch_cpu_init(void) +static void set_core0_reset_vector(u32 entry) { - if (IS_ENABLED(CONFIG_SPL_BUILD)) - clock_init(); - - return 0; -} - -#if defined(CONFIG_SPL_BUILD) -__weak void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image) -{ - debug("image entry point: 0x%lx\n", spl_image->entry_point); - /* Update SIM1 DGO8 for reset vector base */ - writel((u32)spl_image->entry_point, SIM1_BASE_ADDR + 0x5c); + writel(entry, SIM1_BASE_ADDR + 0x5c); /* set update bit */ setbits_le32(SIM1_BASE_ADDR + 0x8, 0x1 << 24); @@ -349,6 +338,26 @@ __weak void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image) /* clear the ack by set 1 */ setbits_le32(SIM1_BASE_ADDR + 0x8, (0x1 << 26)); +} + +int arch_cpu_init(void) +{ + if (IS_ENABLED(CONFIG_SPL_BUILD)) { + clock_init(); + } else { + /* reconfigure core0 reset vector to ROM */ + set_core0_reset_vector(0x1000); + } + + return 0; +} + +#if defined(CONFIG_SPL_BUILD) +__weak void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image) +{ + debug("image entry point: 0x%lx\n", spl_image->entry_point); + + set_core0_reset_vector((u32)spl_image->entry_point); /* Enable the 512KB cache */ setbits_le32(SIM1_BASE_ADDR + 0x30, (0x1 << 4)); |