diff options
author | Tom Rini <trini@konsulko.com> | 2020-08-04 18:11:02 +0300 |
---|---|---|
committer | Tom Rini <trini@konsulko.com> | 2020-08-04 18:11:02 +0300 |
commit | f1c0b7cd4be2081ae3711cec2c4cc2910a5817e1 (patch) | |
tree | 694f503767f8511bffc8c5e6360f542e50428a0d /arch | |
parent | 993b59f0451cb102f23714478a64361b44694fc6 (diff) | |
parent | 3e980a2d8bd13d0d1c2d5cec9e57a47b6cff8b92 (diff) | |
download | u-boot-f1c0b7cd4be2081ae3711cec2c4cc2910a5817e1.tar.xz |
Merge tag 'u-boot-imx-20200804' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx
For 2020.10
-----------
- fixes for Toradex board
- fix warnings from previous PR
- HAB: reset instead of panic after failure
- new board: MYiR Tech MYS-6ULX
- mx6cuboxi: use OF_PLATDATA
- further changes for DM
Travis: https://travis-ci.org/github/sbabic/u-boot-imx/builds/714513163
Diffstat (limited to 'arch')
-rw-r--r-- | arch/arm/Kconfig | 1 | ||||
-rw-r--r-- | arch/arm/dts/Makefile | 1 | ||||
-rw-r--r-- | arch/arm/dts/imx6ull-colibri-u-boot.dtsi | 45 | ||||
-rw-r--r-- | arch/arm/dts/imx6ull-colibri.dtsi | 43 | ||||
-rw-r--r-- | arch/arm/dts/imx6ull-myir-mys-6ulx-eval.dts | 19 | ||||
-rw-r--r-- | arch/arm/dts/imx6ull-myir-mys-6ulx.dtsi | 238 | ||||
-rw-r--r-- | arch/arm/dts/imx6ull-mys-6ulx-u-boot.dtsi | 24 | ||||
-rw-r--r-- | arch/arm/dts/imx7-colibri-emmc.dts | 2 | ||||
-rw-r--r-- | arch/arm/dts/imx7-colibri-rawnand.dts | 10 | ||||
-rw-r--r-- | arch/arm/dts/imx7-colibri-u-boot.dtsi | 39 | ||||
-rw-r--r-- | arch/arm/dts/imx7-colibri.dtsi | 65 | ||||
-rw-r--r-- | arch/arm/dts/imx8mm-verdin.dts | 22 | ||||
-rw-r--r-- | arch/arm/mach-imx/imx8m/soc.c | 2 | ||||
-rw-r--r-- | arch/arm/mach-imx/mx6/Kconfig | 12 | ||||
-rw-r--r-- | arch/arm/mach-imx/mx7/soc.c | 2 | ||||
-rw-r--r-- | arch/arm/mach-imx/spl.c | 6 |
16 files changed, 436 insertions, 95 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index d3ac8e1f47..6b8a32c38d 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1940,6 +1940,7 @@ source "board/hisilicon/hikey/Kconfig" source "board/hisilicon/hikey960/Kconfig" source "board/hisilicon/poplar/Kconfig" source "board/isee/igep003x/Kconfig" +source "board/myir/mys_6ulx/Kconfig" source "board/spear/spear300/Kconfig" source "board/spear/spear310/Kconfig" source "board/spear/spear320/Kconfig" diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index abf9a027cc..43a2ee1213 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -721,6 +721,7 @@ dtb-$(CONFIG_MX6UL) += \ dtb-$(CONFIG_MX6ULL) += \ imx6ull-14x14-evk.dtb \ imx6ull-colibri.dtb \ + imx6ull-myir-mys-6ulx-eval.dtb \ imx6ull-phytec-segin-ff-rdk-emmc.dtb \ imx6ull-dart-6ul.dtb \ imx6ull-somlabs-visionsom.dtb \ diff --git a/arch/arm/dts/imx6ull-colibri-u-boot.dtsi b/arch/arm/dts/imx6ull-colibri-u-boot.dtsi index 531cdcc4da..afdb0f43cf 100644 --- a/arch/arm/dts/imx6ull-colibri-u-boot.dtsi +++ b/arch/arm/dts/imx6ull-colibri-u-boot.dtsi @@ -3,6 +3,15 @@ * Copyright 2019 Toradex AG */ +/ { + aliases { + u-boot,dm-pre-reloc; + mmc0 = &usdhc1; + usb0 = &usbotg1; /* required for ums */ + display0 = &lcdif; + }; +}; + &pinctrl_uart1 { u-boot,dm-pre-reloc; }; @@ -10,3 +19,39 @@ &pinctrl_uart1_ctrl1 { u-boot,dm-pre-reloc; }; + +&lcdif { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcdif_dat + &pinctrl_lcdif_ctrl>; + status = "okay"; + display = <&display0>; + u-boot,dm-pre-reloc; + + display0: display0 { + bits-per-pixel = <18>; + bus-width = <24>; + status = "okay"; + + display-timings { + native-mode = <&timing_vga>; + timing_vga: 640x480 { + u-boot,dm-pre-reloc; + clock-frequency = <25175000>; + hactive = <640>; + vactive = <480>; + hback-porch = <40>; + hfront-porch = <24>; + vback-porch = <32>; + vfront-porch = <11>; + hsync-len = <96>; + vsync-len = <2>; + + de-active = <1>; + hsync-active = <0>; + vsync-active = <0>; + pixelclk-active = <0>; + }; + }; + }; +}; diff --git a/arch/arm/dts/imx6ull-colibri.dtsi b/arch/arm/dts/imx6ull-colibri.dtsi index fca53119fe..b7bf79f28c 100644 --- a/arch/arm/dts/imx6ull-colibri.dtsi +++ b/arch/arm/dts/imx6ull-colibri.dtsi @@ -8,13 +8,6 @@ #include "imx6ull.dtsi" / { - aliases { - u-boot,dm-pre-reloc; - mmc0 = &usdhc1; - usb0 = &usbotg1; /* required for ums */ - display0 = &lcdif; - }; - chosen { stdout-path = &uart1; }; @@ -151,42 +144,6 @@ }; }; -&lcdif { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lcdif_dat - &pinctrl_lcdif_ctrl>; - status = "okay"; - display = <&display0>; - u-boot,dm-pre-reloc; - - display0: display0 { - bits-per-pixel = <18>; - bus-width = <24>; - status = "okay"; - - display-timings { - native-mode = <&timing_vga>; - timing_vga: 640x480 { - u-boot,dm-pre-reloc; - clock-frequency = <25175000>; - hactive = <640>; - vactive = <480>; - hback-porch = <48>; - hfront-porch = <16>; - vback-porch = <33>; - vfront-porch = <10>; - hsync-len = <96>; - vsync-len = <2>; - - de-active = <1>; - hsync-active = <0>; - vsync-active = <0>; - pixelclk-active = <0>; - }; - }; - }; -}; - /* PWM <A> */ &pwm4 { pinctrl-names = "default"; diff --git a/arch/arm/dts/imx6ull-myir-mys-6ulx-eval.dts b/arch/arm/dts/imx6ull-myir-mys-6ulx-eval.dts new file mode 100644 index 0000000000..2fd69da028 --- /dev/null +++ b/arch/arm/dts/imx6ull-myir-mys-6ulx-eval.dts @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2020 Linumiz + * Author: Parthiban Nallathambi <parthiban@linumiz.com> + */ + +/dts-v1/; +#include "imx6ull.dtsi" +#include "imx6ull-myir-mys-6ulx.dtsi" +#include "imx6ull-mys-6ulx-u-boot.dtsi" + +/ { + model = "MYiR i.MX6ULL MYS-6ULX Single Board Computer with NAND"; + compatible = "myir,imx6ull-mys-6ulx-eval", "fsl,imx6ull"; +}; + +&gpmi { + status = "okay"; +}; diff --git a/arch/arm/dts/imx6ull-myir-mys-6ulx.dtsi b/arch/arm/dts/imx6ull-myir-mys-6ulx.dtsi new file mode 100644 index 0000000000..d03694feaf --- /dev/null +++ b/arch/arm/dts/imx6ull-myir-mys-6ulx.dtsi @@ -0,0 +1,238 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2020 Linumiz + * Author: Parthiban Nallathambi <parthiban@linumiz.com> + */ + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/pwm/pwm.h> + +/ { + model = "MYiR MYS-6ULX Single Board Computer"; + compatible = "fsl,imx6ull"; + + chosen { + stdout-path = &uart1; + }; + + reg_vdd_5v: regulator-vdd-5v { + compatible = "regulator-fixed"; + regulator-name = "VDD_5V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; + + reg_vdd_3v3: regulator-vdd-3v3 { + compatible = "regulator-fixed"; + regulator-name = "VDD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + vin-supply = <®_vdd_5v>; + }; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet1>; + phy-mode = "rmii"; + phy-handle = <ðphy0>; + phy-supply = <®_vdd_3v3>; + status = "okay"; + + mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + reg = <0>; + interrupt-parent = <&gpio5>; + interrupts = <5 IRQ_TYPE_LEVEL_LOW>; + clocks = <&clks IMX6UL_CLK_ENET_REF>; + clock-names = "rmii-ref"; + }; + }; +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand>; + nand-on-flash-bbt; + status = "disabled"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&usbotg1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_otg1_id>; + dr_mode = "otg"; + status = "okay"; +}; + +&usbotg2 { + dr_mode = "host"; + disable-over-current; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; + no-1-8-v; + keep-power-in-suspend; + wakeup-source; + vmmc-supply = <®_vdd_3v3>; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>; + bus-width = <8>; + non-removable; + keep-power-in-suspend; + vmmc-supply = <®_vdd_3v3>; +}; + +&iomuxc { + pinctrl_enet1: enet1grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0 + MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0 + MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 + MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031 + MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x1b0b0 + >; + }; + + pinctrl_gpmi_nand: gpminandgrp { + fsl,pins = < + MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0x0b0b1 + MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0x0b0b1 + MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0x0b0b1 + MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0x0b000 + MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0x0b0b1 + MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0x0b0b1 + MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0x0b0b1 + MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0x0b0b1 + MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0x0b0b1 + MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0x0b0b1 + MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0x0b0b1 + MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0x0b0b1 + MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0x0b0b1 + MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0x0b0b1 + MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0x0b0b1 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 + MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_usb_otg1_id: usbotg1idgrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 + MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10069 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x17059 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x17059 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x17059 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x17059 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp100mhz { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100b9 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170b9 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170b9 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170b9 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170b9 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170b9 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170b9 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170b9 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170b9 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170b9 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp200mhz { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100f9 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170f9 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170f9 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170f9 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170f9 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170f9 + >; + }; +}; diff --git a/arch/arm/dts/imx6ull-mys-6ulx-u-boot.dtsi b/arch/arm/dts/imx6ull-mys-6ulx-u-boot.dtsi new file mode 100644 index 0000000000..cd15d9ba86 --- /dev/null +++ b/arch/arm/dts/imx6ull-mys-6ulx-u-boot.dtsi @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2020 Linumiz + * Author: Parthiban Nallathambi <parthiban@linumiz.com> + */ + +&pinctrl_uart1 { + u-boot,dm-pre-reloc; +}; + +&gpmi { + u-boot,dm-spl; + u-boot,dm-pre-reloc; +}; + +&usdhc1 { + u-boot,dm-spl; + u-boot,dm-pre-reloc; +}; + +&usdhc2 { + u-boot,dm-spl; + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/imx7-colibri-emmc.dts b/arch/arm/dts/imx7-colibri-emmc.dts index bc0d10c716..8545498275 100644 --- a/arch/arm/dts/imx7-colibri-emmc.dts +++ b/arch/arm/dts/imx7-colibri-emmc.dts @@ -5,13 +5,13 @@ /dts-v1/; #include "imx7-colibri.dtsi" +#include "imx7-colibri-u-boot.dtsi" / { model = "Toradex Colibri iMX7D 1GB (eMMC)"; compatible = "toradex,imx7d-colibri-emmc", "fsl,imx7d"; aliases { - u-boot,dm-pre-reloc; mmc0 = &usdhc3; mmc1 = &usdhc1; display1 = &lcdif; diff --git a/arch/arm/dts/imx7-colibri-rawnand.dts b/arch/arm/dts/imx7-colibri-rawnand.dts index 5f12a2ac2a..5211fb1f44 100644 --- a/arch/arm/dts/imx7-colibri-rawnand.dts +++ b/arch/arm/dts/imx7-colibri-rawnand.dts @@ -5,19 +5,21 @@ /dts-v1/; #include "imx7-colibri.dtsi" +#include "imx7-colibri-u-boot.dtsi" / { model = "Toradex Colibri iMX7S/D"; compatible = "toradex,imx7-colibri", "fsl,imx7"; - chosen { - stdout-path = &uart1; - }; - aliases { + display1 = &lcdif; usb0 = &usbotg1; /* required for ums */ }; + chosen { + stdout-path = &uart1; + }; + reg_5v0: regulator-5v0 { compatible = "regulator-fixed"; regulator-name = "5V"; diff --git a/arch/arm/dts/imx7-colibri-u-boot.dtsi b/arch/arm/dts/imx7-colibri-u-boot.dtsi new file mode 100644 index 0000000000..91386476d5 --- /dev/null +++ b/arch/arm/dts/imx7-colibri-u-boot.dtsi @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright 2020 Toradex + */ + +&lcdif { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcdif_dat + &pinctrl_lcdif_ctrl>; + display = <&display0>; + u-boot,dm-pre-reloc; + + display0: display0 { + bits-per-pixel = <18>; + bus-width = <18>; + status = "okay"; + + display-timings { + native-mode = <&timing_vga>; + timing_vga: 640x480 { + clock-frequency = <25175000>; + hactive = <640>; + vactive = <480>; + hback-porch = <40>; + hfront-porch = <24>; + vback-porch = <32>; + vfront-porch = <11>; + hsync-len = <96>; + vsync-len = <2>; + + de-active = <1>; + hsync-active = <0>; + vsync-active = <0>; + pixelclk-active = <0>; + }; + }; + }; +}; diff --git a/arch/arm/dts/imx7-colibri.dtsi b/arch/arm/dts/imx7-colibri.dtsi index ec95f22a0c..b352036e30 100644 --- a/arch/arm/dts/imx7-colibri.dtsi +++ b/arch/arm/dts/imx7-colibri.dtsi @@ -172,6 +172,38 @@ >; }; + pinctrl_lcdif_dat: lcdif-dat-grp { + fsl,pins = < + MX7D_PAD_LCD_DATA00__LCD_DATA0 0x79 + MX7D_PAD_LCD_DATA01__LCD_DATA1 0x79 + MX7D_PAD_LCD_DATA02__LCD_DATA2 0x79 + MX7D_PAD_LCD_DATA03__LCD_DATA3 0x79 + MX7D_PAD_LCD_DATA04__LCD_DATA4 0x79 + MX7D_PAD_LCD_DATA05__LCD_DATA5 0x79 + MX7D_PAD_LCD_DATA06__LCD_DATA6 0x79 + MX7D_PAD_LCD_DATA07__LCD_DATA7 0x79 + MX7D_PAD_LCD_DATA08__LCD_DATA8 0x79 + MX7D_PAD_LCD_DATA09__LCD_DATA9 0x79 + MX7D_PAD_LCD_DATA10__LCD_DATA10 0x79 + MX7D_PAD_LCD_DATA11__LCD_DATA11 0x79 + MX7D_PAD_LCD_DATA12__LCD_DATA12 0x79 + MX7D_PAD_LCD_DATA13__LCD_DATA13 0x79 + MX7D_PAD_LCD_DATA14__LCD_DATA14 0x79 + MX7D_PAD_LCD_DATA15__LCD_DATA15 0x79 + MX7D_PAD_LCD_DATA16__LCD_DATA16 0x79 + MX7D_PAD_LCD_DATA17__LCD_DATA17 0x79 + >; + }; + + pinctrl_lcdif_ctrl: lcdif-ctrl-grp { + fsl,pins = < + MX7D_PAD_LCD_CLK__LCD_CLK 0x79 + MX7D_PAD_LCD_ENABLE__LCD_ENABLE 0x79 + MX7D_PAD_LCD_VSYNC__LCD_VSYNC 0x79 + MX7D_PAD_LCD_HSYNC__LCD_HSYNC 0x79 + >; + }; + pinctrl_enet1: enet1grp { fsl,pins = < MX7D_PAD_ENET1_CRS__GPIO7_IO14 0x14 @@ -227,36 +259,3 @@ >; }; }; - -&lcdif { - status = "okay"; - display = <&display0>; - u-boot,dm-pre-reloc; - - display0: display0 { - bits-per-pixel = <18>; - bus-width = <24>; - status = "okay"; - - display-timings { - native-mode = <&timing_vga>; - timing_vga: 640x480 { - u-boot,dm-pre-reloc; - clock-frequency = <25175000>; - hactive = <640>; - vactive = <480>; - hback-porch = <48>; - hfront-porch = <16>; - vback-porch = <33>; - vfront-porch = <10>; - hsync-len = <96>; - vsync-len = <2>; - - de-active = <1>; - hsync-active = <0>; - vsync-active = <0>; - pixelclk-active = <0>; - }; - }; - }; -}; diff --git a/arch/arm/dts/imx8mm-verdin.dts b/arch/arm/dts/imx8mm-verdin.dts index b86f46e03e..1c67c08c88 100644 --- a/arch/arm/dts/imx8mm-verdin.dts +++ b/arch/arm/dts/imx8mm-verdin.dts @@ -16,6 +16,12 @@ stdout-path = &uart1; }; + aliases { + eeprom0 = &eeprom_module; + eeprom1 = &eeprom_carrier_board; + eeprom2 = &eeprom_display_adapter; + }; + /* fixed clock dedicated to SPI CAN controller */ clk20m: oscillator { compatible = "fixed-clock"; @@ -321,8 +327,8 @@ vcc-supply = <&ldo5_reg>; }; - eeprom@50 { - compatible = "st,24c02"; + eeprom_module: eeprom@50 { + compatible = "st,24c02", "atmel,24c02", "i2c-eeprom"; pagesize = <16>; reg = <0x50>; }; @@ -377,16 +383,16 @@ status = "okay"; }; - /* EEPROM on MIPI-DSI to HDMI adapter */ - eeprom_50: eeprom@50 { - compatible = "st,24c02"; + /* EEPROM on display adapter (MIPI DSI Display Adapter) */ + eeprom_display_adapter: eeprom@50 { + compatible = "st,24c02", "atmel,24c02", "i2c-eeprom"; pagesize = <16>; reg = <0x50>; }; - /* EEPROM on Verdin Development board */ - eeprom_57: eeprom@57 { - compatible = "st,24c02"; + /* EEPROM on carrier board */ + eeprom_carrier_board: eeprom@57 { + compatible = "st,24c02", "atmel,24c02", "i2c-eeprom"; pagesize = <16>; reg = <0x57>; }; diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c index 8ee024ff1a..8dfc8645fc 100644 --- a/arch/arm/mach-imx/imx8m/soc.c +++ b/arch/arm/mach-imx/imx8m/soc.c @@ -933,7 +933,7 @@ static void acquire_buildinfo(void) /* Get ARM Trusted Firmware commit id */ arm_smccc_smc(IMX_SIP_BUILDINFO, IMX_SIP_BUILDINFO_GET_COMMITHASH, - 0, 0 , 0, 0, 0, 0, &res); + 0, 0, 0, 0, 0, 0, &res); atf_commit = res.a0; if (atf_commit == 0xffffffff) { debug("ATF does not support build info\n"); diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig index fdee0d4f64..17173f9839 100644 --- a/arch/arm/mach-imx/mx6/Kconfig +++ b/arch/arm/mach-imx/mx6/Kconfig @@ -460,6 +460,18 @@ config TARGET_MX6ULL_14X14_EVK select MX6ULL imply CMD_DM +config TARGET_MYS_6ULX + bool "MYiR MYS-6ULX" + select MX6ULL + select DM + select DM_ETH + select DM_GPIO + select DM_I2C + select DM_MMC + select DM_SERIAL + select DM_THERMAL + select SUPPORT_SPL + config TARGET_NITROGEN6X bool "nitrogen6x" imply USB_ETHER_ASIX diff --git a/arch/arm/mach-imx/mx7/soc.c b/arch/arm/mach-imx/mx7/soc.c index 798fe74a3d..9cb61f5c34 100644 --- a/arch/arm/mach-imx/mx7/soc.c +++ b/arch/arm/mach-imx/mx7/soc.c @@ -218,7 +218,7 @@ const struct rproc_att hostmap[] = { { 0x00940000, 0x00940000, 0x20000 }, /* OCRAM_PXP */ { 0x20240000, 0x00940000, 0x20000 }, /* OCRAM_PXP */ { 0x10000000, 0x80000000, 0x0fff0000 }, /* DDR Code alias */ - { 0x80000000, 0x80000000, 0xe0000000 }, /* DDRC */ + { 0x80000000, 0x80000000, 0x60000000 }, /* DDRC */ { /* sentinel */ } }; #endif diff --git a/arch/arm/mach-imx/spl.c b/arch/arm/mach-imx/spl.c index 1a231c67f5..76a5f7aca6 100644 --- a/arch/arm/mach-imx/spl.c +++ b/arch/arm/mach-imx/spl.c @@ -293,8 +293,7 @@ __weak void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image) CSF_PAD_SIZE, offset)) { image_entry(); } else { - puts("spl: ERROR: image authentication fail\n"); - hang(); + panic("spl: ERROR: image authentication fail\n"); } } } @@ -320,8 +319,7 @@ void board_spl_fit_post_load(ulong load_addr, size_t length) if (imx_hab_authenticate_image(load_addr, offset + IVT_SIZE + CSF_PAD_SIZE, offset)) { - puts("spl: ERROR: image authentication unsuccessful\n"); - hang(); + panic("spl: ERROR: image authentication unsuccessful\n"); } } #endif |