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author | Sergiu Moga <sergiu.moga@microchip.com> | 2022-04-01 12:27:23 +0300 |
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committer | Eugen Hristev <eugen.hristev@microchip.com> | 2022-04-26 09:51:46 +0300 |
commit | 2016585c3a9486ea438145f47a28ee7fa8f7060c (patch) | |
tree | 8cb8e1fe3dca46a084de67ac0aca74b9708c9e56 /arch | |
parent | c8532d3f9eb8c69f41a73c734d1874d9a0d2b8df (diff) | |
download | u-boot-2016585c3a9486ea438145f47a28ee7fa8f7060c.tar.xz |
ARM: dts: at91: Add RSTC node
Add node for RSTC.
Signed-off-by: Sergiu Moga <sergiu.moga@microchip.com>
Diffstat (limited to 'arch')
-rw-r--r-- | arch/arm/dts/sam9x60.dtsi | 6 | ||||
-rw-r--r-- | arch/arm/dts/sama7g5.dtsi | 7 |
2 files changed, 13 insertions, 0 deletions
diff --git a/arch/arm/dts/sam9x60.dtsi b/arch/arm/dts/sam9x60.dtsi index be44519934..733cc5cec9 100644 --- a/arch/arm/dts/sam9x60.dtsi +++ b/arch/arm/dts/sam9x60.dtsi @@ -223,6 +223,12 @@ status = "okay"; }; + reset_controller: rstc@fffffe00 { + compatible = "microchip,sam9x60-rstc"; + reg = <0xfffffe00 0x10>; + clocks = <&clk32 0>; + }; + pit: timer@fffffe40 { compatible = "atmel,at91sam9260-pit"; reg = <0xfffffe40 0x10>; diff --git a/arch/arm/dts/sama7g5.dtsi b/arch/arm/dts/sama7g5.dtsi index b7c261ebe9..7015bd7f6d 100644 --- a/arch/arm/dts/sama7g5.dtsi +++ b/arch/arm/dts/sama7g5.dtsi @@ -232,6 +232,13 @@ clocks = <&clk32k 0>; }; + reset_controller: rstc@e001d000 { + compatible = "microchip,sama7g5-rstc", "microchip,sam9x60-rstc"; + reg = <0xe001d000 0xc>, <0xe001d0e4 0x4>; + #reset-cells = <1>; + clocks = <&clk32k 0>; + }; + clk32k: clock-controller@e001d050 { compatible = "microchip,sama7g5-sckc", "microchip,sam9x60-sckc"; reg = <0xe001d050 0x4>; |