Merge tag 'xilinx-for-v2022.04-rc3' of https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze

Xilinx changes for v2022.04-rc3

microblaze:
- Fix exception handler

zynqmp:
- Show information about secure images
- DT changes (som u-boot file removal)
- Fix zynqmp_pm_cfg_obj_convert.py
- Fix platform boot

xilinx:
- Fix bootm_size calculation
- Remove GPIO_EXTRA_HEADER selection

power:
- Add zynqmp power management driver

scsi:
- Add phy support to ceva driver

zynq qspi:
- Fix unaligned accesses and check baudrate setup
- Add support for spi memory operations

net:
- Fix 64bit calculation in axi_emac

video:
- Add missing gpio dependency for seps driver

14 files changed, 48 insertions, 92 deletions

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 8053394389..391a77c2b4 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1139,7 +1139,6 @@ config ARCH_VERSAL
 	select DM_MMC if MMC
 	select DM_SERIAL
 	select GICV3
-	select GPIO_EXTRA_HEADER
 	select OF_CONTROL
 	select SOC_DEVICE
 	imply BOARD_LATE_INIT
@@ -1159,13 +1158,13 @@ config ARCH_ZYNQ
 	select CLK
 	select CLK_ZYNQ
 	select CPU_V7A
+	select DEBUG_UART_BOARD_INIT if SPL && DEBUG_UART
 	select DM
 	select DM_ETH if NET
 	select DM_MMC if MMC
 	select DM_SERIAL
 	select DM_SPI
 	select DM_SPI_FLASH
-	select GPIO_EXTRA_HEADER
 	select OF_CONTROL
 	select SPI
 	select SPL_BOARD_INIT if SPL
@@ -1192,7 +1191,6 @@ config ARCH_ZYNQMP_R5
 	select DM_ETH if NET
 	select DM_MMC if MMC
 	select DM_SERIAL
-	select GPIO_EXTRA_HEADER
 	select OF_CONTROL
 	imply CMD_DM
 	imply DM_USB_GADGET
@@ -1202,6 +1200,7 @@ config ARCH_ZYNQMP
 	select ARM64
 	select CLK
 	select DM
+	select DEBUG_UART_BOARD_INIT if SPL && DEBUG_UART
 	select DM_ETH if NET
 	select DM_MAILBOX
 	select DM_MMC if MMC
@@ -1210,7 +1209,6 @@ config ARCH_ZYNQMP
 	select DM_SPI_FLASH if DM_SPI
 	imply FIRMWARE
 	select GICV2
-	select GPIO_EXTRA_HEADER
 	select OF_CONTROL
 	select SPL_BOARD_INIT if SPL
 	select SPL_CLK if SPL
diff --git a/arch/arm/dts/zynqmp-dlc21-revA.dts b/arch/arm/dts/zynqmp-dlc21-revA.dts
index cf0aadf03c..0461219ca3 100644
--- a/arch/arm/dts/zynqmp-dlc21-revA.dts
+++ b/arch/arm/dts/zynqmp-dlc21-revA.dts
@@ -12,7 +12,6 @@
 #include "zynqmp-clk-ccf.dtsi"
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/phy/phy.h>
-#include <include/dt-bindings/gpio/gpio.h>
 
 / {
 	model = "Smartlynq+ DLC21 RevA";
diff --git a/arch/arm/dts/zynqmp-sm-k26-revA-u-boot.dtsi b/arch/arm/dts/zynqmp-sm-k26-revA-u-boot.dtsi
deleted file mode 100644
index 467df9f23a..0000000000
--- a/arch/arm/dts/zynqmp-sm-k26-revA-u-boot.dtsi
+++ /dev/null
@@ -1,21 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * dts file for Xilinx ZynqMP K26/KV260 SD wiring
- *
- * (C) Copyright 2020 - 2021, Xilinx, Inc.
- *
- * Michal Simek <michal.simek@xilinx.com>
- */
-
-/* SD0 only supports 3.3V, no level shifter */
-&sdhci1 { /* on CC - MIO 39 - 51 */
-	status = "okay";
-	no-1-8-v;
-	disable-wp;
-	broken-cd;
-	xlnx,mio-bank = <1>;
-	/* Do not run SD in HS mode from bootloader */
-	sdhci-caps-mask = <0 0x200000>;
-	sdhci-caps = <0 0>;
-	max-frequency = <19000000>;
-};
diff --git a/arch/arm/dts/zynqmp-smk-k26-revA-u-boot.dtsi b/arch/arm/dts/zynqmp-smk-k26-revA-u-boot.dtsi
deleted file mode 100644
index 34e6328fb6..0000000000
--- a/arch/arm/dts/zynqmp-smk-k26-revA-u-boot.dtsi
+++ /dev/null
@@ -1,21 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * dts file for Xilinx ZynqMP Z2-VSOM
- *
- * (C) Copyright 2020 - 2021, Xilinx, Inc.
- *
- * Michal Simek <michal.simek@xilinx.com>
- */
-
-/* SD0 only supports 3.3V, no level shifter */
-&sdhci1 { /* FIXME - on CC - MIO 39 - 51 */
-	status = "okay";
-	no-1-8-v;
-	disable-wp;
-	broken-cd;
-	xlnx,mio-bank = <1>;
-	/* Do not run SD in HS mode from bootloader */
-	sdhci-caps-mask = <0 0x200000>;
-	sdhci-caps = <0 0>;
-	max-frequency = <19000000>;
-};
diff --git a/arch/arm/mach-versal/include/mach/gpio.h b/arch/arm/mach-versal/include/mach/gpio.h
deleted file mode 100644
index 677facba5e..0000000000
--- a/arch/arm/mach-versal/include/mach/gpio.h
+++ /dev/null
@@ -1,6 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2016 - 2018 Xilinx, Inc.
- */
-
-/* Empty file - for compilation */
diff --git a/arch/arm/mach-zynq/include/mach/gpio.h b/arch/arm/mach-zynq/include/mach/gpio.h
deleted file mode 100644
index 6143e24563..0000000000
--- a/arch/arm/mach-zynq/include/mach/gpio.h
+++ /dev/null
@@ -1,10 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (c) 2013 Xilinx, Inc.
- * Copyright (c) 2015 DAVE Embedded Systems
- */
-
-#ifndef _ZYNQ_GPIO_H
-#define _ZYNQ_GPIO_H
-
-#endif /* _ZYNQ_GPIO_H */
diff --git a/arch/arm/mach-zynq/spl.c b/arch/arm/mach-zynq/spl.c
index b1a5184b68..fea1c9b12a 100644
--- a/arch/arm/mach-zynq/spl.c
+++ b/arch/arm/mach-zynq/spl.c
@@ -16,17 +16,20 @@
 #include <asm/arch/sys_proto.h>
 #include <asm/arch/ps7_init_gpl.h>
 
+#if defined(CONFIG_DEBUG_UART_BOARD_INIT)
+void board_debug_uart_init(void)
+{
+	ps7_init();
+}
+#endif
+
 void board_init_f(ulong dummy)
 {
+#if !defined(CONFIG_DEBUG_UART_BOARD_INIT)
 	ps7_init();
+#endif
 
 	arch_cpu_init();
-
-#ifdef CONFIG_DEBUG_UART
-	/* Uart debug for sure */
-	debug_uart_init();
-	puts("Debug uart enabled\n"); /* or printch() */
-#endif
 }
 
 #ifdef CONFIG_SPL_BOARD_INIT
diff --git a/arch/arm/mach-zynqmp/Kconfig b/arch/arm/mach-zynqmp/Kconfig
index f8b5906039..66045067d2 100644
--- a/arch/arm/mach-zynqmp/Kconfig
+++ b/arch/arm/mach-zynqmp/Kconfig
@@ -140,6 +140,7 @@ config DEFINE_TCM_OCM_MMAP
 
 config ZYNQMP_PSU_INIT_ENABLED
 	bool "Include psu_init"
+	select BOARD_EARLY_INIT_F
 	help
 	  Include psu_init to full u-boot. SPL include psu_init by default.
 
diff --git a/arch/arm/mach-zynqmp/Makefile b/arch/arm/mach-zynqmp/Makefile
index eb6c5112b3..4f9f6b56a9 100644
--- a/arch/arm/mach-zynqmp/Makefile
+++ b/arch/arm/mach-zynqmp/Makefile
@@ -6,6 +6,6 @@
 obj-y	+= clk.o
 obj-y	+= cpu.o
 obj-$(CONFIG_MP)	+= mp.o
-obj-$(CONFIG_SPL_BUILD) += spl.o handoff.o
+obj-$(CONFIG_SPL_BUILD) += spl.o handoff.o psu_spl_init.o
 obj-$(CONFIG_SPL_ZYNQMP_DRAM_ECC_INIT) += ecc_spl_init.o
 obj-$(CONFIG_ZYNQMP_PSU_INIT_ENABLED)	+= psu_spl_init.o
diff --git a/arch/arm/mach-zynqmp/include/mach/gpio.h b/arch/arm/mach-zynqmp/include/mach/gpio.h
deleted file mode 100644
index 542a5fc3e9..0000000000
--- a/arch/arm/mach-zynqmp/include/mach/gpio.h
+++ /dev/null
@@ -1,11 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2015 Xilinx, Inc.
- */
-
-#ifndef __ARCH_ZYNQMP_GPIO_H
-#define __ARCH_ZYNQMP_GPIO_H
-
-/* Empty file - sdhci requires this. */
-
-#endif
diff --git a/arch/arm/mach-zynqmp/include/mach/hardware.h b/arch/arm/mach-zynqmp/include/mach/hardware.h
index e6a3ee4a57..a70d6d611b 100644
--- a/arch/arm/mach-zynqmp/include/mach/hardware.h
+++ b/arch/arm/mach-zynqmp/include/mach/hardware.h
@@ -152,8 +152,12 @@ struct apu_regs {
 #define CSU_JTAG_CHAIN_WR_SETUP		GENMASK(1, 0)
 #define CSU_PCAP_PROG_RELEASE_PL	BIT(0)
 
+#define ZYNQMP_CSU_STATUS_AUTHENTICATED	BIT(0)
+#define ZYNQMP_CSU_STATUS_ENCRYPTED	BIT(1)
+
 struct csu_regs {
-	u32 reserved0[4];
+	u32 status;
+	u32 reserved0[3];
 	u32 multi_boot;
 	u32 reserved1[7];
 	u32 jtag_chain_status_wr;
diff --git a/arch/arm/mach-zynqmp/include/mach/psu_init_gpl.h b/arch/arm/mach-zynqmp/include/mach/psu_init_gpl.h
index e37acda2f8..434a7fa20e 100644
--- a/arch/arm/mach-zynqmp/include/mach/psu_init_gpl.h
+++ b/arch/arm/mach-zynqmp/include/mach/psu_init_gpl.h
@@ -22,5 +22,6 @@ void prog_reg(unsigned long addr, unsigned long mask,
 
 int psu_init(void);
 unsigned long psu_post_config_data(void);
+int psu_uboot_init(void);
 
 #endif /* _PSU_INIT_GPL_H_ */
diff --git a/arch/arm/mach-zynqmp/spl.c b/arch/arm/mach-zynqmp/spl.c
index 6b836cbff2..b428fd5312 100644
--- a/arch/arm/mach-zynqmp/spl.c
+++ b/arch/arm/mach-zynqmp/spl.c
@@ -19,9 +19,19 @@
 #include <asm/arch/psu_init_gpl.h>
 #include <asm/arch/sys_proto.h>
 
+#if defined(CONFIG_DEBUG_UART_BOARD_INIT)
+void board_debug_uart_init(void)
+{
+	psu_uboot_init();
+}
+#endif
+
 void board_init_f(ulong dummy)
 {
-	board_early_init_f();
+#if !defined(CONFIG_DEBUG_UART_BOARD_INIT)
+	psu_uboot_init();
+#endif
+
 	board_early_init_r();
 #ifdef CONFIG_SPL_ZYNQMP_DRAM_ECC_INIT
 	zynqmp_ecc_init();
diff --git a/arch/microblaze/cpu/exception.c b/arch/microblaze/cpu/exception.c
index e9476abedb..d3640d3903 100644
--- a/arch/microblaze/cpu/exception.c
+++ b/arch/microblaze/cpu/exception.c
@@ -20,10 +20,25 @@ void _hw_exception_handler (void)
 	MFS(state, resr);
 	printf("Hardware exception at 0x%x address\n", address);
 	R17(address);
-	printf("Return address from exception 0x%x\n", address);
+
+	if (CONFIG_IS_ENABLED(XILINX_MICROBLAZE0_DELAY_SLOT_EXCEP) &&
+	    (state & 0x1000)) {
+		/*
+		 * For exceptions in delay slots, the return address is stored
+		 * in the Branch Target Register (BTR), rather than R17.
+		 */
+		MFS(address, rbtr);
+
+		puts("Exception in delay slot\n");
+	}
+
 	switch (state & 0x1f) {	/* mask on exception cause */
 	case 0x1:
 		puts("Unaligned data access exception\n");
+
+		printf("Unaligned %sword access\n", ((state & 0x800) ? "" : "half"));
+		printf("Unaligned %s access\n", ((state & 0x400) ? "store" : "load"));
+		printf("Register R%x\n", (state & 0x3E0) >> 5);
 		break;
 	case 0x2:
 		puts("Illegal op-code exception\n");
@@ -37,21 +52,15 @@ void _hw_exception_handler (void)
 	case 0x5:
 		puts("Divide by zero exception\n");
 		break;
-#ifdef MICROBLAZE_V5
 	case 0x7:
 		puts("Priviledged or stack protection violation exception\n");
 		break;
-	case 0x1000:
-		puts("Exception in delay slot\n");
-		break;
-#endif
 	default:
 		puts("Undefined cause\n");
 		break;
 	}
-	printf("Unaligned %sword access\n", ((state & 0x800) ? "" : "half"));
-	printf("Unaligned %s access\n", ((state & 0x400) ? "store" : "load"));
-	printf("Register R%x\n", (state & 0x3E) >> 5);
+
+	printf("Return address from exception 0x%x\n", address);
 	hang();
 }