diff options
author | Tom Rini <trini@konsulko.com> | 2023-02-01 17:30:52 +0300 |
---|---|---|
committer | Tom Rini <trini@konsulko.com> | 2023-02-01 17:30:52 +0300 |
commit | 3592a61fa8b4b55c0fab9a75bfb9ac3c73fdcbc0 (patch) | |
tree | 46d89652f8a6235ed0cdcd6473be02c98269395a /arch | |
parent | 73a3f5139182a0389d505bf29b0ad4bc29424cf8 (diff) | |
parent | f42c0726fd02e978a524ab35b060382d317ef438 (diff) | |
download | u-boot-3592a61fa8b4b55c0fab9a75bfb9ac3c73fdcbc0.tar.xz |
Merge tag 'u-boot-imx-20230201' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx
For 2023.04
-----------
- several conversion to DM_SERIAL and DM_I2C
- fixes for Toradex boards
- PSCI
CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/14965
Diffstat (limited to 'arch')
54 files changed, 1624 insertions, 98 deletions
diff --git a/arch/arm/cpu/armv8/fwcall.c b/arch/arm/cpu/armv8/fwcall.c index 16914dc1ee..87de09979b 100644 --- a/arch/arm/cpu/armv8/fwcall.c +++ b/arch/arm/cpu/armv8/fwcall.c @@ -103,7 +103,7 @@ void __noreturn psci_system_reset2(u32 reset_level, u32 cookie) { struct pt_regs regs; - regs.regs[0] = ARM_PSCI_0_2_FN64_SYSTEM_RESET2; + regs.regs[0] = ARM_PSCI_1_1_FN64_SYSTEM_RESET2; regs.regs[1] = PSCI_RESET2_TYPE_VENDOR | reset_level; regs.regs[2] = cookie; if (use_smc_for_psci) diff --git a/arch/arm/cpu/armv8/psci.S b/arch/arm/cpu/armv8/psci.S index 6aece11987..ab8b3df341 100644 --- a/arch/arm/cpu/armv8/psci.S +++ b/arch/arm/cpu/armv8/psci.S @@ -81,6 +81,7 @@ PSCI_DEFAULT(psci_node_hw_state_64) PSCI_DEFAULT(psci_system_suspend_64) PSCI_DEFAULT(psci_stat_residency_64) PSCI_DEFAULT(psci_stat_count_64) +PSCI_DEFAULT(psci_system_reset2_64) .align 3 _psci_64_table: @@ -94,6 +95,7 @@ PSCI_TABLE(ARM_PSCI_1_0_FN64_NODE_HW_STATE, psci_node_hw_state_64) PSCI_TABLE(ARM_PSCI_1_0_FN64_SYSTEM_SUSPEND, psci_system_suspend_64) PSCI_TABLE(ARM_PSCI_1_0_FN64_STAT_RESIDENCY, psci_stat_residency_64) PSCI_TABLE(ARM_PSCI_1_0_FN64_STAT_COUNT, psci_stat_count_64) +PSCI_TABLE(ARM_PSCI_1_1_FN64_SYSTEM_RESET2, psci_system_reset2_64) PSCI_TABLE(0, 0) .macro psci_enter diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 1fc4d2c2fe..d9b719f85d 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -962,6 +962,7 @@ dtb-$(CONFIG_ARCH_IMX8M) += \ imx8mm-kontron-bl.dtb \ imx8mm-kontron-bl-osm-s.dtb \ imx8mm-mx8menlo.dtb \ + imx8mm-phg.dtb \ imx8mm-venice.dtb \ imx8mm-venice-gw71xx-0x.dtb \ imx8mm-venice-gw72xx-0x.dtb \ diff --git a/arch/arm/dts/fsl-imx8qm-apalis.dts b/arch/arm/dts/fsl-imx8qm-apalis.dts index 0d8d3b3e8e..bc7c75d337 100644 --- a/arch/arm/dts/fsl-imx8qm-apalis.dts +++ b/arch/arm/dts/fsl-imx8qm-apalis.dts @@ -589,8 +589,10 @@ /* eMMC */ &usdhc1 { - pinctrl-names = "default"; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1>; + pinctrl-2 = <&pinctrl_usdhc1>; bus-width = <8>; non-removable; status = "okay"; @@ -598,8 +600,10 @@ /* Apalis MMC1 */ &usdhc2 { - pinctrl-names = "default"; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_mmc1_cd>; + pinctrl-1 = <&pinctrl_usdhc2>, <&pinctrl_mmc1_cd>; + pinctrl-2 = <&pinctrl_usdhc2>, <&pinctrl_mmc1_cd>; bus-width = <8>; cd-gpios = <&gpio2 9 GPIO_ACTIVE_LOW>; /* Apalis MMC1_CD# */ status = "okay"; diff --git a/arch/arm/dts/imx6q-sabrelite-u-boot.dtsi b/arch/arm/dts/imx6q-sabrelite-u-boot.dtsi new file mode 100644 index 0000000000..9eb1c34b20 --- /dev/null +++ b/arch/arm/dts/imx6q-sabrelite-u-boot.dtsi @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2022 Collabora + */ + +#include "imx6qdl-u-boot.dtsi" + +/ { + aliases { + mmc0 = &usdhc3; + mmc1 = &usdhc4; + }; +}; diff --git a/arch/arm/dts/imx6qdl-icore-u-boot.dtsi b/arch/arm/dts/imx6qdl-icore-u-boot.dtsi index f95d49d00d..12e46e38f6 100644 --- a/arch/arm/dts/imx6qdl-icore-u-boot.dtsi +++ b/arch/arm/dts/imx6qdl-icore-u-boot.dtsi @@ -5,6 +5,22 @@ #include "imx6qdl-u-boot.dtsi" +&soc { + u-boot,dm-pre-reloc; +}; + +&aips1 { + u-boot,dm-pre-reloc; +}; + +&pinctrl_uart4 { + u-boot,dm-pre-reloc; +}; + +&uart4 { + u-boot,dm-pre-reloc; +}; + &usdhc1 { u-boot,dm-spl; }; diff --git a/arch/arm/dts/imx6qdl-sabresd-u-boot.dtsi b/arch/arm/dts/imx6qdl-sabresd-u-boot.dtsi index 45f02b19c7..cbb856fba3 100644 --- a/arch/arm/dts/imx6qdl-sabresd-u-boot.dtsi +++ b/arch/arm/dts/imx6qdl-sabresd-u-boot.dtsi @@ -5,6 +5,12 @@ #include "imx6qdl-u-boot.dtsi" +/ { + aliases { + mmc1 = &usdhc3; + }; +}; + &usdhc3 { u-boot,dm-spl; }; diff --git a/arch/arm/dts/imx6sll-evk-u-boot.dtsi b/arch/arm/dts/imx6sll-evk-u-boot.dtsi new file mode 100644 index 0000000000..14d0b58949 --- /dev/null +++ b/arch/arm/dts/imx6sll-evk-u-boot.dtsi @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019, 2021 NXP + */ + +&pinctrl_uart1 { + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/imx6sx-sabreauto-u-boot.dtsi b/arch/arm/dts/imx6sx-sabreauto-u-boot.dtsi index 549461df71..7812aa34ee 100644 --- a/arch/arm/dts/imx6sx-sabreauto-u-boot.dtsi +++ b/arch/arm/dts/imx6sx-sabreauto-u-boot.dtsi @@ -14,3 +14,7 @@ compatible = "jedec,spi-nor"; }; }; + +&pinctrl_uart1 { + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/imx6ul-isiot-u-boot.dtsi b/arch/arm/dts/imx6ul-isiot-u-boot.dtsi index aa8e9804bf..7213e71989 100644 --- a/arch/arm/dts/imx6ul-isiot-u-boot.dtsi +++ b/arch/arm/dts/imx6ul-isiot-u-boot.dtsi @@ -5,6 +5,22 @@ #include "imx6ul-u-boot.dtsi" +&soc { + u-boot,dm-pre-reloc; +}; + +&aips1 { + u-boot,dm-pre-reloc; +}; + +&pinctrl_uart1 { + u-boot,dm-pre-reloc; +}; + +&uart1 { + u-boot,dm-pre-reloc; +}; + &usdhc1 { u-boot,dm-spl; }; diff --git a/arch/arm/dts/imx6ull-14x14-evk-u-boot.dtsi b/arch/arm/dts/imx6ull-14x14-evk-u-boot.dtsi new file mode 100644 index 0000000000..d283e815e6 --- /dev/null +++ b/arch/arm/dts/imx6ull-14x14-evk-u-boot.dtsi @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2022 NXP + */ + +&pinctrl_uart1 { + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/imx6ull-colibri-eval-v3-u-boot.dtsi b/arch/arm/dts/imx6ull-colibri-eval-v3-u-boot.dtsi index 65dfeab5bb..0a732269ba 100644 --- a/arch/arm/dts/imx6ull-colibri-eval-v3-u-boot.dtsi +++ b/arch/arm/dts/imx6ull-colibri-eval-v3-u-boot.dtsi @@ -6,7 +6,6 @@ / { aliases { u-boot,dm-pre-reloc; - mmc0 = &usdhc1; usb0 = &usbotg1; /* required for ums */ display0 = &lcdif; }; diff --git a/arch/arm/dts/imx6ulz-14x14-evk-u-boot.dtsi b/arch/arm/dts/imx6ulz-14x14-evk-u-boot.dtsi new file mode 100644 index 0000000000..d283e815e6 --- /dev/null +++ b/arch/arm/dts/imx6ulz-14x14-evk-u-boot.dtsi @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2022 NXP + */ + +&pinctrl_uart1 { + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/imx8mm-kontron-bl.dts b/arch/arm/dts/imx8mm-kontron-bl.dts index a079322a37..dcec57c203 100644 --- a/arch/arm/dts/imx8mm-kontron-bl.dts +++ b/arch/arm/dts/imx8mm-kontron-bl.dts @@ -13,6 +13,8 @@ aliases { ethernet1 = &usbnet; + rtc0 = &rx8900; + rtc1 = &snvs_rtc; }; /* fixed crystal dedicated to mcp2515 */ @@ -136,7 +138,7 @@ pinctrl-0 = <&pinctrl_i2c4>; status = "okay"; - rtc@32 { + rx8900: rtc@32 { compatible = "epson,rx8900"; reg = <0x32>; }; diff --git a/arch/arm/dts/imx8mm-kontron-osm-s.dtsi b/arch/arm/dts/imx8mm-kontron-osm-s.dtsi index 8d10f5b412..695da2fa7c 100644 --- a/arch/arm/dts/imx8mm-kontron-osm-s.dtsi +++ b/arch/arm/dts/imx8mm-kontron-osm-s.dtsi @@ -10,6 +10,11 @@ model = "Kontron OSM-S i.MX8MM (N802X SOM)"; compatible = "kontron,imx8mm-osm-s", "fsl,imx8mm"; + aliases { + rtc0 = &rv3028; + rtc1 = &snvs_rtc; + }; + memory@40000000 { device_type = "memory"; /* @@ -200,7 +205,7 @@ }; }; - rtc@52 { + rv3028: rtc@52 { compatible = "microcrystal,rv3028"; reg = <0x52>; pinctrl-names = "default"; diff --git a/arch/arm/dts/imx8mm-phg-u-boot.dtsi b/arch/arm/dts/imx8mm-phg-u-boot.dtsi new file mode 100644 index 0000000000..3bf45ef4a6 --- /dev/null +++ b/arch/arm/dts/imx8mm-phg-u-boot.dtsi @@ -0,0 +1,137 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +#include "imx8mm-u-boot.dtsi" + +/ { + wdt-reboot { + compatible = "wdt-reboot"; + wdt = <&wdog1>; + u-boot,dm-spl; + }; + + firmware { + optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + }; +}; + +&aips4 { + u-boot,dm-spl; +}; + +®_usdhc2_vmmc { + u-boot,off-on-delay-us = <20000>; +}; + +&pinctrl_reg_usdhc2_vmmc { + u-boot,dm-spl; +}; + +&pinctrl_uart2 { + u-boot,dm-spl; +}; + +&pinctrl_usdhc2_gpio { + u-boot,dm-spl; +}; + +&pinctrl_usdhc2 { + u-boot,dm-spl; +}; + +&pinctrl_usdhc3 { + u-boot,dm-spl; +}; + +&gpio1 { + u-boot,dm-spl; +}; + +&gpio2 { + u-boot,dm-spl; +}; + +&gpio3 { + u-boot,dm-spl; +}; + +&gpio4 { + u-boot,dm-spl; +}; + +&gpio5 { + u-boot,dm-spl; +}; + +&uart2 { + u-boot,dm-spl; +}; + +&usbmisc1 { + u-boot,dm-spl; +}; + +&usbphynop1 { + u-boot,dm-spl; +}; + +&usbotg1 { + u-boot,dm-spl; +}; + +&usdhc1 { + u-boot,dm-spl; +}; + +&usdhc2 { + u-boot,dm-spl; + sd-uhs-sdr104; + sd-uhs-ddr50; + assigned-clocks = <&clk IMX8MM_CLK_USDHC2>; + assigned-clock-rates = <400000000>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_400M>; +}; + +&usdhc3 { + u-boot,dm-spl; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + /* + * prevents voltage switch warn: driver will switch even at + * fixed voltage + */ + /delete-property/ vmmc-supply; + /delete-property/ vqmmc-supply; + assigned-clocks = <&clk IMX8MM_CLK_USDHC3>; + assigned-clock-rates = <400000000>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_400M>; +}; + +&i2c1 { + u-boot,dm-spl; +}; + +&{/soc@0/bus@30800000/i2c@30a20000/pmic@25} { + u-boot,dm-spl; +}; + +&{/soc@0/bus@30800000/i2c@30a20000/pmic@25/regulators} { + u-boot,dm-spl; +}; + +&pinctrl_i2c1 { + u-boot,dm-spl; +}; + +&pinctrl_pmic { + u-boot,dm-spl; +}; + +&wdog1 { + u-boot,dm-spl; +}; diff --git a/arch/arm/dts/imx8mm-phg.dts b/arch/arm/dts/imx8mm-phg.dts new file mode 100644 index 0000000000..e9447738b1 --- /dev/null +++ b/arch/arm/dts/imx8mm-phg.dts @@ -0,0 +1,266 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 Fabio Estevam <festevam@denx.de> + */ + +/dts-v1/; + +#include "imx8mm-tqma8mqml.dtsi" + +/ { + model = "Cloos i.MX8MM PHG board"; + compatible = "cloos,imx8mm-phg", "tq,imx8mm-tqma8mqml", "fsl,imx8mm"; + + aliases { + mmc0 = &usdhc3; + mmc1 = &usdhc2; + }; + + chosen { + stdout-path = &uart2; + }; + + beeper { + compatible = "gpio-beeper"; + pinctrl-0 = <&pinctrl_beeper>; + gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_led>; + + led-0 { + label = "status1"; + gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; + }; + + led-1 { + label = "status2"; + gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; + }; + + led-2 { + label = "status3"; + gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; + }; + + led-3 { + label = "run"; + gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; + }; + + led-4 { + label = "powerled"; + gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>; + }; + }; + + reg_usb_otg_vbus: regulator-usb-otg-vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_otg_vbus_ctrl>; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio2 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usdhc2_vmmc: regulator-vmmc { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; + regulator-name = "VSD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + enable-active-high; + startup-delay-us = <100>; + off-on-delay-us = <12000>; + }; +}; + +&ecspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy0>; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + reg = <0>; + compatible = "ethernet-phy-ieee802.3-c22"; + }; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&usbphynop1 { + power-domains = <&pgc_otg1>; +}; + +&usbphynop2 { + power-domains = <&pgc_otg2>; +}; + +&usbotg1 { + dr_mode = "host"; + vbus-supply = <®_usb_otg_vbus>; + status = "okay"; +}; + +&usbotg2 { + dr_mode = "host"; + status = "okay"; +}; + +&usdhc2 { + assigned-clocks = <&clk IMX8MM_CLK_USDHC2>; + assigned-clock-rates = <400000000>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_400M>; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + bus-width = <4>; + cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; + disable-wp; + no-mmc; + no-sdio; + sd-uhs-sdr104; + sd-uhs-ddr50; + vmmc-supply = <®_usdhc2_vmmc>; + status = "okay"; +}; + +&iomuxc { + pinctrl_beeper: beepergrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x19 + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x82 + MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x82 + MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x82 + MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x19 + >; + }; + + pinctrl_fec1: fec1grp { + fsl,pins = < + MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x40000002 + MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x40000002 + MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x14 + MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x14 + MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x14 + MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x14 + MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x90 + MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x90 + MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x90 + MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x90 + MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x14 + MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x90 + MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x90 + MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x14 + MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x10 + >; + }; + + pinctrl_gpio_led: gpioledgrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x19 + MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x19 + MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x19 + MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x19 + MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x19 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 + MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3 + >; + }; + + pinctrl_otg_vbus_ctrl: otgvbusctrlgrp { + fsl,pins = < + MX8MM_IOMUXC_SD1_DATA0_GPIO2_IO2 0x119 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 + MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2grpgpiogrp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x1c4 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 + >; + }; +}; diff --git a/arch/arm/dts/imx8mm-tqma8mqml.dtsi b/arch/arm/dts/imx8mm-tqma8mqml.dtsi new file mode 100644 index 0000000000..f649dfacb4 --- /dev/null +++ b/arch/arm/dts/imx8mm-tqma8mqml.dtsi @@ -0,0 +1,341 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright 2020-2021 TQ-Systems GmbH + */ + +#include <dt-bindings/phy/phy-imx8-pcie.h> +#include "imx8mm.dtsi" + +/ { + model = "TQ-Systems GmbH i.MX8MM TQMa8MxML"; + compatible = "tq,imx8mm-tqma8mqml", "fsl,imx8mm"; + + memory@40000000 { + device_type = "memory"; + /* our minimum RAM config will be 1024 MiB */ + reg = <0x00000000 0x40000000 0 0x40000000>; + }; + + /* e-MMC IO, needed for HS modes */ + reg_vcc1v8: regulator-vcc1v8 { + compatible = "regulator-fixed"; + regulator-name = "TQMA8MXML_VCC1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + /* identical to buck4_reg, but should never change */ + reg_vcc3v3: regulator-vcc3v3 { + compatible = "regulator-fixed"; + regulator-name = "TQMA8MXML_VCC3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* global autoconfigured region for contiguous allocations */ + linux,cma { + compatible = "shared-dma-pool"; + reusable; + /* 640 MiB */ + size = <0 0x28000000>; + /* 1024 - 128 MiB, our minimum RAM config will be 1024 MiB */ + alloc-ranges = <0 0x40000000 0 0x78000000>; + linux,cma-default; + }; + }; +}; + +&A53_0 { + cpu-supply = <&buck2_reg>; +}; + +&flexspi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi>; + status = "okay"; + + flash0: flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <84000000>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; + }; +}; + +&gpu_2d { + status = "okay"; +}; + +&gpu_3d { + status = "okay"; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; + + sensor0: temperature-sensor-eeprom@1b { + compatible = "nxp,se97", "jedec,jc-42.4-temp"; + reg = <0x1b>; + }; + + pca9450: pmic@25 { + compatible = "nxp,pca9450a"; + reg = <0x25>; + + /* PMIC PCA9450 PMIC_nINT GPIO1_IO08 */ + pinctrl-0 = <&pinctrl_pmic>; + pinctrl-names = "default"; + interrupt-parent = <&gpio1>; + interrupts = <8 IRQ_TYPE_LEVEL_LOW>; + + regulators { + /* V_0V85_SOC: 0.85 */ + buck1_reg: BUCK1 { + regulator-name = "BUCK1"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + }; + + /* VDD_ARM */ + buck2_reg: BUCK2 { + regulator-name = "BUCK2"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1000000>; + regulator-boot-on; + regulator-always-on; + nxp,dvs-run-voltage = <950000>; + nxp,dvs-standby-voltage = <850000>; + regulator-ramp-delay = <3125>; + }; + + /* V_0V85_GPU / DRAM / VPU */ + buck3_reg: BUCK3 { + regulator-name = "BUCK3"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <950000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + }; + + /* VCC3V3 -> VMMC, ... must not be changed */ + buck4_reg: BUCK4 { + regulator-name = "BUCK4"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + /* V_1V8 -> VQMMC, SPI-NOR, ... must not be changed */ + buck5_reg: BUCK5 { + regulator-name = "BUCK5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + /* V_1V1 -> RAM, ... must not be changed */ + buck6_reg: BUCK6 { + regulator-name = "BUCK6"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-boot-on; + regulator-always-on; + }; + + /* V_1V8_SNVS */ + ldo1_reg: LDO1 { + regulator-name = "LDO1"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + /* V_0V8_SNVS */ + ldo2_reg: LDO2 { + regulator-name = "LDO2"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <850000>; + regulator-boot-on; + regulator-always-on; + }; + + /* V_1V8_ANA */ + ldo3_reg: LDO3 { + regulator-name = "LDO3"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + /* V_0V9_MIPI */ + ldo4_reg: LDO4 { + regulator-name = "LDO4"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-boot-on; + regulator-always-on; + }; + + /* VCC SD IO - switched using SD2 VSELECT */ + ldo5_reg: LDO5 { + regulator-name = "LDO5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + }; + }; + + + pcf85063: rtc@51 { + compatible = "nxp,pcf85063a"; + reg = <0x51>; + quartz-load-femtofarads = <7000>; + }; + + eeprom1: eeprom@53 { + compatible = "nxp,se97b", "atmel,24c02"; + read-only; + reg = <0x53>; + pagesize = <16>; + }; + + eeprom0: eeprom@57 { + compatible = "atmel,24c64"; + reg = <0x57>; + pagesize = <32>; + }; +}; + +&pcie_phy { + fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>; + fsl,clkreq-unsupported; +}; + +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + bus-width = <8>; + non-removable; + no-sd; + no-sdio; + vmmc-supply = <®_vcc3v3>; + vqmmc-supply = <®_vcc1v8>; + status = "okay"; +}; + +/* + * Attention: + * wdog reset is routed to PMIC, PMIC must be preconfigured to force POR + * without LDO for SNVS. GPIO1_IO02 must not be used as GPIO. + */ +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; + +&iomuxc { + pinctrl_flexspi: flexspigrp { + fsl,pins = <MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x82>, + <MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82>, + <MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82>, + <MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82>, + <MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82>, + <MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82>; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = <MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x40000004>, + <MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x40000004>; + }; + + pinctrl_i2c1_gpio: i2c1gpiogrp { + fsl,pins = <MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x40000004>, + <MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x40000004>; + }; + + pinctrl_pmic: pmicgrp { + fsl,pins = <MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x94>; + }; + + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { + fsl,pins = <MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x84>; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = <MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x1d4>, + <MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d2>, + <MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4>, + <MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4>, + <MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4>, + <MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4>, + <MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4>, + <MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4>, + <MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4>, + <MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4>, + <MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x84>, + /* option USDHC3_RESET_B not defined, only in RM */ + <MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x84>; + }; + + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { + fsl,pins = <MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x1d2>, + <MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d2>, + <MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4>, + <MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4>, + <MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4>, + <MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4>, + <MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4>, + <MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4>, + <MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4>, + <MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4>, + <MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x84>, + /* option USDHC3_RESET_B not defined, only in RM */ + <MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x84>; + }; + + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { + fsl,pins = <MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x1d6>, + <MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d2>, + <MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4>, + <MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4>, + <MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4>, + <MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4>, + <MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4>, + <MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4>, + <MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4>, + <MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4>, + <MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x84>, + /* option USDHC3_RESET_B not defined, only in RM */ + <MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x84>; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = <MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x84>; + }; +}; diff --git a/arch/arm/dts/imx8mm-u-boot.dtsi b/arch/arm/dts/imx8mm-u-boot.dtsi index 60d49bc3d7..25dc8e12dd 100644 --- a/arch/arm/dts/imx8mm-u-boot.dtsi +++ b/arch/arm/dts/imx8mm-u-boot.dtsi @@ -99,6 +99,7 @@ }; }; +#ifndef CONFIG_ARMV8_PSCI atf { arch = "arm64"; compression = "none"; @@ -112,6 +113,7 @@ type = "atf-bl31"; }; }; +#endif binman_fip: fip { arch = "arm64"; @@ -140,7 +142,9 @@ description = "NAME"; fdt = "fdt-SEQ"; firmware = "uboot"; +#ifndef CONFIG_ARMV8_PSCI loadables = "atf"; +#endif }; }; }; diff --git a/arch/arm/dts/imx8mm-venice-gw700x.dtsi b/arch/arm/dts/imx8mm-venice-gw700x.dtsi index 66a0d103c9..c305e325d0 100644 --- a/arch/arm/dts/imx8mm-venice-gw700x.dtsi +++ b/arch/arm/dts/imx8mm-venice-gw700x.dtsi @@ -119,8 +119,11 @@ &i2c1 { clock-frequency = <100000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; gsc: gsc@20 { @@ -365,8 +368,11 @@ &i2c2 { clock-frequency = <400000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; eeprom@52 { @@ -435,6 +441,13 @@ >; }; + pinctrl_i2c1_gpio: i2c1gpiogrp { + fsl,pins = < + MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x400001c3 + MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x400001c3 + >; + }; + pinctrl_i2c2: i2c2grp { fsl,pins = < MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 @@ -442,6 +455,13 @@ >; }; + pinctrl_i2c2_gpio: i2c2gpiogrp { + fsl,pins = < + MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16 0x400001c3 + MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17 0x400001c3 + >; + }; + pinctrl_uart2: uart2grp { fsl,pins = < MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 diff --git a/arch/arm/dts/imx8mm-venice-gw7901.dts b/arch/arm/dts/imx8mm-venice-gw7901.dts index d3ee6fc4ba..826627bd45 100644 --- a/arch/arm/dts/imx8mm-venice-gw7901.dts +++ b/arch/arm/dts/imx8mm-venice-gw7901.dts @@ -326,8 +326,11 @@ &i2c1 { clock-frequency = <100000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; gsc: gsc@20 { @@ -477,8 +480,11 @@ &i2c2 { clock-frequency = <400000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; pmic@4b { @@ -600,8 +606,11 @@ &i2c3 { clock-frequency = <400000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_gpio>; + scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; leds_gpio: gpio@20 { @@ -673,8 +682,11 @@ &i2c4 { clock-frequency = <400000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c4>; + pinctrl-1 = <&pinctrl_i2c4_gpio>; + scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; }; @@ -852,6 +864,13 @@ >; }; + pinctrl_i2c1_gpio: i2c1gpiogrp { + fsl,pins = < + MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x400001c3 + MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x400001c3 + >; + }; + pinctrl_i2c2: i2c2grp { fsl,pins = < MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 @@ -859,6 +878,13 @@ >; }; + pinctrl_i2c2_gpio: i2c2gpiogrp { + fsl,pins = < + MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16 0x400001c3 + MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17 0x400001c3 + >; + }; + pinctrl_i2c3: i2c3grp { fsl,pins = < MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 @@ -866,6 +892,13 @@ >; }; + pinctrl_i2c3_gpio: i2c3gpiogrp { + fsl,pins = < + MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 0x400001c3 + MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19 0x400001c3 + >; + }; + pinctrl_i2c4: i2c4grp { fsl,pins = < MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3 @@ -873,6 +906,13 @@ >; }; + pinctrl_i2c4_gpio: i2c4gpiogrp { + fsl,pins = < + MX8MM_IOMUXC_I2C4_SCL_GPIO5_IO20 0x400001c3 + MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21 0x400001c3 + >; + }; + pinctrl_ksz: kszgrp { fsl,pins = < MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x41 diff --git a/arch/arm/dts/imx8mm-venice-gw7902-u-boot.dtsi b/arch/arm/dts/imx8mm-venice-gw7902-u-boot.dtsi index f21e46b12d..d58a7d14b6 100644 --- a/arch/arm/dts/imx8mm-venice-gw7902-u-boot.dtsi +++ b/arch/arm/dts/imx8mm-venice-gw7902-u-boot.dtsi @@ -6,6 +6,13 @@ #include "imx8mm-venice-u-boot.dtsi" &gpio1 { + m2pwren { + gpio-hog; + output-low; + gpios = <8 GPIO_ACTIVE_HIGH>; + line-name = "m2_pwren"; + }; + m2rst { gpio-hog; output-low; @@ -96,6 +103,13 @@ line-name = "app_gpio1"; }; + vdd4p0en { + gpio-hog; + output-low; + gpios = <22 GPIO_ACTIVE_HIGH>; + line-name = "vdd_4p0_en"; + }; + uart1rs485 { gpio-hog; output-low; diff --git a/arch/arm/dts/imx8mm-venice-gw7902.dts b/arch/arm/dts/imx8mm-venice-gw7902.dts index 31f4c735fe..11481e09c7 100644 --- a/arch/arm/dts/imx8mm-venice-gw7902.dts +++ b/arch/arm/dts/imx8mm-venice-gw7902.dts @@ -261,7 +261,7 @@ &gpio1 { gpio-line-names = "", "", "", "", "", "", "", "", - "", "", "", "", "", "m2_reset", "", "m2_wdis#", + "m2_pwr_en", "", "", "", "", "m2_reset", "", "m2_wdis#", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", ""; }; @@ -283,7 +283,8 @@ &gpio4 { gpio-line-names = "", "", "", "", "", "", "", "", "", "", "", "amp_gpio3", "amp_gpio2", "", "amp_gpio1", "", - "", "", "", "", "amp_gpio4", "app_gpio1", "", "uart1_rs485", + "lte_pwr#", "lte_rst", "lte_int", "", + "amp_gpio4", "app_gpio1", "vdd_4p0_en", "uart1_rs485", "", "uart1_term", "uart1_half", "app_gpio2", "mipi_gpio1", "", "", ""; }; @@ -298,8 +299,11 @@ &i2c1 { clock-frequency = <100000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; gsc: gsc@20 { @@ -566,8 +570,11 @@ &i2c2 { clock-frequency = <400000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; accelerometer@19 { @@ -585,16 +592,22 @@ /* off-board header */ &i2c3 { clock-frequency = <400000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_gpio>; + scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; }; /* off-board header */ &i2c4 { clock-frequency = <400000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c4>; + pinctrl-1 = <&pinctrl_i2c4_gpio>; + scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; }; @@ -738,14 +751,19 @@ pinctrl_hog: hoggrp { fsl,pins = < MX8MM_IOMUXC_NAND_CE0_B_GPIO3_IO1 0x40000159 /* M2_GDIS# */ + MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x40000041 /* M2_PWR_EN */ MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x40000041 /* M2_RESET */ MX8MM_IOMUXC_NAND_DATA01_GPIO3_IO7 0x40000119 /* M2_OFF# */ MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x40000159 /* M2_WDIS# */ + MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x40000041 /* LTE_INT */ + MX8MM_IOMUXC_SAI1_TXD5_GPIO4_IO17 0x40000041 /* LTE_RST# */ + MX8MM_IOMUXC_SAI1_TXD4_GPIO4_IO16 0x40000041 /* LTE_PWR */ MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x40000041 /* AMP GPIO1 */ MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12 0x40000041 /* AMP GPIO2 */ MX8MM_IOMUXC_SAI1_TXC_GPIO4_IO11 0x40000041 /* AMP GPIO3 */ MX8MM_IOMUXC_SAI1_MCLK_GPIO4_IO20 0x40000041 /* AMP_GPIO4 */ MX8MM_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x40000041 /* APP GPIO1 */ + MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x40000041 /* VDD_4P0_EN */ MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x40000041 /* APP GPIO2 */ MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8 0x40000041 /* UART2_EN# */ MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x40000041 /* MIPI_GPIO1 */ @@ -779,8 +797,6 @@ MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x19 /* RST# */ MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x19 /* IRQ# */ - MX8MM_IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN 0x141 - MX8MM_IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT 0x141 >; }; @@ -797,6 +813,13 @@ >; }; + pinctrl_i2c1_gpio: i2c1gpiogrp { + fsl,pins = < + MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x400001c3 + MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x400001c3 + >; + }; + pinctrl_i2c2: i2c2grp { fsl,pins = < MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 @@ -804,6 +827,13 @@ >; }; + pinctrl_i2c2_gpio: i2c2gpiogrp { + fsl,pins = < + MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16 0x400001c3 + MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17 0x400001c3 + >; + }; + pinctrl_i2c3: i2c3grp { fsl,pins = < MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 @@ -811,6 +841,13 @@ >; }; + pinctrl_i2c3_gpio: i2c3gpiogrp { + fsl,pins = < + MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 0x400001c3 + MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19 0x400001c3 + >; + }; + pinctrl_i2c4: i2c4grp { fsl,pins = < MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3 @@ -818,6 +855,13 @@ >; }; + pinctrl_i2c4_gpio: i2c4gpiogrp { + fsl,pins = < + MX8MM_IOMUXC_I2C4_SCL_GPIO5_IO20 0x400001c3 + MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21 0x400001c3 + >; + }; + pinctrl_gpio_leds: gpioledgrp { fsl,pins = < MX8MM_IOMUXC_SAI5_RXD0_GPIO3_IO21 0x19 diff --git a/arch/arm/dts/imx8mm-venice-gw7903.dts b/arch/arm/dts/imx8mm-venice-gw7903.dts index 19f6d2943d..1ec91c5c6a 100644 --- a/arch/arm/dts/imx8mm-venice-gw7903.dts +++ b/arch/arm/dts/imx8mm-venice-gw7903.dts @@ -265,8 +265,11 @@ &i2c1 { clock-frequency = <100000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; gsc: gsc@20 { @@ -397,8 +400,11 @@ &i2c2 { clock-frequency = <400000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; pmic@4b { @@ -520,8 +526,11 @@ &i2c3 { clock-frequency = <400000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_gpio>; + scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; accelerometer@19 { @@ -681,6 +690,13 @@ >; }; + pinctrl_i2c1_gpio: i2c1gpiogrp { + fsl,pins = < + MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x400001c3 + MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x400001c3 + >; + }; + pinctrl_i2c2: i2c2grp { fsl,pins = < MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 @@ -688,6 +704,13 @@ >; }; + pinctrl_i2c2_gpio: i2c2gpiogrp { + fsl,pins = < + MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16 0x400001c3 + MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17 0x400001c3 + >; + }; + pinctrl_i2c3: i2c3grp { fsl,pins = < MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 @@ -695,6 +718,13 @@ >; }; + pinctrl_i2c3_gpio: i2c3gpiogrp { + fsl,pins = < + MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 0x400001c3 + MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19 0x400001c3 + >; + }; + pinctrl_gpio_leds: gpioledgrp { fsl,pins = < MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x19 diff --git a/arch/arm/dts/imx8mm-venice-gw7904.dts b/arch/arm/dts/imx8mm-venice-gw7904.dts index a67771d021..93c9651c31 100644 --- a/arch/arm/dts/imx8mm-venice-gw7904.dts +++ b/arch/arm/dts/imx8mm-venice-gw7904.dts @@ -315,8 +315,11 @@ &i2c1 { clock-frequency = <100000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; gsc: gsc@20 { @@ -441,8 +444,11 @@ &i2c2 { clock-frequency = <400000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; pmic@4b { @@ -564,8 +570,11 @@ &i2c3 { clock-frequency = <400000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_gpio>; + scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; accelerometer@19 { @@ -582,8 +591,11 @@ &i2c4 { clock-frequency = <400000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c4>; + pinctrl-1 = <&pinctrl_i2c4_gpio>; + scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; gpioled: gpio@27 { @@ -738,6 +750,13 @@ >; }; + pinctrl_i2c1_gpio: i2c1gpiogrp { + fsl,pins = < + MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x400001c3 + MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x400001c3 + >; + }; + pinctrl_i2c2: i2c2grp { fsl,pins = < MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 @@ -745,6 +764,13 @@ >; }; + pinctrl_i2c2_gpio: i2c2gpiogrp { + fsl,pins = < + MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16 0x400001c3 + MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17 0x400001c3 + >; + }; + pinctrl_i2c3: i2c3grp { fsl,pins = < MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 @@ -752,6 +778,13 @@ >; }; + pinctrl_i2c3_gpio: i2c3gpiogrp { + fsl,pins = < + MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 0x400001c3 + MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19 0x400001c3 + >; + }; + pinctrl_i2c4: i2c4grp { fsl,pins = < MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3 @@ -759,6 +792,13 @@ >; }; + pinctrl_i2c4_gpio: i2c4gpiogrp { + fsl,pins = < + MX8MM_IOMUXC_I2C4_SCL_GPIO5_IO20 0x400001c3 + MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21 0x400001c3 + >; + }; + pinctrl_pcie0: pciegrp { fsl,pins = < MX8MM_IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x41 diff --git a/arch/arm/dts/imx8mm-venice-u-boot.dtsi b/arch/arm/dts/imx8mm-venice-u-boot.dtsi index 68978a0413..6f786b9467 100644 --- a/arch/arm/dts/imx8mm-venice-u-boot.dtsi +++ b/arch/arm/dts/imx8mm-venice-u-boot.dtsi @@ -57,6 +57,10 @@ u-boot,dm-spl; }; +&pinctrl_i2c1_gpio { + u-boot,dm-spl; +}; + &gsc { u-boot,dm-spl; }; diff --git a/arch/arm/dts/imx8mm-venice.dts b/arch/arm/dts/imx8mm-venice.dts index 39b030691e..d0929908ce 100644 --- a/arch/arm/dts/imx8mm-venice.dts +++ b/arch/arm/dts/imx8mm-venice.dts @@ -23,8 +23,11 @@ &i2c1 { clock-frequency = <100000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio5 14 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>; status = "okay"; gsc: gsc@20 { @@ -89,6 +92,13 @@ >; }; + pinctrl_i2c1_gpio: i2c1grp-gpio-grp { + fsl,pins = < + MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x400001c3 + MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x400001c3 + >; + }; + pinctrl_i2c2: i2c2grp { fsl,pins = < MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 diff --git a/arch/arm/dts/imx8mn-u-boot.dtsi b/arch/arm/dts/imx8mn-u-boot.dtsi index 95f45ad252..98659bb528 100644 --- a/arch/arm/dts/imx8mn-u-boot.dtsi +++ b/arch/arm/dts/imx8mn-u-boot.dtsi @@ -85,7 +85,7 @@ #ifdef CONFIG_IMX8M_LPDDR4 filename = "lpddr4_pmu_train_1d_imem.bin"; #elif CONFIG_IMX8M_DDR4 - filename = "ddr4_imem_1d.bin"; + filename = "ddr4_imem_1d_201810.bin"; #else filename = "ddr3_imem_1d.bin"; #endif @@ -97,7 +97,7 @@ #ifdef CONFIG_IMX8M_LPDDR4 filename = "lpddr4_pmu_train_1d_dmem.bin"; #elif CONFIG_IMX8M_DDR4 - filename = "ddr4_dmem_1d.bin"; + filename = "ddr4_dmem_1d_201810.bin"; #else filename = "ddr3_dmem_1d.bin"; #endif @@ -105,11 +105,12 @@ align-end = <4>; }; +#if defined(CONFIG_IMX8M_LPDDR4) || defined(CONFIG_IMX8M_DDR4) ddr-2d-imem-fw { #ifdef CONFIG_IMX8M_LPDDR4 filename = "lpddr4_pmu_train_2d_imem.bin"; -#elif CONFIG_IMX8M_DDR4 - filename = "ddr4_imem_2d.bin"; +#else + filename = "ddr4_imem_2d_201810.bin"; #endif type = "blob-ext"; align-end = <4>; @@ -118,12 +119,13 @@ ddr-2d-dmem-fw { #ifdef CONFIG_IMX8M_LPDDR4 filename = "lpddr4_pmu_train_2d_dmem.bin"; -#elif CONFIG_IMX8M_DDR4 - filename = "ddr4_dmem_2d.bin"; +#else + filename = "ddr4_dmem_2d_201810.bin"; #endif type = "blob-ext"; align-end = <4>; }; +#endif }; spl { @@ -161,6 +163,7 @@ }; }; +#ifndef CONFIG_ARMV8_PSCI atf { arch = "arm64"; compression = "none"; @@ -174,6 +177,7 @@ type = "atf-bl31"; }; }; +#endif binman_fip: fip { arch = "arm64"; @@ -202,7 +206,9 @@ description = "NAME"; fdt = "fdt-SEQ"; firmware = "uboot"; +#ifndef CONFIG_ARMV8_PSCI loadables = "atf"; +#endif }; }; }; diff --git a/arch/arm/dts/imx8mn-venice-gw7902-u-boot.dtsi b/arch/arm/dts/imx8mn-venice-gw7902-u-boot.dtsi index 17e6828c79..10656ce903 100644 --- a/arch/arm/dts/imx8mn-venice-gw7902-u-boot.dtsi +++ b/arch/arm/dts/imx8mn-venice-gw7902-u-boot.dtsi @@ -6,6 +6,13 @@ #include "imx8mn-venice-u-boot.dtsi" &gpio1 { + m2pwren { + gpio-hog; + output-low; + gpios = <8 GPIO_ACTIVE_HIGH>; + line-name = "m2_pwren"; + }; + m2rst { gpio-hog; output-low; @@ -54,6 +61,13 @@ line-name = "app_gpio1"; }; + vdd4p0en { + gpio-hog; + output-low; + gpios = <22 GPIO_ACTIVE_HIGH>; + line-name = "vdd_4p0_en"; + }; + uart1rs485 { gpio-hog; output-low; diff --git a/arch/arm/dts/imx8mn-venice-gw7902.dts b/arch/arm/dts/imx8mn-venice-gw7902.dts index dd4302ac1d..97582db71c 100644 --- a/arch/arm/dts/imx8mn-venice-gw7902.dts +++ b/arch/arm/dts/imx8mn-venice-gw7902.dts @@ -256,7 +256,7 @@ &gpio1 { gpio-line-names = "", "", "", "", "", "", "", "", - "", "", "", "", "", "m2_reset", "", "m2_wdis#", + "m2_pwr_en", "", "", "", "", "m2_reset", "", "m2_wdis#", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", ""; }; @@ -278,7 +278,7 @@ &gpio4 { gpio-line-names = "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", - "", "", "", "", "", "app_gpio1", "", "uart1_rs485", + "", "", "", "", "", "app_gpio1", "vdd_4p0_en", "uart1_rs485", "", "uart1_term", "uart1_half", "app_gpio2", "mipi_gpio1", "", "", ""; }; @@ -297,8 +297,11 @@ &i2c1 { clock-frequency = <100000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; gsc: gsc@20 { @@ -565,8 +568,11 @@ &i2c2 { clock-frequency = <400000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; accelerometer@19 { @@ -584,16 +590,22 @@ /* off-board header */ &i2c3 { clock-frequency = <400000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_gpio>; + scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; }; /* off-board header */ &i2c4 { clock-frequency = <400000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c4>; + pinctrl-1 = <&pinctrl_i2c4_gpio>; + scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; }; @@ -689,10 +701,12 @@ pinctrl_hog: hoggrp { fsl,pins = < MX8MN_IOMUXC_NAND_CE0_B_GPIO3_IO1 0x40000159 /* M2_GDIS# */ + MX8MN_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x40000041 /* M2_PWR_EN */ MX8MN_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x40000041 /* M2_RESET */ MX8MN_IOMUXC_NAND_DATA01_GPIO3_IO7 0x40000119 /* M2_OFF# */ MX8MN_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x40000159 /* M2_WDIS# */ MX8MN_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x40000041 /* APP GPIO1 */ + MX8MN_IOMUXC_SAI2_RXC_GPIO4_IO22 0x40000041 /* VDD_4P0_EN */ MX8MN_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x40000041 /* APP GPIO2 */ MX8MN_IOMUXC_SD1_DATA6_GPIO2_IO8 0x40000041 /* UART2_EN# */ MX8MN_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x40000041 /* MIPI_GPIO1 */ @@ -726,8 +740,6 @@ MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f MX8MN_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x19 /* RST# */ MX8MN_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x19 /* IRQ# */ - MX8MN_IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN 0x141 - MX8MN_IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT 0x141 >; }; @@ -744,6 +756,13 @@ >; }; + pinctrl_i2c1_gpio: i2c1gpiogrp { + fsl,pins = < + MX8MN_IOMUXC_I2C1_SCL_GPIO5_IO14 0x400001c3 + MX8MN_IOMUXC_I2C1_SDA_GPIO5_IO15 0x400001c3 + >; + }; + pinctrl_i2c2: i2c2grp { fsl,pins = < MX8MN_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 @@ -751,6 +770,13 @@ >; }; + pinctrl_i2c2_gpio: i2c2gpiogrp { + fsl,pins = < + MX8MN_IOMUXC_I2C2_SCL_GPIO5_IO16 0x400001c3 + MX8MN_IOMUXC_I2C2_SDA_GPIO5_IO17 0x400001c3 + >; + }; + pinctrl_i2c3: i2c3grp { fsl,pins = < MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 @@ -758,6 +784,13 @@ >; }; + pinctrl_i2c3_gpio: i2c3gpiogrp { + fsl,pins = < + MX8MN_IOMUXC_I2C3_SCL_GPIO5_IO18 0x400001c3 + MX8MN_IOMUXC_I2C3_SDA_GPIO5_IO19 0x400001c3 + >; + }; + pinctrl_i2c4: i2c4grp { fsl,pins = < MX8MN_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3 @@ -765,6 +798,13 @@ >; }; + pinctrl_i2c4_gpio: i2c4gpiogrp { + fsl,pins = < + MX8MN_IOMUXC_I2C4_SCL_GPIO5_IO20 0x400001c3 + MX8MN_IOMUXC_I2C4_SDA_GPIO5_IO21 0x400001c3 + >; + }; + pinctrl_gpio_leds: gpioledgrp { fsl,pins = < MX8MN_IOMUXC_SAI5_RXD0_GPIO3_IO21 0x19 diff --git a/arch/arm/dts/imx8mn-venice-u-boot.dtsi b/arch/arm/dts/imx8mn-venice-u-boot.dtsi index aea48f2d79..4af6b8b4ed 100644 --- a/arch/arm/dts/imx8mn-venice-u-boot.dtsi +++ b/arch/arm/dts/imx8mn-venice-u-boot.dtsi @@ -49,6 +49,10 @@ u-boot,dm-spl; }; +&pinctrl_i2c1_gpio { + u-boot,dm-spl; +}; + &gsc { u-boot,dm-spl; }; diff --git a/arch/arm/dts/imx8mn-venice.dts b/arch/arm/dts/imx8mn-venice.dts index eeae225632..9e31b37f24 100644 --- a/arch/arm/dts/imx8mn-venice.dts +++ b/arch/arm/dts/imx8mn-venice.dts @@ -23,8 +23,11 @@ &i2c1 { clock-frequency = <100000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio5 14 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>; status = "okay"; gsc: gsc@20 { @@ -89,6 +92,13 @@ >; }; + pinctrl_i2c1_gpio: i2c1grp-gpio-grp { + fsl,pins = < + MX8MN_IOMUXC_I2C1_SCL_GPIO5_IO14 0x400001c3 + MX8MN_IOMUXC_I2C1_SDA_GPIO5_IO15 0x400001c3 + >; + }; + pinctrl_i2c2: i2c2grp { fsl,pins = < MX8MN_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 diff --git a/arch/arm/dts/imx8mp-rsb3720-a1-u-boot.dtsi b/arch/arm/dts/imx8mp-rsb3720-a1-u-boot.dtsi index 4419967ee4..32d9fbc886 100644 --- a/arch/arm/dts/imx8mp-rsb3720-a1-u-boot.dtsi +++ b/arch/arm/dts/imx8mp-rsb3720-a1-u-boot.dtsi @@ -158,12 +158,10 @@ }; }; }; - - configurations { - conf { - loadables = "atf", "fip"; - }; - }; }; }; }; + +&binman_configuration { + loadables = "atf", "fip"; +}; diff --git a/arch/arm/dts/imx8mp-u-boot.dtsi b/arch/arm/dts/imx8mp-u-boot.dtsi index f9883aa133..07538da621 100644 --- a/arch/arm/dts/imx8mp-u-boot.dtsi +++ b/arch/arm/dts/imx8mp-u-boot.dtsi @@ -120,6 +120,7 @@ }; }; +#ifndef CONFIG_ARMV8_PSCI atf { description = "ARM Trusted Firmware"; type = "firmware"; @@ -133,6 +134,7 @@ type = "atf-bl31"; }; }; +#endif @fdt-SEQ { description = "NAME"; @@ -148,11 +150,13 @@ configurations { default = "@config-DEFAULT-SEQ"; - @config-SEQ { + binman_configuration: @config-SEQ { description = "NAME"; fdt = "fdt-SEQ"; firmware = "uboot"; +#ifndef CONFIG_ARMV8_PSCI loadables = "atf"; +#endif }; }; }; diff --git a/arch/arm/dts/imx8mp-venice-gw74xx.dts b/arch/arm/dts/imx8mp-venice-gw74xx.dts index 06b4c93c58..ceeca4966f 100644 --- a/arch/arm/dts/imx8mp-venice-gw74xx.dts +++ b/arch/arm/dts/imx8mp-venice-gw74xx.dts @@ -253,8 +253,11 @@ &i2c1 { clock-frequency = <100000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; gsc: gsc@20 { @@ -477,8 +480,11 @@ &i2c2 { clock-frequency = <400000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; accelerometer@19 { @@ -556,16 +562,22 @@ /* off-board header */ &i2c3 { clock-frequency = <400000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_gpio>; + scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; }; /* off-board header */ &i2c4 { clock-frequency = <400000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c4>; + pinctrl-1 = <&pinctrl_i2c4_gpio>; + scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; }; @@ -800,6 +812,13 @@ >; }; + pinctrl_i2c1_gpio: i2c1gpiogrp { + fsl,pins = < + MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 0x400001c2 + MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 0x400001c2 + >; + }; + pinctrl_i2c2: i2c2grp { fsl,pins = < MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2 @@ -807,6 +826,13 @@ >; }; + pinctrl_i2c2_gpio: i2c2gpiogrp { + fsl,pins = < + MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x400001c3 + MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x400001c3 + >; + }; + pinctrl_i2c3: i2c3grp { fsl,pins = < MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2 @@ -814,6 +840,13 @@ >; }; + pinctrl_i2c3_gpio: i2c3gpiogrp { + fsl,pins = < + MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18 0x400001c3 + MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19 0x400001c3 + >; + }; + pinctrl_i2c4: i2c4grp { fsl,pins = < MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x400001c2 @@ -821,6 +854,13 @@ >; }; + pinctrl_i2c4_gpio: i2c4gpiogrp { + fsl,pins = < + MX8MP_IOMUXC_I2C4_SCL__GPIO5_IO20 0x400001c3 + MX8MP_IOMUXC_I2C4_SDA__GPIO5_IO21 0x400001c3 + >; + }; + pinctrl_ksz: kszgrp { fsl,pins = < MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0x150 /* IRQ# */ diff --git a/arch/arm/dts/imx8mp-venice-u-boot.dtsi b/arch/arm/dts/imx8mp-venice-u-boot.dtsi index 96b9fa89cf..f9068ebfbe 100644 --- a/arch/arm/dts/imx8mp-venice-u-boot.dtsi +++ b/arch/arm/dts/imx8mp-venice-u-boot.dtsi @@ -57,6 +57,10 @@ u-boot,dm-spl; }; +&pinctrl_i2c1_gpio { + u-boot,dm-spl; +}; + &gsc { u-boot,dm-spl; }; diff --git a/arch/arm/dts/imx8mp-venice.dts b/arch/arm/dts/imx8mp-venice.dts index 6b1a7f1a89..77e5ac423d 100644 --- a/arch/arm/dts/imx8mp-venice.dts +++ b/arch/arm/dts/imx8mp-venice.dts @@ -23,8 +23,11 @@ &i2c1 { clock-frequency = <100000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio5 14 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>; status = "okay"; gsc: gsc@20 { @@ -89,6 +92,13 @@ >; }; + pinctrl_i2c1_gpio: i2c1grp-gpio-grp { + fsl,pins = < + MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 0x400001c3 + MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 0x400001c3 + >; + }; + pinctrl_i2c2: i2c2grp { fsl,pins = < MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c3 diff --git a/arch/arm/dts/imx8mq-u-boot.dtsi b/arch/arm/dts/imx8mq-u-boot.dtsi index 8d385e8da4..2bc9f413da 100644 --- a/arch/arm/dts/imx8mq-u-boot.dtsi +++ b/arch/arm/dts/imx8mq-u-boot.dtsi @@ -114,6 +114,7 @@ }; }; +#ifndef CONFIG_ARMV8_PSCI atf { arch = "arm64"; compression = "none"; @@ -127,6 +128,7 @@ type = "blob-ext"; }; }; +#endif fdt { compression = "none"; @@ -147,7 +149,9 @@ description = "NAME"; fdt = "fdt"; firmware = "uboot"; +#ifndef CONFIG_ARMV8_PSCI loadables = "atf"; +#endif }; }; }; diff --git a/arch/arm/dts/imx8ulp-evk-u-boot.dtsi b/arch/arm/dts/imx8ulp-evk-u-boot.dtsi index ad264f271e..7acdb4a98a 100644 --- a/arch/arm/dts/imx8ulp-evk-u-boot.dtsi +++ b/arch/arm/dts/imx8ulp-evk-u-boot.dtsi @@ -26,6 +26,7 @@ &iomuxc1 { u-boot,dm-spl; + fsl,mux_mask = <0xf00>; }; &pinctrl_lpuart5 { diff --git a/arch/arm/include/asm/arch-imx8/sci/rpc.h b/arch/arm/include/asm/arch-imx8/sci/rpc.h index 9f55904f44..39de7f0e3e 100644 --- a/arch/arm/include/asm/arch-imx8/sci/rpc.h +++ b/arch/arm/include/asm/arch-imx8/sci/rpc.h @@ -11,7 +11,7 @@ /* Defines */ #define SCFW_API_VERSION_MAJOR 1U -#define SCFW_API_VERSION_MINOR 15U +#define SCFW_API_VERSION_MINOR 21U #define SC_RPC_VERSION 1U diff --git a/arch/arm/include/asm/arch-imx8m/imx-regs.h b/arch/arm/include/asm/arch-imx8m/imx-regs.h index 20f4699a12..1559bf6d21 100644 --- a/arch/arm/include/asm/arch-imx8m/imx-regs.h +++ b/arch/arm/include/asm/arch-imx8m/imx-regs.h @@ -31,6 +31,7 @@ #define CCM_BASE_ADDR 0x30380000 #define SRC_BASE_ADDR 0x30390000 #define GPC_BASE_ADDR 0x303A0000 +#define CSU_BASE_ADDR 0x303E0000 #define SYSCNT_RD_BASE_ADDR 0x306A0000 #define SYSCNT_CMP_BASE_ADDR 0x306B0000 @@ -81,6 +82,9 @@ #define MXS_GPMI_BASE (APBH_DMA_ARB_BASE_ADDR + 0x02000) #define MXS_BCH_BASE (APBH_DMA_ARB_BASE_ADDR + 0x04000) +#define GICD_BASE 0x38800000 +#define GICR_BASE 0x38880000 + #define DDRC_DDR_SS_GPR0 0x3d000000 #define DDRC_IPS_BASE_ADDR(X) (0x3d400000 + ((X) * 0x2000000)) #define DDR_CSD1_BASE_ADDR 0x40000000 @@ -88,6 +92,10 @@ #define IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_MASK 0x70000 #define FEC_QUIRK_ENET_MAC +#ifdef CONFIG_ARMV8_PSCI /* Final jump location */ +#define CPU_RELEASE_ADDR 0x900000 +#endif + #define CAAM_ARB_BASE_ADDR (0x00100000) #define CAAM_ARB_END_ADDR (0x00107FFF) #define CAAM_IPS_BASE_ADDR (0x30900000) diff --git a/arch/arm/include/asm/arch-imx8m/imx8mq_pins.h b/arch/arm/include/asm/arch-imx8m/imx8mq_pins.h index c71913f209..16d418c687 100644 --- a/arch/arm/include/asm/arch-imx8m/imx8mq_pins.h +++ b/arch/arm/include/asm/arch-imx8m/imx8mq_pins.h @@ -538,7 +538,7 @@ enum { IMX8MQ_PAD_ECSPI2_SCLK__GPIO5_IO10 = IOMUX_PAD(0x046C, 0x0204, 5, 0x0000, 0, 0), IMX8MQ_PAD_ECSPI2_MOSI__ECSPI2_MOSI = IOMUX_PAD(0x0470, 0x0208, 0, 0x0000, 0, 0), - IMX8MQ_PAD_ECSPI2_MOSI__UART4_TX = IOMUX_PAD(0x0470, 0x0208, 1, 0x050C, 1, 0), + IMX8MQ_PAD_ECSPI2_MOSI__UART4_TX = IOMUX_PAD(0x0470, 0x0208, 1, 0x0000, 0, 0), IMX8MQ_PAD_ECSPI2_MOSI__GPIO5_IO11 = IOMUX_PAD(0x0470, 0x0208, 5, 0x0000, 0, 0), IMX8MQ_PAD_ECSPI2_MISO__ECSPI2_MISO = IOMUX_PAD(0x0474, 0x020C, 0, 0x0000, 0, 0), diff --git a/arch/arm/include/asm/mach-imx/sys_proto.h b/arch/arm/include/asm/mach-imx/sys_proto.h index dd0d3f2933..27fdc16cd5 100644 --- a/arch/arm/include/asm/mach-imx/sys_proto.h +++ b/arch/arm/include/asm/mach-imx/sys_proto.h @@ -149,6 +149,8 @@ struct rproc_att { u32 size; /* size of reg range */ }; +const struct rproc_att *imx_bootaux_get_hostmap(void); + struct rom_api { u16 ver; u16 tag; diff --git a/arch/arm/include/asm/psci.h b/arch/arm/include/asm/psci.h index 67e9234066..7343b941ef 100644 --- a/arch/arm/include/asm/psci.h +++ b/arch/arm/include/asm/psci.h @@ -22,6 +22,7 @@ #include <linux/bitops.h> #endif +#define ARM_PSCI_VER_1_1 (0x00010001) #define ARM_PSCI_VER_1_0 (0x00010000) #define ARM_PSCI_VER_0_2 (0x00000002) @@ -68,7 +69,6 @@ #define ARM_PSCI_0_2_FN64_AFFINITY_INFO ARM_PSCI_0_2_FN64(4) #define ARM_PSCI_0_2_FN64_MIGRATE ARM_PSCI_0_2_FN64(5) #define ARM_PSCI_0_2_FN64_MIGRATE_INFO_UP_CPU ARM_PSCI_0_2_FN64(7) -#define ARM_PSCI_0_2_FN64_SYSTEM_RESET2 ARM_PSCI_0_2_FN64(18) /* PSCI 1.0 interface */ #define ARM_PSCI_1_0_FN_PSCI_FEATURES ARM_PSCI_0_2_FN(10) @@ -86,6 +86,9 @@ #define ARM_PSCI_1_0_FN64_STAT_RESIDENCY ARM_PSCI_0_2_FN64(16) #define ARM_PSCI_1_0_FN64_STAT_COUNT ARM_PSCI_0_2_FN64(17) +/* PSCI 1.1 interface */ +#define ARM_PSCI_1_1_FN64_SYSTEM_RESET2 ARM_PSCI_0_2_FN64(18) + /* 1KB stack per core */ #define ARM_PSCI_STACK_SHIFT 10 #define ARM_PSCI_STACK_SIZE (1 << ARM_PSCI_STACK_SHIFT) diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile index 61b4f4f8cd..4dfc60eedc 100644 --- a/arch/arm/mach-imx/Makefile +++ b/arch/arm/mach-imx/Makefile @@ -235,8 +235,6 @@ endif targets += $(addprefix ../../../,SPL spl/u-boot-spl.cfgout u-boot-dtb.cfgout u-boot.cfgout u-boot.uim spl/u-boot-nand-spl.imx) -obj-$(CONFIG_ARM64) += lowlevel.o - obj-$(CONFIG_MX5) += mx5/ obj-$(CONFIG_MX6) += mx6/ obj-$(CONFIG_MX7) += mx7/ diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig index a0715e8091..5e4836b02f 100644 --- a/arch/arm/mach-imx/imx8m/Kconfig +++ b/arch/arm/mach-imx/imx8m/Kconfig @@ -2,6 +2,7 @@ if ARCH_IMX8M config IMX8M bool + select GICV3 if ARMV8_PSCI select HAS_CAAM select ROM_UNIFIED_SECTIONS select ARMV8_CRYPTO @@ -26,6 +27,14 @@ config IMX8MP config SYS_SOC default "imx8m" +config SYS_HAS_ARMV8_SECURE_BASE + bool "Enable secure address for PSCI image" + depends on ARMV8_PSCI + help + PSCI image can be re-located to secure RAM. + If enabled, please also define the value for ARMV8_SECURE_BASE, + for i.MX8M, it could be some address in OCRAM. + choice prompt "NXP i.MX8M board select" optional @@ -94,6 +103,13 @@ config TARGET_IMX8MM_MX8MENLO select SUPPORT_SPL select IMX8M_LPDDR4 +config TARGET_IMX8MM_PHG + bool "i.MX8MM PHG board" + select BINMAN + select IMX8MM + select SUPPORT_SPL + select IMX8M_LPDDR4 + config TARGET_IMX8MM_VENICE bool "Support Gateworks Venice iMX8M Mini module" select BINMAN @@ -233,6 +249,9 @@ config TARGET_IMX8MM_BEACON select IMX8MM select SUPPORT_SPL select IMX8M_LPDDR4 + select FSL_CAAM + select ARCH_MISC_INIT + select SPL_CRYPTO if SPL config TARGET_IMX8MN_BEACON bool "imx8mn Beacon Embedded devkit" @@ -240,6 +259,9 @@ config TARGET_IMX8MN_BEACON select IMX8MN select SUPPORT_SPL select IMX8M_LPDDR4 + select FSL_CAAM + select ARCH_MISC_INIT + select SPL_CRYPTO if SPL config TARGET_PHYCORE_IMX8MM bool "PHYTEC PHYCORE i.MX8MM" @@ -305,6 +327,7 @@ source "board/advantech/imx8mp_rsb3720a1/Kconfig" source "board/beacon/imx8mm/Kconfig" source "board/beacon/imx8mn/Kconfig" source "board/bsh/imx8mn_smm_s2/Kconfig" +source "board/cloos/imx8mm_phg/Kconfig" source "board/compulab/imx8mm-cl-iot-gate/Kconfig" source "board/data_modul/imx8mm_edm_sbc/Kconfig" source "board/dhelectronics/dh_imx8mp/Kconfig" diff --git a/arch/arm/mach-imx/imx8m/Makefile b/arch/arm/mach-imx/imx8m/Makefile index d9dee894aa..abd5ddc177 100644 --- a/arch/arm/mach-imx/imx8m/Makefile +++ b/arch/arm/mach-imx/imx8m/Makefile @@ -4,5 +4,6 @@ obj-y += lowlevel_init.o obj-y += clock_slice.o soc.o +obj-$(CONFIG_ARMV8_PSCI) += psci.o obj-$(CONFIG_IMX8MQ) += clock_imx8mq.o obj-$(CONFIG_IMX8MM)$(CONFIG_IMX8MN)$(CONFIG_IMX8MP) += clock_imx8mm.o diff --git a/arch/arm/mach-imx/imx8m/psci.c b/arch/arm/mach-imx/imx8m/psci.c new file mode 100644 index 0000000000..62f0b768cf --- /dev/null +++ b/arch/arm/mach-imx/imx8m/psci.c @@ -0,0 +1,288 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * This file implements basic PSCI support for i.MX8M + * + * Copyright (C) 2022 Marek Vasut <marex@denx.de> + */ +#include <asm/arch/imx-regs.h> +#include <asm/cache.h> +#include <asm/gic.h> +#include <asm/io.h> +#include <asm/psci.h> +#include <asm/secure.h> +#include <common.h> +#include <cpu_func.h> +#include <debug_uart.h> +#include <fsl_wdog.h> +#include <linux/bitops.h> + +#define SNVS_LPCR 0x38 +#define SNVS_LPCR_TOP BIT(6) +#define SNVS_LPCR_DP_EN BIT(5) +#define SNVS_LPCR_SRTC_ENV BIT(0) + +#define MPIDR_AFF0 GENMASK(7, 0) + +#define GPC_LPCR_A53_AD 0x4 +#define EN_Cn_WFI_PDN(cpu) BIT(((((cpu) & 1) * 2) + (((cpu) & 2) * 8))) +#define GPC_PGC_nCTRL(cpu) (0x800 + ((cpu) * 0x40)) +#define PGC_PCR BIT(0) +#define GPC_CPU_PGC_SW_PUP_REQ (IS_ENABLED(CONFIG_IMX8MP) ? 0xd0 : 0xf0) +#define COREn_A53_SW_PUP_REQ(cpu) BIT(cpu) + +#define SRC_A53RCR1 0x8 +#define A53_COREn_ENABLE(n) BIT(n) +#define SRC_GPR(n) (0x74 + ((n) * 4)) + +/* + * Helper code + */ +static u8 psci_state[CONFIG_ARMV8_PSCI_NR_CPUS] __secure_data = { + PSCI_AFFINITY_LEVEL_ON, + PSCI_AFFINITY_LEVEL_OFF, + PSCI_AFFINITY_LEVEL_OFF, + PSCI_AFFINITY_LEVEL_OFF +}; + +int psci_update_dt(void *fdt) +{ + return 0; +} + +__secure static void psci_set_state(int cpu, u8 state) +{ + psci_state[cpu] = state; + dsb(); + isb(); +} + +__secure static s32 psci_cpu_on_validate_mpidr(u64 mpidr, u32 *cpu) +{ + *cpu = mpidr & MPIDR_AFF0; + + if (mpidr & ~MPIDR_AFF0) + return ARM_PSCI_RET_INVAL; + + if (*cpu >= CONFIG_ARMV8_PSCI_NR_CPUS) + return ARM_PSCI_RET_INVAL; + + if (psci_state[*cpu] == PSCI_AFFINITY_LEVEL_ON) + return ARM_PSCI_RET_ALREADY_ON; + + if (psci_state[*cpu] == PSCI_AFFINITY_LEVEL_ON_PENDING) + return ARM_PSCI_RET_ON_PENDING; + + return ARM_PSCI_RET_SUCCESS; +} + +__secure static void psci_cpu_on_write_entry_point(const u32 cpu, u64 entry_point) +{ + const u64 ep = CONFIG_SPL_TEXT_BASE; + + /* Trampoline target */ + writeq(entry_point, CPU_RELEASE_ADDR); + /* RVBAR address HI */ + writel((u32)(ep >> 24) & 0xffff, + (void *)SRC_BASE_ADDR + SRC_GPR(cpu * 2)); + /* RVBAR address LO */ + writel((u32)(ep >> 2) & 0x3fffff, + (void *)SRC_BASE_ADDR + SRC_GPR(cpu * 2 + 1)); +} + +__secure static void psci_cpu_on_power_on(const u32 cpu) +{ + int i; + + clrbits_le32((void *)GPC_BASE_ADDR + GPC_LPCR_A53_AD, EN_Cn_WFI_PDN(cpu)); + clrbits_le32((void *)SRC_BASE_ADDR + SRC_A53RCR1, A53_COREn_ENABLE(cpu)); + setbits_le32((void *)GPC_BASE_ADDR + GPC_PGC_nCTRL(cpu), PGC_PCR); + setbits_le32((void *)GPC_BASE_ADDR + GPC_CPU_PGC_SW_PUP_REQ, COREn_A53_SW_PUP_REQ(cpu)); + + /* If we fail here, the core gets power cycled, hang is OK */ + while (readl(GPC_BASE_ADDR + GPC_CPU_PGC_SW_PUP_REQ) & COREn_A53_SW_PUP_REQ(cpu)) + ; + + clrbits_le32((void *)GPC_BASE_ADDR + GPC_PGC_nCTRL(cpu), PGC_PCR); + setbits_le32((void *)SRC_BASE_ADDR + SRC_A53RCR1, A53_COREn_ENABLE(cpu)); + + /* Give the core a bit of time to boot and start executing code */ + for (i = 0; i < 100000; i++) + asm volatile("nop"); +} + +__secure static void psci_cpu_on_power_off(const u32 cpu) +{ + setbits_le32((void *)GPC_BASE_ADDR + GPC_LPCR_A53_AD, EN_Cn_WFI_PDN(cpu)); + setbits_le32((void *)GPC_BASE_ADDR + GPC_PGC_nCTRL(cpu), PGC_PCR); +} + +/* + * Common PSCI code + */ +/* Return supported PSCI version */ +__secure u32 psci_version(void) +{ + return ARM_PSCI_VER_1_0; +} + +/* + * 64bit PSCI code + */ +__secure s32 psci_cpu_on_64(u32 __always_unused function_id, u64 mpidr, + u64 entry_point_address, u64 context_id) +{ + u32 cpu = 0; + int ret; + + ret = psci_cpu_on_validate_mpidr(mpidr, &cpu); + if (ret != ARM_PSCI_RET_SUCCESS) + return ret; + + psci_cpu_on_write_entry_point(cpu, entry_point_address); + + psci_set_state(cpu, PSCI_AFFINITY_LEVEL_ON); + + psci_cpu_on_power_on(cpu); + + smp_kick_all_cpus(); + + return ARM_PSCI_RET_SUCCESS; +} + +__secure s32 psci_affinity_info_64(u32 __always_unused function_id, + u64 target_affinity, u32 lowest_affinity_level) +{ + u32 cpu = target_affinity & MPIDR_AFF0; + + if (lowest_affinity_level > 0) + return ARM_PSCI_RET_INVAL; + + if (target_affinity & ~MPIDR_AFF0) + return ARM_PSCI_RET_INVAL; + + if (cpu >= CONFIG_ARMV8_PSCI_NR_CPUS) + return ARM_PSCI_RET_INVAL; + + return psci_state[cpu]; +} + +__secure s32 psci_system_reset2_64(u32 __always_unused function_id, + u32 reset_type, u64 cookie) +{ + psci_system_reset(); + return 0; /* Not reached */ +} + +/* + * 32bit PSCI code + */ +__secure s32 psci_affinity_info(u32 __always_unused function_id, + u32 target_affinity, u32 lowest_affinity_level) +{ + return psci_affinity_info_64(function_id, target_affinity, lowest_affinity_level); +} + +__secure s32 psci_cpu_on(u32 __always_unused function_id, u32 mpidr, + u32 entry_point_address, u32 context_id) +{ + return psci_cpu_on_64(function_id, mpidr, entry_point_address, context_id); +} + +__secure s32 psci_cpu_off(void) +{ + u32 cpu = psci_get_cpu_id(); + + psci_cpu_on_power_off(cpu); + psci_set_state(cpu, PSCI_AFFINITY_LEVEL_OFF); + + while (1) + wfi(); +} + +__secure u32 psci_migrate_info_type(void) +{ + /* Trusted OS is either not present or does not require migration */ + return 2; +} + +__secure void psci_system_reset(void) +{ + struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR; + bool ext_reset = true; + + u16 wcr = WCR_WDE; + + if (ext_reset) + wcr |= WCR_SRS; /* do not assert internal reset */ + else + wcr |= WCR_WDA; /* do not assert external reset */ + + /* Write 3 times to ensure it works, due to IMX6Q errata ERR004346 */ + writew(wcr, &wdog->wcr); + writew(wcr, &wdog->wcr); + writew(wcr, &wdog->wcr); + + while (1) + wfi(); +} + +__secure void psci_system_off(void) +{ + writel(SNVS_LPCR_TOP | SNVS_LPCR_DP_EN | SNVS_LPCR_SRTC_ENV, + SNVS_BASE_ADDR + SNVS_LPCR); + + while (1) + wfi(); +} + +/* + * PSCI jump table + */ +__secure s32 psci_features(u32 __always_unused function_id, u32 psci_fid) +{ + switch (psci_fid) { + case ARM_PSCI_0_2_FN_PSCI_VERSION: + case ARM_PSCI_0_2_FN_CPU_OFF: + case ARM_PSCI_0_2_FN_CPU_ON: + case ARM_PSCI_0_2_FN_AFFINITY_INFO: + case ARM_PSCI_0_2_FN_MIGRATE_INFO_TYPE: + case ARM_PSCI_0_2_FN_SYSTEM_OFF: + case ARM_PSCI_0_2_FN_SYSTEM_RESET: + case ARM_PSCI_0_2_FN64_CPU_ON: + case ARM_PSCI_0_2_FN64_AFFINITY_INFO: + + /* PSCI 1.0 interface */ + case ARM_PSCI_1_0_FN_PSCI_FEATURES: + + /* PSCI 1.1 interface */ + case ARM_PSCI_1_1_FN64_SYSTEM_RESET2: + return 0x0; + + /* + * Not implemented: + * ARM_PSCI_0_2_FN_CPU_SUSPEND + * ARM_PSCI_1_0_FN_CPU_FREEZE + * ARM_PSCI_1_0_FN_CPU_DEFAULT_SUSPEND + * ARM_PSCI_1_0_FN_NODE_HW_STATE + * ARM_PSCI_1_0_FN_SYSTEM_SUSPEND + * ARM_PSCI_1_0_FN_SET_SUSPEND_MODE + * ARM_PSCI_1_0_FN_STAT_RESIDENCY + * ARM_PSCI_1_0_FN_STAT_COUNT + * ARM_PSCI_0_2_FN64_CPU_SUSPEND + * ARM_PSCI_1_0_FN64_CPU_DEFAULT_SUSPEND + * ARM_PSCI_1_0_FN64_NODE_HW_STATE + * ARM_PSCI_1_0_FN64_SYSTEM_SUSPEND + * ARM_PSCI_1_0_FN64_STAT_RESIDENCY + * ARM_PSCI_1_0_FN64_STAT_COUNT + */ + + /* Not required, ARM_PSCI_0_2_FN_MIGRATE_INFO_TYPE returns 2 */ + case ARM_PSCI_0_2_FN_MIGRATE: + case ARM_PSCI_0_2_FN64_MIGRATE: + /* Not required */ + case ARM_PSCI_0_2_FN_MIGRATE_INFO_UP_CPU: + case ARM_PSCI_0_2_FN64_MIGRATE_INFO_UP_CPU: + default: + return ARM_PSCI_RET_NI; + } +} diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c index 8050406613..df865e997d 100644 --- a/arch/arm/mach-imx/imx8m/soc.c +++ b/arch/arm/mach-imx/imx8m/soc.c @@ -100,6 +100,12 @@ void set_wdog_reset(struct wdog_regs *wdog) setbits_le16(&wdog->wcr, WDOG_WDT_MASK | WDOG_WDZST_MASK); } +#ifdef CONFIG_ARMV8_PSCI +#define PTE_MAP_NS PTE_BLOCK_NS +#else +#define PTE_MAP_NS 0 +#endif + static struct mm_region imx8m_mem_map[] = { { /* ROM */ @@ -122,7 +128,7 @@ static struct mm_region imx8m_mem_map[] = { .phys = 0x180000UL, .size = 0x8000UL, .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | - PTE_BLOCK_OUTER_SHARE + PTE_BLOCK_OUTER_SHARE | PTE_MAP_NS }, { /* TCM */ .virt = 0x7C0000UL, @@ -130,14 +136,14 @@ static struct mm_region imx8m_mem_map[] = { .size = 0x80000UL, .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | - PTE_BLOCK_PXN | PTE_BLOCK_UXN + PTE_BLOCK_PXN | PTE_BLOCK_UXN | PTE_MAP_NS }, { /* OCRAM */ .virt = 0x900000UL, .phys = 0x900000UL, .size = 0x200000UL, .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | - PTE_BLOCK_OUTER_SHARE + PTE_BLOCK_OUTER_SHARE | PTE_MAP_NS }, { /* AIPS */ .virt = 0xB00000UL, @@ -152,7 +158,7 @@ static struct mm_region imx8m_mem_map[] = { .phys = 0x40000000UL, .size = PHYS_SDRAM_SIZE, .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | - PTE_BLOCK_OUTER_SHARE + PTE_BLOCK_OUTER_SHARE | PTE_MAP_NS #ifdef PHYS_SDRAM_2_SIZE }, { /* DRAM2 */ @@ -160,7 +166,7 @@ static struct mm_region imx8m_mem_map[] = { .phys = 0x100000000UL, .size = PHYS_SDRAM_2_SIZE, .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | - PTE_BLOCK_OUTER_SHARE + PTE_BLOCK_OUTER_SHARE | PTE_MAP_NS #endif }, { /* empty entrie to split table entry 5 if needed when TEEs are used */ @@ -238,7 +244,7 @@ int dram_init(void) return ret; /* rom_pointer[1] contains the size of TEE occupies */ - if (rom_pointer[1]) + if (!IS_ENABLED(CONFIG_ARMV8_PSCI) && rom_pointer[1]) gd->ram_size = sdram_size - rom_pointer[1]; else gd->ram_size = sdram_size; @@ -267,7 +273,7 @@ int dram_init_banksize(void) } gd->bd->bi_dram[bank].start = PHYS_SDRAM; - if (rom_pointer[1]) { + if (!IS_ENABLED(CONFIG_ARMV8_PSCI) && rom_pointer[1]) { phys_addr_t optee_start = (phys_addr_t)rom_pointer[0]; phys_size_t optee_size = (size_t)rom_pointer[1]; @@ -312,7 +318,7 @@ phys_size_t get_effective_memsize(void) sdram_b1_size = sdram_size; } - if (rom_pointer[1]) { + if (!IS_ENABLED(CONFIG_ARMV8_PSCI) && rom_pointer[1]) { /* We will relocate u-boot to Top of dram1. Tee position has two cases: * 1. At the top of dram1, Then return the size removed optee size. * 2. In the middle of dram1, return the size of dram1. @@ -344,7 +350,8 @@ phys_size_t board_get_usable_ram_top(phys_size_t total_size) * rom_pointer[1] stores the size TEE uses. * We need to reserve the memory region for TEE. */ - if (rom_pointer[0] && rom_pointer[1] && top_addr > rom_pointer[0]) + if (!IS_ENABLED(CONFIG_ARMV8_PSCI) && rom_pointer[0] && + rom_pointer[1] && top_addr > rom_pointer[0]) top_addr = rom_pointer[0]; return top_addr; @@ -554,6 +561,29 @@ static void imx8m_setup_snvs(void) writel(0xffffffff, SNVS_BASE_ADDR + SNVS_LPSR); } +static void imx8m_setup_csu_tzasc(void) +{ + const uintptr_t tzasc_base[4] = { + 0x301f0000, 0x301f0000, 0x301f0000, 0x301f0000 + }; + int i, j; + + if (!IS_ENABLED(CONFIG_ARMV8_PSCI)) + return; + + /* CSU */ + for (i = 0; i < 64; i++) + writel(0x00ff00ff, (void *)CSU_BASE_ADDR + (4 * i)); + + /* TZASC */ + for (j = 0; j < 4; j++) { + writel(0x77777777, (void *)(tzasc_base[j])); + writel(0x77777777, (void *)(tzasc_base[j]) + 0x4); + for (i = 0; i <= 0x10; i += 4) + writel(0, (void *)(tzasc_base[j]) + 0x40 + i); + } +} + int arch_cpu_init(void) { struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR; @@ -606,6 +636,8 @@ int arch_cpu_init(void) imx8m_setup_snvs(); + imx8m_setup_csu_tzasc(); + return 0; } @@ -1610,4 +1642,9 @@ const struct rproc_att hostmap[] = { { 0x40000000, 0x40000000, 0x80000000 }, { /* sentinel */ } }; + +const struct rproc_att *imx_bootaux_get_hostmap(void) +{ + return hostmap; +} #endif diff --git a/arch/arm/mach-imx/imx_bootaux.c b/arch/arm/mach-imx/imx_bootaux.c index 8115bf40f1..888c53d690 100644 --- a/arch/arm/mach-imx/imx_bootaux.c +++ b/arch/arm/mach-imx/imx_bootaux.c @@ -15,17 +15,20 @@ #include <cpu_func.h> /* Just to avoid build error */ -#if CONFIG_IS_ENABLED(IMX8M) +#if IS_ENABLED(CONFIG_IMX8M) #define SRC_M4C_NON_SCLR_RST_MASK BIT(0) #define SRC_M4_ENABLE_MASK BIT(0) #define SRC_M4_REG_OFFSET 0 #endif -const __weak struct rproc_att hostmap[] = { }; +__weak const struct rproc_att *imx_bootaux_get_hostmap(void) +{ + return NULL; +} static const struct rproc_att *get_host_mapping(unsigned long auxcore) { - const struct rproc_att *mmap = hostmap; + const struct rproc_att *mmap = imx_bootaux_get_hostmap(); while (mmap && mmap->size) { if (mmap->da <= auxcore && @@ -106,7 +109,7 @@ int arch_auxiliary_core_up(u32 core_id, ulong addr) if (!pc) return CMD_RET_FAILURE; - if (!CONFIG_IS_ENABLED(ARM64)) + if (!IS_ENABLED(CONFIG_ARM64)) stack = 0x0; } else { /* @@ -128,7 +131,7 @@ int arch_auxiliary_core_up(u32 core_id, ulong addr) flush_dcache_all(); /* Enable M4 */ - if (CONFIG_IS_ENABLED(IMX8M)) { + if (IS_ENABLED(CONFIG_IMX8M)) { arm_smccc_smc(IMX_SIP_SRC, IMX_SIP_SRC_M4_START, 0, 0, 0, 0, 0, 0, NULL); } else { clrsetbits_le32(SRC_BASE_ADDR + SRC_M4_REG_OFFSET, @@ -143,7 +146,7 @@ int arch_auxiliary_core_check_up(u32 core_id) struct arm_smccc_res res; unsigned int val; - if (CONFIG_IS_ENABLED(IMX8M)) { + if (IS_ENABLED(CONFIG_IMX8M)) { arm_smccc_smc(IMX_SIP_SRC, IMX_SIP_SRC_M4_STARTED, 0, 0, 0, 0, 0, 0, &res); return res.a0; } diff --git a/arch/arm/mach-imx/lowlevel.S b/arch/arm/mach-imx/lowlevel.S deleted file mode 100644 index 158fdb7d87..0000000000 --- a/arch/arm/mach-imx/lowlevel.S +++ /dev/null @@ -1,22 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2019 NXP - */ - -#include <linux/linkage.h> - -ENTRY(lowlevel_init) - mrs x0, CurrentEL - cmp x0, #8 - b.eq 1f - ret -1: - msr daifclr, #4 - - /* set HCR_EL2.AMO to catch SERROR */ - mrs x0, hcr_el2 - orr x0, x0, #0x20 - msr hcr_el2, x0 - isb - ret -ENDPROC(lowlevel_init) diff --git a/arch/arm/mach-imx/mx7/clock.c b/arch/arm/mach-imx/mx7/clock.c index 88f6fe0274..4e232385af 100644 --- a/arch/arm/mach-imx/mx7/clock.c +++ b/arch/arm/mach-imx/mx7/clock.c @@ -502,7 +502,7 @@ unsigned int mxc_get_clock(enum mxc_clock clk) case MXC_IPG_CLK: return get_ipg_clk(); case MXC_I2C_CLK: - return get_root_clk(I2C1_CLK_ROOT); + return 60000000; case MXC_UART_CLK: return get_root_clk(UART1_CLK_ROOT); case MXC_CSPI_CLK: diff --git a/arch/arm/mach-imx/mx7/soc.c b/arch/arm/mach-imx/mx7/soc.c index 02af0d568f..689dbefe8e 100644 --- a/arch/arm/mach-imx/mx7/soc.c +++ b/arch/arm/mach-imx/mx7/soc.c @@ -224,6 +224,11 @@ const struct rproc_att hostmap[] = { { 0x80000000, 0x80000000, 0x60000000 }, /* DDRC */ { /* sentinel */ } }; + +const struct rproc_att *imx_bootaux_get_hostmap(void) +{ + return hostmap; +} #endif #if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) diff --git a/arch/arm/mach-imx/romapi.c b/arch/arm/mach-imx/romapi.c index c8accdb04d..b49e7f80a2 100644 --- a/arch/arm/mach-imx/romapi.c +++ b/arch/arm/mach-imx/romapi.c @@ -66,6 +66,9 @@ enum boot_device get_boot_device(void) case BT_DEV_TYPE_FLEXSPINOR: boot_dev = QSPI_BOOT; break; + case BT_DEV_TYPE_SPI_NOR: + boot_dev = SPI_NOR_BOOT; + break; case BT_DEV_TYPE_USB: boot_dev = boot_instance + USB_BOOT; break; |