diff options
| author | Ye Li <ye.li@nxp.com> | 2023-01-31 11:42:21 +0300 |
|---|---|---|
| committer | Stefano Babic <sbabic@denx.de> | 2023-03-29 21:15:42 +0300 |
| commit | 4e08a510d23e2e23c8a776ccea582d0acd75fd4d (patch) | |
| tree | 531df17303054600555777b003d5c86ac86f3295 /arch | |
| parent | e01d1b1e302f77bdad6d1f0c7a17c4edee1e7ebd (diff) | |
| download | u-boot-4e08a510d23e2e23c8a776ccea582d0acd75fd4d.tar.xz | |
imx: imx8ulp: Clear dividers in PLL3DIV_PFD registers
At present, in cgc1_pll3_init we don't set the pll3pfd div values,
just use the default 0. But on A1 part, ROM will set PLL3 pfd1div2
to 1 and pfd2div1 to 3.
This finally causes some clocks' rate decreased, for example USDHC.
So clear the PLL3DIV_PFD dividers to get correct rate.
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/mach-imx/imx8ulp/cgc.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/arch/arm/mach-imx/imx8ulp/cgc.c b/arch/arm/mach-imx/imx8ulp/cgc.c index d240abaee4..104109e693 100644 --- a/arch/arm/mach-imx/imx8ulp/cgc.c +++ b/arch/arm/mach-imx/imx8ulp/cgc.c @@ -169,6 +169,9 @@ void cgc1_pll3_init(ulong freq) while (!(readl(&cgc1_regs->pll3pfdcfg) & BIT(30))) ; + clrbits_le32(&cgc1_regs->pll3div_pfd0, 0x3f3f3f3f); + clrbits_le32(&cgc1_regs->pll3div_pfd1, 0x3f3f3f3f); + clrbits_le32(&cgc1_regs->pll3div_pfd0, BIT(7)); clrbits_le32(&cgc1_regs->pll3div_pfd0, BIT(15)); clrbits_le32(&cgc1_regs->pll3div_pfd0, BIT(23)); |