Merge https://source.denx.de/u-boot/custodians/u-boot-riscv

5 files changed, 49 insertions, 15 deletions

diff --git a/arch/riscv/cpu/ax25/Makefile b/arch/riscv/cpu/ax25/Makefile
index 318baccb09..35a1a2fb83 100644
--- a/arch/riscv/cpu/ax25/Makefile
+++ b/arch/riscv/cpu/ax25/Makefile
@@ -5,3 +5,4 @@
 
 obj-y	:= cpu.o
 obj-y	+= cache.o
+obj-y	+= spl.o
diff --git a/arch/riscv/cpu/ax25/cpu.c b/arch/riscv/cpu/ax25/cpu.c
index c4c2de2ef0..a46674f7c2 100644
--- a/arch/riscv/cpu/ax25/cpu.c
+++ b/arch/riscv/cpu/ax25/cpu.c
@@ -12,18 +12,20 @@
 #include <asm/csr.h>
 
 #define CSR_MCACHE_CTL	0x7ca
-#define CSR_MMISC_CTL	0x7d0
-#define CSR_MARCHID		0xf12
+#define CSR_MMISC_CTL		0x7d0
+#define CSR_MARCHID			0xf12
 
 #define V5_MCACHE_CTL_IC_EN_OFFSET      0
 #define V5_MCACHE_CTL_DC_EN_OFFSET      1
-#define V5_MCACHE_CTL_DC_COHEN_OFFSET	19
+#define V5_MCACHE_CTL_CCTL_SUEN_OFFSET	8
+#define V5_MCACHE_CTL_DC_COHEN_OFFSET		19
 #define V5_MCACHE_CTL_DC_COHSTA_OFFSET	20
 
-#define V5_MCACHE_CTL_IC_EN		BIT(V5_MCACHE_CTL_IC_EN_OFFSET)
-#define V5_MCACHE_CTL_DC_EN				BIT(V5_MCACHE_CTL_DC_EN_OFFSET)
-#define V5_MCACHE_CTL_DC_COHEN_EN       BIT(V5_MCACHE_CTL_DC_COHEN_OFFSET)
-#define V5_MCACHE_CTL_DC_COHSTA_EN      BIT(V5_MCACHE_CTL_DC_COHSTA_OFFSET)
+#define V5_MCACHE_CTL_IC_EN					BIT(V5_MCACHE_CTL_IC_EN_OFFSET)
+#define V5_MCACHE_CTL_DC_EN					BIT(V5_MCACHE_CTL_DC_EN_OFFSET)
+#define V5_MCACHE_CTL_CCTL_SUEN			BIT(V5_MCACHE_CTL_CCTL_SUEN_OFFSET)
+#define V5_MCACHE_CTL_DC_COHEN_EN   BIT(V5_MCACHE_CTL_DC_COHEN_OFFSET)
+#define V5_MCACHE_CTL_DC_COHSTA_EN  BIT(V5_MCACHE_CTL_DC_COHSTA_OFFSET)
 
 
 /*
@@ -55,6 +57,8 @@ void harts_early_init(void)
 			mcache_ctl_val |= V5_MCACHE_CTL_IC_EN;
 		if (!(mcache_ctl_val & V5_MCACHE_CTL_DC_EN))
 			mcache_ctl_val |= V5_MCACHE_CTL_DC_EN;
+		if (!(mcache_ctl_val & V5_MCACHE_CTL_CCTL_SUEN))
+			mcache_ctl_val |= V5_MCACHE_CTL_CCTL_SUEN;
 		csr_write(CSR_MCACHE_CTL, mcache_ctl_val);
 
 		/*
diff --git a/arch/riscv/cpu/ax25/spl.c b/arch/riscv/cpu/ax25/spl.c
new file mode 100644
index 0000000000..413849043b
--- /dev/null
+++ b/arch/riscv/cpu/ax25/spl.c
@@ -0,0 +1,27 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2023 Andes Technology Corporation
+ * Rick Chen, Andes Technology Corporation <rick@andestech.com>
+ */
+#include <common.h>
+#include <cpu_func.h>
+#include <hang.h>
+#include <init.h>
+#include <log.h>
+#include <spl.h>
+#include <asm/global_data.h>
+#include <asm/system.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if CONFIG_IS_ENABLED(RAM_SUPPORT)
+struct legacy_img_hdr *spl_get_load_buffer(ssize_t offset, size_t size)
+{
+	return (void *)(CONFIG_SPL_LOAD_FIT_ADDRESS + offset);
+}
+
+void *board_spl_fit_buffer_addr(ulong fit_size, int sectors, int bl_len)
+{
+	return spl_get_load_buffer(0, sectors * bl_len);
+}
+#endif
diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c
index d34c8efce0..e1ed4ec01d 100644
--- a/arch/riscv/cpu/cpu.c
+++ b/arch/riscv/cpu/cpu.c
@@ -33,7 +33,9 @@ u32 available_harts_lock = 1;
 
 static inline bool supports_extension(char ext)
 {
-#ifdef CONFIG_CPU
+#if CONFIG_IS_ENABLED(RISCV_MMODE)
+	return csr_read(CSR_MISA) & (1 << (ext - 'a'));
+#elif CONFIG_CPU
 	struct udevice *dev;
 	char desc[32];
 	int i;
@@ -58,13 +60,9 @@ static inline bool supports_extension(char ext)
 
 	return false;
 #else  /* !CONFIG_CPU */
-#if CONFIG_IS_ENABLED(RISCV_MMODE)
-	return csr_read(CSR_MISA) & (1 << (ext - 'a'));
-#else  /* !CONFIG_IS_ENABLED(RISCV_MMODE) */
 #warning "There is no way to determine the available extensions in S-mode."
 #warning "Please convert your board to use the RISC-V CPU driver."
 	return false;
-#endif /* CONFIG_IS_ENABLED(RISCV_MMODE) */
 #endif /* CONFIG_CPU */
 }
 
@@ -112,12 +110,14 @@ int riscv_cpu_setup(void *ctx, struct event *event)
 		 * Enable perf counters for cycle, time,
 		 * and instret counters only
 		 */
+		if (supports_extension('u')) {
 #ifdef CONFIG_RISCV_PRIV_1_9
-		csr_write(CSR_MSCOUNTEREN, GENMASK(2, 0));
-		csr_write(CSR_MUCOUNTEREN, GENMASK(2, 0));
+			csr_write(CSR_MSCOUNTEREN, GENMASK(2, 0));
+			csr_write(CSR_MUCOUNTEREN, GENMASK(2, 0));
 #else
-		csr_write(CSR_MCOUNTEREN, GENMASK(2, 0));
+			csr_write(CSR_MCOUNTEREN, GENMASK(2, 0));
 #endif
+		}
 
 		/* Disable paging */
 		if (supports_extension('s'))
diff --git a/arch/riscv/lib/memcpy.S b/arch/riscv/lib/memcpy.S
index 00672c19ad..9884077c93 100644
--- a/arch/riscv/lib/memcpy.S
+++ b/arch/riscv/lib/memcpy.S
@@ -9,6 +9,7 @@
 /* void *memcpy(void *, const void *, size_t) */
 ENTRY(__memcpy)
 WEAK(memcpy)
+	beq	a0, a1, .copy_end
 	/* Save for return value */
 	mv	t6, a0
 
@@ -121,6 +122,7 @@ WEAK(memcpy)
 2:
 
 	mv	a0, t6
+.copy_end:
 	ret
 
 .Lmisaligned_word_copy: