Merge https://source.denx.de/u-boot/custodians/u-boot-riscv

- Set up per-hart stack before any function call
- Sync visionfive2 board DTS with Linux
- Define cache line size for USB 3.0 driver for RISC-V CPU

5 files changed, 41 insertions, 20 deletions

diff --git a/arch/riscv/cpu/generic/Kconfig b/arch/riscv/cpu/generic/Kconfig
index 897765c3c6..2baba22992 100644
--- a/arch/riscv/cpu/generic/Kconfig
+++ b/arch/riscv/cpu/generic/Kconfig
@@ -6,6 +6,7 @@ config GENERIC_RISCV
 	bool
 	select BINMAN if SPL
 	select ARCH_EARLY_INIT_R
+	select SYS_CACHE_SHIFT_6
 	imply CPU
 	imply CPU_RISCV
 	imply RISCV_TIMER if (RISCV_SMODE || SPL_RISCV_SMODE)
diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S
index dad22bfea8..59d58a5a57 100644
--- a/arch/riscv/cpu/start.S
+++ b/arch/riscv/cpu/start.S
@@ -91,16 +91,35 @@ _start:
  * Set stackpointer in internal/ex RAM to call board_init_f
  */
 call_board_init_f:
-	li	t0, -16
 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_STACK)
-	li	t1, CONFIG_SPL_STACK
+	li	t0, CONFIG_SPL_STACK
 #else
-	li	t1, SYS_INIT_SP_ADDR
+	li	t0, SYS_INIT_SP_ADDR
 #endif
-	and	sp, t1, t0		/* force 16 byte alignment */
+	and	t0, t0, -16		/* force 16 byte alignment */
+
+	/* setup stack */
+#if CONFIG_IS_ENABLED(SMP)
+	/* tp: hart id */
+	slli	t1, tp, CONFIG_STACK_SIZE_SHIFT
+	sub	sp, t0, t1
+#else
+	mv	sp, t0
+#endif
+/*
+ * Now sp points to the right stack belonging to current CPU.
+ * It's essential before any function call, otherwise, we get data-race.
+ */
 
 call_board_init_f_0:
-	mv	a0, sp
+	/* find top of reserve space */
+#if CONFIG_IS_ENABLED(SMP)
+	li	t1, CONFIG_NR_CPUS
+#else
+	li	t1, 1
+#endif
+	slli	t1, t1, CONFIG_STACK_SIZE_SHIFT
+	sub	a0, t0, t1		/* t1 -> size of all CPU stacks */
 	jal	board_init_f_alloc_reserve
 
 	/*
@@ -109,14 +128,6 @@ call_board_init_f_0:
 	 */
 	mv	s0, a0
 
-	/* setup stack */
-#if CONFIG_IS_ENABLED(SMP)
-	/* tp: hart id */
-	slli	t0, tp, CONFIG_STACK_SIZE_SHIFT
-	sub	sp, a0, t0
-#else
-	mv	sp, a0
-#endif
 
 	/* Configure proprietary settings and customized CSRs of harts */
 call_harts_early_init:
diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
index 710b082766..b90e7f8995 100644
--- a/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
+++ b/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
@@ -313,9 +313,9 @@
 			  <&syscrg JH7110_SYSCLK_BUS_ROOT>,
 			  <&syscrg JH7110_SYSCLK_PERH_ROOT>,
 			  <&syscrg JH7110_SYSCLK_QSPI_REF>;
-	assigned-clock-parents = <&syscrg JH7110_SYSCLK_PLL0_OUT>,
-				 <&syscrg JH7110_SYSCLK_PLL2_OUT>,
-				 <&syscrg JH7110_SYSCLK_PLL2_OUT>,
+	assigned-clock-parents = <&pllclk JH7110_SYSCLK_PLL0_OUT>,
+				 <&pllclk JH7110_SYSCLK_PLL2_OUT>,
+				 <&pllclk JH7110_SYSCLK_PLL2_OUT>,
 				 <&syscrg JH7110_SYSCLK_QSPI_REF_SRC>;
 	assigned-clock-rates = <0>, <0>, <0>, <0>;
 };
diff --git a/arch/riscv/dts/jh7110-u-boot.dtsi b/arch/riscv/dts/jh7110-u-boot.dtsi
index c22119518c..2f560e7296 100644
--- a/arch/riscv/dts/jh7110-u-boot.dtsi
+++ b/arch/riscv/dts/jh7110-u-boot.dtsi
@@ -83,7 +83,6 @@
 
 &syscrg {
 	bootph-pre-ram;
-	starfive,sys-syscon = <&sys_syscon>;
 };
 
 &stgcrg {
diff --git a/arch/riscv/dts/jh7110.dtsi b/arch/riscv/dts/jh7110.dtsi
index 58e332e9d7..825fbb7198 100644
--- a/arch/riscv/dts/jh7110.dtsi
+++ b/arch/riscv/dts/jh7110.dtsi
@@ -487,19 +487,29 @@
 				 <&gmac1_rgmii_rxin>,
 				 <&i2stx_bclk_ext>, <&i2stx_lrck_ext>,
 				 <&i2srx_bclk_ext>, <&i2srx_lrck_ext>,
-				 <&tdm_ext>, <&mclk_ext>;
+				 <&tdm_ext>, <&mclk_ext>,
+				 <&pllclk JH7110_SYSCLK_PLL0_OUT>,
+				 <&pllclk JH7110_SYSCLK_PLL1_OUT>,
+				 <&pllclk JH7110_SYSCLK_PLL2_OUT>;
 			clock-names = "osc", "gmac1_rmii_refin",
 				      "gmac1_rgmii_rxin",
 				      "i2stx_bclk_ext", "i2stx_lrck_ext",
 				      "i2srx_bclk_ext", "i2srx_lrck_ext",
-				      "tdm_ext", "mclk_ext";
+				      "tdm_ext", "mclk_ext",
+				      "pll0_out", "pll1_out", "pll2_out";
 			#clock-cells = <1>;
 			#reset-cells = <1>;
 		};
 
 		sys_syscon: sys_syscon@13030000 {
-			compatible = "starfive,jh7110-sys-syscon","syscon";
+			compatible = "starfive,jh7110-sys-syscon","syscon", "simple-mfd";
 			reg = <0x0 0x13030000 0x0 0x1000>;
+
+			pllclk: clock-controller {
+				compatible = "starfive,jh7110-pll";
+				clocks = <&osc>;
+				#clock-cells = <1>;
+			};
 		};
 
 		sysgpio: pinctrl@13040000 {