diff options
| author | Marek Vasut <marex@denx.de> | 2023-03-06 17:53:53 +0300 |
|---|---|---|
| committer | Stefano Babic <sbabic@denx.de> | 2023-03-30 14:51:33 +0300 |
| commit | 599474120a089924aaa502b701600b2fe4b6270c (patch) | |
| tree | 39700fc6ed88f636f901847b6c163ddc64065d04 /arch | |
| parent | c7ea9612df0f89613a37ebe44ee2f48afc3493d3 (diff) | |
| download | u-boot-599474120a089924aaa502b701600b2fe4b6270c.tar.xz | |
arm64: imx8mp: Drop EQoS GPR[1] board workaround
The EQoS interface mode is now configured in common board_interface_eth_init()
and called by EQoS MAC driver when appropriate. Drop the board side duplicates
if the same functionality.
Signed-off-by: Marek Vasut <marex@denx.de>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/include/asm/arch-imx8m/clock.h | 1 | ||||
| -rw-r--r-- | arch/arm/mach-imx/imx8m/clock_imx8mm.c | 47 |
2 files changed, 0 insertions, 48 deletions
diff --git a/arch/arm/include/asm/arch-imx8m/clock.h b/arch/arm/include/asm/arch-imx8m/clock.h index e4433763bc..a861cd6db3 100644 --- a/arch/arm/include/asm/arch-imx8m/clock.h +++ b/arch/arm/include/asm/arch-imx8m/clock.h @@ -276,5 +276,4 @@ int set_clk_qspi(void); void enable_ocotp_clk(unsigned char enable); int enable_i2c_clk(unsigned char enable, unsigned int i2c_num); int set_clk_enet(enum enet_freq type); -int set_clk_eqos(enum enet_freq type); void hab_caam_clock_enable(unsigned char enable); diff --git a/arch/arm/mach-imx/imx8m/clock_imx8mm.c b/arch/arm/mach-imx/imx8m/clock_imx8mm.c index 22e954b462..76f6c5541b 100644 --- a/arch/arm/mach-imx/imx8m/clock_imx8mm.c +++ b/arch/arm/mach-imx/imx8m/clock_imx8mm.c @@ -827,53 +827,6 @@ u32 mxc_get_clock(enum mxc_clock clk) } #if defined(CONFIG_IMX8MP) && defined(CONFIG_DWC_ETH_QOS) -int set_clk_eqos(enum enet_freq type) -{ - u32 target; - u32 enet1_ref; - - switch (type) { - case ENET_125MHZ: - enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK; - break; - case ENET_50MHZ: - enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK; - break; - case ENET_25MHZ: - enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK; - break; - default: - return -EINVAL; - } - - /* disable the clock first */ - clock_enable(CCGR_QOS_ETHENET, 0); - clock_enable(CCGR_SDMA2, 0); - - /* set enet axi clock 266Mhz */ - target = CLK_ROOT_ON | ENET_AXI_CLK_ROOT_FROM_SYS1_PLL_266M | - CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) | - CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1); - clock_set_target_val(ENET_AXI_CLK_ROOT, target); - - target = CLK_ROOT_ON | enet1_ref | - CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) | - CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1); - clock_set_target_val(ENET_QOS_CLK_ROOT, target); - - target = CLK_ROOT_ON | - ENET1_TIME_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK | - CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) | - CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4); - clock_set_target_val(ENET_QOS_TIMER_CLK_ROOT, target); - - /* enable clock */ - clock_enable(CCGR_QOS_ETHENET, 1); - clock_enable(CCGR_SDMA2, 1); - - return 0; -} - static int imx8mp_eqos_interface_init(struct udevice *dev, phy_interface_t interface_type) { |