diff options
| author | Jonas Karlman <jonas@kwiboo.se> | 2023-08-04 12:33:59 +0300 |
|---|---|---|
| committer | Kever Yang <kever.yang@rock-chips.com> | 2023-08-12 05:35:35 +0300 |
| commit | 6da8400d7ae986ef2a8e0ddb4f39907c6c0666f1 (patch) | |
| tree | 9d3c048a08ce7d74434eedc808996281387cc564 /arch | |
| parent | acb9812034850ae0d737a767b392b9cd097f3606 (diff) | |
| download | u-boot-6da8400d7ae986ef2a8e0ddb4f39907c6c0666f1.tar.xz | |
clk: rockchip: rk3568: Fix mask for clk_cpll_div_25m_div
The field for clk_cpll_div_25m_div in CRU_CLKSEL_CON81 is 6 bits wide,
not 5 bits wide as currently defined in CPLL_25M_DIV_MASK.
Fix this and the assert so that CPLL_25M can be assigned a 25 MHz rate.
Fixes: 4a262feba3a5 ("rockchip: rk3568: add clock driver")
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/include/asm/arch-rockchip/cru_rk3568.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3568.h b/arch/arm/include/asm/arch-rockchip/cru_rk3568.h index 76f1ad5510..9c7ddd751f 100644 --- a/arch/arm/include/asm/arch-rockchip/cru_rk3568.h +++ b/arch/arm/include/asm/arch-rockchip/cru_rk3568.h @@ -495,7 +495,7 @@ enum { /* CRU_CLK_SEL81_CON */ CPLL_25M_DIV_SHIFT = 8, - CPLL_25M_DIV_MASK = 0x1f << CPLL_25M_DIV_SHIFT, + CPLL_25M_DIV_MASK = 0x3f << CPLL_25M_DIV_SHIFT, CPLL_50M_DIV_SHIFT = 0, CPLL_50M_DIV_MASK = 0x1f << CPLL_50M_DIV_SHIFT, |