diff options
| author | Nikita Shubin <n.shubin@yadro.com> | 2022-12-14 08:58:43 +0300 |
|---|---|---|
| committer | Leo Yu-Chi Liang <ycliang@andestech.com> | 2023-02-01 11:17:13 +0300 |
| commit | 81b56a55c21cf3de3e8faa4de3830a9036bf3e5c (patch) | |
| tree | 71fa3178e46d5e00e95163f4409cbdca4ee093b8 /arch | |
| parent | 73a3f5139182a0389d505bf29b0ad4bc29424cf8 (diff) | |
| download | u-boot-81b56a55c21cf3de3e8faa4de3830a9036bf3e5c.tar.xz | |
riscv: cpu: check U-Mode before counteren write
The Priv ISA states:
"In systems without U-mode, the mcounteren register should
not exist."
Check U-Mode is present in MISA before writing to counteren, otherwise
we endup with Illegal Instruction exception on systems without U-Mode.
Also make checking MISA default for M-Mode.
Signed-off-by: Nikita Shubin <n.shubin@yadro.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/riscv/cpu/cpu.c | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c index d34c8efce0..e1ed4ec01d 100644 --- a/arch/riscv/cpu/cpu.c +++ b/arch/riscv/cpu/cpu.c @@ -33,7 +33,9 @@ u32 available_harts_lock = 1; static inline bool supports_extension(char ext) { -#ifdef CONFIG_CPU +#if CONFIG_IS_ENABLED(RISCV_MMODE) + return csr_read(CSR_MISA) & (1 << (ext - 'a')); +#elif CONFIG_CPU struct udevice *dev; char desc[32]; int i; @@ -58,13 +60,9 @@ static inline bool supports_extension(char ext) return false; #else /* !CONFIG_CPU */ -#if CONFIG_IS_ENABLED(RISCV_MMODE) - return csr_read(CSR_MISA) & (1 << (ext - 'a')); -#else /* !CONFIG_IS_ENABLED(RISCV_MMODE) */ #warning "There is no way to determine the available extensions in S-mode." #warning "Please convert your board to use the RISC-V CPU driver." return false; -#endif /* CONFIG_IS_ENABLED(RISCV_MMODE) */ #endif /* CONFIG_CPU */ } @@ -112,12 +110,14 @@ int riscv_cpu_setup(void *ctx, struct event *event) * Enable perf counters for cycle, time, * and instret counters only */ + if (supports_extension('u')) { #ifdef CONFIG_RISCV_PRIV_1_9 - csr_write(CSR_MSCOUNTEREN, GENMASK(2, 0)); - csr_write(CSR_MUCOUNTEREN, GENMASK(2, 0)); + csr_write(CSR_MSCOUNTEREN, GENMASK(2, 0)); + csr_write(CSR_MUCOUNTEREN, GENMASK(2, 0)); #else - csr_write(CSR_MCOUNTEREN, GENMASK(2, 0)); + csr_write(CSR_MCOUNTEREN, GENMASK(2, 0)); #endif + } /* Disable paging */ if (supports_extension('s')) |