global: Move remaining CONFIG_*SRIO_* to CFG_*

The rest of the unmigrated CONFIG symbols in the SRIO namespace do not
easily transition to Kconfig. In many cases they likely should come from
the device tree instead. Move these out of CONFIG namespace and in to
CFG namespace.

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

2 files changed, 46 insertions, 46 deletions

diff --git a/arch/powerpc/cpu/mpc8xxx/law.c b/arch/powerpc/cpu/mpc8xxx/law.c
index dd274166c0..35409dc882 100644
--- a/arch/powerpc/cpu/mpc8xxx/law.c
+++ b/arch/powerpc/cpu/mpc8xxx/law.c
@@ -309,42 +309,42 @@ void init_laws(void)
 	 */
 	switch ((bootloc & FSL_CORENET_RCWSR6_BOOT_LOC) >> 23) {
 	case 0x0: /* boot from PCIE1 */
-		set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS,
+		set_next_law(CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS,
 				LAW_SIZE_1M,
 				LAW_TRGT_IF_PCIE_1);
-		set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS,
+		set_next_law(CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS,
 				LAW_SIZE_1M,
 				LAW_TRGT_IF_PCIE_1);
 		break;
 	case 0x1: /* boot from PCIE2 */
-		set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS,
+		set_next_law(CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS,
 				LAW_SIZE_1M,
 				LAW_TRGT_IF_PCIE_2);
-		set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS,
+		set_next_law(CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS,
 				LAW_SIZE_1M,
 				LAW_TRGT_IF_PCIE_2);
 		break;
 	case 0x2: /* boot from PCIE3 */
-		set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS,
+		set_next_law(CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS,
 				LAW_SIZE_1M,
 				LAW_TRGT_IF_PCIE_3);
-		set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS,
+		set_next_law(CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS,
 				LAW_SIZE_1M,
 				LAW_TRGT_IF_PCIE_3);
 		break;
 	case 0x8: /* boot from SRIO1 */
-		set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS,
+		set_next_law(CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS,
 				LAW_SIZE_1M,
 				LAW_TRGT_IF_RIO_1);
-		set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS,
+		set_next_law(CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS,
 				LAW_SIZE_1M,
 				LAW_TRGT_IF_RIO_1);
 		break;
 	case 0x9: /* boot from SRIO2 */
-		set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS,
+		set_next_law(CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS,
 				LAW_SIZE_1M,
 				LAW_TRGT_IF_RIO_2);
-		set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS,
+		set_next_law(CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS,
 				LAW_SIZE_1M,
 				LAW_TRGT_IF_RIO_2);
 		break;
diff --git a/arch/powerpc/cpu/mpc8xxx/srio.c b/arch/powerpc/cpu/mpc8xxx/srio.c
index c815d19384..dc1bc0db42 100644
--- a/arch/powerpc/cpu/mpc8xxx/srio.c
+++ b/arch/powerpc/cpu/mpc8xxx/srio.c
@@ -240,8 +240,8 @@ void srio_init(void)
 	devdisr = &gur->devdisr;
 #endif
 	if (is_serdes_configured(SRIO1)) {
-		set_next_law(CONFIG_SYS_SRIO1_MEM_PHYS,
-				law_size_bits(CONFIG_SYS_SRIO1_MEM_SIZE),
+		set_next_law(CFG_SYS_SRIO1_MEM_PHYS,
+				law_size_bits(CFG_SYS_SRIO1_MEM_SIZE),
 				LAW_TRGT_IF_RIO_1);
 		srio1_used = 1;
 #ifdef CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
@@ -256,8 +256,8 @@ void srio_init(void)
 
 #ifdef CONFIG_SRIO2
 	if (is_serdes_configured(SRIO2)) {
-		set_next_law(CONFIG_SYS_SRIO2_MEM_PHYS,
-				law_size_bits(CONFIG_SYS_SRIO2_MEM_SIZE),
+		set_next_law(CFG_SYS_SRIO2_MEM_PHYS,
+				law_size_bits(CFG_SYS_SRIO2_MEM_SIZE),
 				LAW_TRGT_IF_RIO_2);
 		srio2_used = 1;
 #ifdef CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
@@ -301,44 +301,44 @@ void srio_boot_master(int port)
 	/* configure inbound window for slave's u-boot image */
 	debug("SRIOBOOT - MASTER: Inbound window for slave's image; "
 			"Local = 0x%llx, Srio = 0x%llx, Size = 0x%x\n",
-			(u64)CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS,
-			(u64)CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1,
-			CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE);
+			(u64)CFG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS,
+			(u64)CFG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1,
+			CFG_SRIO_PCIE_BOOT_IMAGE_SIZE);
 	out_be32((void *)&srio->atmu.port[port - 1].inbw[0].riwtar,
-			CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS >> 12);
+			CFG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS >> 12);
 	out_be32((void *)&srio->atmu.port[port - 1].inbw[0].riwbar,
-			CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 >> 12);
+			CFG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 >> 12);
 	out_be32((void *)&srio->atmu.port[port - 1].inbw[0].riwar,
 			SRIO_IB_ATMU_AR
-			| atmu_size_mask(CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE));
+			| atmu_size_mask(CFG_SRIO_PCIE_BOOT_IMAGE_SIZE));
 
 	/* configure inbound window for slave's u-boot image */
 	debug("SRIOBOOT - MASTER: Inbound window for slave's image; "
 			"Local = 0x%llx, Srio = 0x%llx, Size = 0x%x\n",
-			(u64)CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS,
-			(u64)CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2,
-			CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE);
+			(u64)CFG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS,
+			(u64)CFG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2,
+			CFG_SRIO_PCIE_BOOT_IMAGE_SIZE);
 	out_be32((void *)&srio->atmu.port[port - 1].inbw[1].riwtar,
-			CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS >> 12);
+			CFG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS >> 12);
 	out_be32((void *)&srio->atmu.port[port - 1].inbw[1].riwbar,
-			CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 >> 12);
+			CFG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 >> 12);
 	out_be32((void *)&srio->atmu.port[port - 1].inbw[1].riwar,
 			SRIO_IB_ATMU_AR
-			| atmu_size_mask(CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE));
+			| atmu_size_mask(CFG_SRIO_PCIE_BOOT_IMAGE_SIZE));
 
 	/* configure inbound window for slave's ucode and ENV */
 	debug("SRIOBOOT - MASTER: Inbound window for slave's ucode and ENV; "
 			"Local = 0x%llx, Srio = 0x%llx, Size = 0x%x\n",
-			(u64)CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS,
-			(u64)CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS,
-			CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE);
+			(u64)CFG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS,
+			(u64)CFG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS,
+			CFG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE);
 	out_be32((void *)&srio->atmu.port[port - 1].inbw[2].riwtar,
-			CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS >> 12);
+			CFG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS >> 12);
 	out_be32((void *)&srio->atmu.port[port - 1].inbw[2].riwbar,
-			CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS >> 12);
+			CFG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS >> 12);
 	out_be32((void *)&srio->atmu.port[port - 1].inbw[2].riwar,
 			SRIO_IB_ATMU_AR
-			| atmu_size_mask(CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE));
+			| atmu_size_mask(CFG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE));
 }
 
 void srio_boot_master_release_slave(int port)
@@ -368,11 +368,11 @@ void srio_boot_master_release_slave(int port)
 			if (port - 1)
 				out_be32((void *)&srio->atmu.port[port - 1]
 					.outbw[1].rowbar,
-					CONFIG_SYS_SRIO2_MEM_PHYS >> 12);
+					CFG_SYS_SRIO2_MEM_PHYS >> 12);
 			else
 				out_be32((void *)&srio->atmu.port[port - 1]
 					.outbw[1].rowbar,
-					CONFIG_SYS_SRIO1_MEM_PHYS >> 12);
+					CFG_SYS_SRIO1_MEM_PHYS >> 12);
 			out_be32((void *)&srio->atmu.port[port - 1]
 					.outbw[1].rowar,
 					SRIO_OB_ATMU_AR_MAINT
@@ -390,12 +390,12 @@ void srio_boot_master_release_slave(int port)
 			if (port - 1)
 				out_be32((void *)&srio->atmu.port[port - 1]
 					.outbw[2].rowbar,
-					(CONFIG_SYS_SRIO2_MEM_PHYS
+					(CFG_SYS_SRIO2_MEM_PHYS
 					+ SRIO_MAINT_WIN_SIZE) >> 12);
 			else
 				out_be32((void *)&srio->atmu.port[port - 1]
 					.outbw[2].rowbar,
-					(CONFIG_SYS_SRIO1_MEM_PHYS
+					(CFG_SYS_SRIO1_MEM_PHYS
 					+ SRIO_MAINT_WIN_SIZE) >> 12);
 			out_be32((void *)&srio->atmu.port[port - 1]
 				.outbw[2].rowar,
@@ -407,10 +407,10 @@ void srio_boot_master_release_slave(int port)
 			 * by the maint-outbound window
 			 */
 			if (port - 1) {
-				out_be32((void *)CONFIG_SYS_SRIO2_MEM_VIRT
+				out_be32((void *)CFG_SYS_SRIO2_MEM_VIRT
 					+ SRIO_LCSBA1CSR_OFFSET,
 					SRIO_LCSBA1CSR);
-				while (in_be32((void *)CONFIG_SYS_SRIO2_MEM_VIRT
+				while (in_be32((void *)CFG_SYS_SRIO2_MEM_VIRT
 					+ SRIO_LCSBA1CSR_OFFSET)
 					!= SRIO_LCSBA1CSR)
 					;
@@ -418,15 +418,15 @@ void srio_boot_master_release_slave(int port)
 				 * And then set the BRR register
 				 * to release slave core
 				 */
-				out_be32((void *)CONFIG_SYS_SRIO2_MEM_VIRT
+				out_be32((void *)CFG_SYS_SRIO2_MEM_VIRT
 					+ SRIO_MAINT_WIN_SIZE
-					+ CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET,
-					CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK);
+					+ CFG_SRIO_PCIE_BOOT_BRR_OFFSET,
+					CFG_SRIO_PCIE_BOOT_RELEASE_MASK);
 			} else {
-				out_be32((void *)CONFIG_SYS_SRIO1_MEM_VIRT
+				out_be32((void *)CFG_SYS_SRIO1_MEM_VIRT
 					+ SRIO_LCSBA1CSR_OFFSET,
 					SRIO_LCSBA1CSR);
-				while (in_be32((void *)CONFIG_SYS_SRIO1_MEM_VIRT
+				while (in_be32((void *)CFG_SYS_SRIO1_MEM_VIRT
 					+ SRIO_LCSBA1CSR_OFFSET)
 					!= SRIO_LCSBA1CSR)
 					;
@@ -434,10 +434,10 @@ void srio_boot_master_release_slave(int port)
 				 * And then set the BRR register
 				 * to release slave core
 				 */
-				out_be32((void *)CONFIG_SYS_SRIO1_MEM_VIRT
+				out_be32((void *)CFG_SYS_SRIO1_MEM_VIRT
 					+ SRIO_MAINT_WIN_SIZE
-					+ CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET,
-					CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK);
+					+ CFG_SRIO_PCIE_BOOT_BRR_OFFSET,
+					CFG_SRIO_PCIE_BOOT_RELEASE_MASK);
 			}
 			debug("SRIOBOOT - MASTER: "
 					"Release slave successfully! Now the slave should start up!\n");