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| author | Michael Walle <michael@walle.cc> | 2020-06-01 22:53:29 +0300 |
|---|---|---|
| committer | Priyanka Jain <priyanka.jain@nxp.com> | 2020-07-27 11:46:27 +0300 |
| commit | b1c41231c43b0cc6719b93fe0e0e985b7abb7f5a (patch) | |
| tree | d5a151b6bbf222e5089fd2fbd4cb416c079b5ba6 /arch | |
| parent | 2eca7b97046e96e5cde4431b6635e0b4173b3e40 (diff) | |
| download | u-boot-b1c41231c43b0cc6719b93fe0e0e985b7abb7f5a.tar.xz | |
armv8: layerscape: fix alignment for spin table
Fix the alignment so it will match the comments. The spin table has to
be 8 byte aligned, so ".align 3" is enough.
Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/cpu/armv8/fsl-layerscape/spintable.S | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/spintable.S b/arch/arm/cpu/armv8/fsl-layerscape/spintable.S index ac9c622aee..a92f930e04 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/spintable.S +++ b/arch/arm/cpu/armv8/fsl-layerscape/spintable.S @@ -19,7 +19,7 @@ secondary_boot_addr: .ltorg /* Using 64 bit alignment since the spin table is accessed as data */ - .align 4 + .align 3 .global secondary_boot_code /* Secondary Boot Code starts here */ secondary_boot_code: @@ -144,7 +144,7 @@ ENDPROC(secondary_switch_to_el1) .ltorg /* 64 bit alignment for elements accessed as data */ - .align 4 + .align 3 .global __real_cntfrq __real_cntfrq: .quad COUNTER_FREQUENCY |