summaryrefslogtreecommitdiff
path: root/arch
diff options
context:
space:
mode:
authorTim Harvey <tharvey@gateworks.com>2022-11-30 20:42:51 +0300
committerTom Rini <trini@konsulko.com>2023-02-02 22:44:53 +0300
commitc3d9736d54e7504656577020e3608f01c8fa76d5 (patch)
tree29a4ad64ff2f7daf4e2304b42d4e77b8b848b74d /arch
parent01e7dd050fc90358c64d990e146c9b0f86d6d563 (diff)
downloadu-boot-c3d9736d54e7504656577020e3608f01c8fa76d5.tar.xz
board: gw_ventana: enable MV88E61XX DSA support
Add MV88E61XX DSA support: - update dt to provide internal MDIO bus and port handles. U-Boot requires a more restrictive subset of the dt bindings required by Linux for the sake of simplifying code - update defconfig to remove old driver and enable new one - replace mv88e61xx_hw_reset weak override with board_phy_config support for register configuration that is outside the scope of the DSA driver Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Fabio Estevam <festevam@denx.de> Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/dts/imx6qdl-gw5904.dtsi36
1 files changed, 35 insertions, 1 deletions
diff --git a/arch/arm/dts/imx6qdl-gw5904.dtsi b/arch/arm/dts/imx6qdl-gw5904.dtsi
index 612b6e068e..ea54922f15 100644
--- a/arch/arm/dts/imx6qdl-gw5904.dtsi
+++ b/arch/arm/dts/imx6qdl-gw5904.dtsi
@@ -212,6 +212,27 @@
compatible = "marvell,mv88e6085";
reg = <0>;
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ sw_phy0: ethernet-phy@0 {
+ reg = <0x0>;
+ };
+
+ sw_phy1: ethernet-phy@1 {
+ reg = <0x1>;
+ };
+
+ sw_phy2: ethernet-phy@2 {
+ reg = <0x2>;
+ };
+
+ sw_phy3: ethernet-phy@3 {
+ reg = <0x3>;
+ };
+ };
+
ports {
#address-cells = <1>;
#size-cells = <0>;
@@ -219,27 +240,40 @@
port@0 {
reg = <0>;
label = "lan4";
+ phy-handle = <&sw_phy0>;
+ phy-mode = "internal";
};
port@1 {
reg = <1>;
label = "lan3";
+ phy-handle = <&sw_phy1>;
+ phy-mode = "internal";
};
port@2 {
reg = <2>;
label = "lan2";
+ phy-handle = <&sw_phy2>;
+ phy-mode = "internal";
};
port@3 {
reg = <3>;
label = "lan1";
+ phy-handle = <&sw_phy3>;
+ phy-mode = "internal";
};
port@5 {
reg = <5>;
- label = "cpu";
ethernet = <&fec>;
+ phy-mode = "rgmii-id";
+
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
};
};
};