diff options
| author | Rick Chen <rick@andestech.com> | 2023-01-03 11:17:13 +0300 |
|---|---|---|
| committer | Leo Yu-Chi Liang <ycliang@andestech.com> | 2023-02-01 11:17:34 +0300 |
| commit | c83f64b77dfa08717d697672881dbe33db6786b8 (patch) | |
| tree | e163868a46d4341839ec84174782b2c9a9750ff5 /arch | |
| parent | 81b56a55c21cf3de3e8faa4de3830a9036bf3e5c (diff) | |
| download | u-boot-c83f64b77dfa08717d697672881dbe33db6786b8.tar.xz | |
riscv: ae350: Enable CCTL_SUEN
CCTL operations are available to Supervisor/User-mode
software under the control of the mcache_ctl.CCTL_SUEN
control bit. Enable it to support Supervisor(and User)
CCTL operations.
Signed-off-by: Rick Chen <rick@andestech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/riscv/cpu/ax25/cpu.c | 18 |
1 files changed, 11 insertions, 7 deletions
diff --git a/arch/riscv/cpu/ax25/cpu.c b/arch/riscv/cpu/ax25/cpu.c index c4c2de2ef0..a46674f7c2 100644 --- a/arch/riscv/cpu/ax25/cpu.c +++ b/arch/riscv/cpu/ax25/cpu.c @@ -12,18 +12,20 @@ #include <asm/csr.h> #define CSR_MCACHE_CTL 0x7ca -#define CSR_MMISC_CTL 0x7d0 -#define CSR_MARCHID 0xf12 +#define CSR_MMISC_CTL 0x7d0 +#define CSR_MARCHID 0xf12 #define V5_MCACHE_CTL_IC_EN_OFFSET 0 #define V5_MCACHE_CTL_DC_EN_OFFSET 1 -#define V5_MCACHE_CTL_DC_COHEN_OFFSET 19 +#define V5_MCACHE_CTL_CCTL_SUEN_OFFSET 8 +#define V5_MCACHE_CTL_DC_COHEN_OFFSET 19 #define V5_MCACHE_CTL_DC_COHSTA_OFFSET 20 -#define V5_MCACHE_CTL_IC_EN BIT(V5_MCACHE_CTL_IC_EN_OFFSET) -#define V5_MCACHE_CTL_DC_EN BIT(V5_MCACHE_CTL_DC_EN_OFFSET) -#define V5_MCACHE_CTL_DC_COHEN_EN BIT(V5_MCACHE_CTL_DC_COHEN_OFFSET) -#define V5_MCACHE_CTL_DC_COHSTA_EN BIT(V5_MCACHE_CTL_DC_COHSTA_OFFSET) +#define V5_MCACHE_CTL_IC_EN BIT(V5_MCACHE_CTL_IC_EN_OFFSET) +#define V5_MCACHE_CTL_DC_EN BIT(V5_MCACHE_CTL_DC_EN_OFFSET) +#define V5_MCACHE_CTL_CCTL_SUEN BIT(V5_MCACHE_CTL_CCTL_SUEN_OFFSET) +#define V5_MCACHE_CTL_DC_COHEN_EN BIT(V5_MCACHE_CTL_DC_COHEN_OFFSET) +#define V5_MCACHE_CTL_DC_COHSTA_EN BIT(V5_MCACHE_CTL_DC_COHSTA_OFFSET) /* @@ -55,6 +57,8 @@ void harts_early_init(void) mcache_ctl_val |= V5_MCACHE_CTL_IC_EN; if (!(mcache_ctl_val & V5_MCACHE_CTL_DC_EN)) mcache_ctl_val |= V5_MCACHE_CTL_DC_EN; + if (!(mcache_ctl_val & V5_MCACHE_CTL_CCTL_SUEN)) + mcache_ctl_val |= V5_MCACHE_CTL_CCTL_SUEN; csr_write(CSR_MCACHE_CTL, mcache_ctl_val); /* |