diff options
| author | Tom Rini <trini@konsulko.com> | 2023-01-09 19:30:08 +0300 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2023-01-09 19:30:08 +0300 |
| commit | cebdfc22da6eb81793b616e855bc4d6d89c1c7a6 (patch) | |
| tree | 44eaafcbe4866712d361304882e7d56ca0ef1682 /arch | |
| parent | 62e2ad1ceafbfdf2c44d3dc1b6efc81e768a96b9 (diff) | |
| parent | fe33066d246462551f385f204690a11018336ac8 (diff) | |
| download | u-boot-cebdfc22da6eb81793b616e855bc4d6d89c1c7a6.tar.xz | |
Merge branch 'next'
Signed-off-by: Tom Rini <trini@konsulko.com>
Diffstat (limited to 'arch')
393 files changed, 13994 insertions, 4349 deletions
diff --git a/arch/Kconfig b/arch/Kconfig index 102956d24c..5f2b72f535 100644 --- a/arch/Kconfig +++ b/arch/Kconfig @@ -113,7 +113,6 @@ config RISCV select DM imply SPL_SEPARATE_BSS if SPL imply DM_SERIAL - imply DM_ETH imply DM_EVENT imply DM_MMC imply DM_SPI @@ -146,6 +145,7 @@ config SANDBOX select DM_SPI select DM_SPI_FLASH select GZIP_COMPRESSED + select IO_TRACE select LZO select OF_BOARD_SETUP select PCI_ENDPOINT @@ -240,7 +240,6 @@ config X86 imply CMD_SF imply CMD_SF_TEST imply CMD_ZBOOT - imply DM_ETH imply DM_EVENT imply DM_GPIO imply DM_KEYBOARD @@ -381,6 +380,10 @@ config SYS_IMMR Address for the Internal Memory-Mapped Registers (IMMR) window used to configure the features of many Freescale / NXP SoCs. +config MONITOR_IS_IN_RAM + bool "U-Boot is loaded in to RAM by a pre-loader" + depends on M68K || NIOS2 + config SKIP_LOWLEVEL_INIT bool "Skip the calls to certain low level initialization functions" depends on ARM || MIPS || RISCV diff --git a/arch/Kconfig.nxp b/arch/Kconfig.nxp index 8c5a6f63a9..ad61dabb31 100644 --- a/arch/Kconfig.nxp +++ b/arch/Kconfig.nxp @@ -1,5 +1,10 @@ +config FSL_TRUST_ARCH_v1 + bool + config NXP_ESBC bool "NXP ESBC (secure boot) functionality" + select FSL_TRUST_ARCH_v1 if ARCH_P3041 || ARCH_P4080 || \ + ARCH_P5040 || ARCH_P2041 help Enable Freescale Secure Boot feature. Normally selected by defconfig. If unsure, do not change. @@ -10,6 +15,7 @@ menu "Chain of trust / secure boot options" config CHAIN_OF_TRUST select FSL_CAAM select ARCH_MISC_INIT + select FSL_ISBC_KEY_EXT if (ARM || FSL_CORENET) && !SYS_RAMBOOT select FSL_SEC_MON select SPL_BOARD_INIT if (ARM && SPL) select SPL_HASH if (ARM && SPL) @@ -41,6 +47,17 @@ config ESBC_ADDR_64BIT help For Layerscape based platforms, ESBC image Address in Header is 64bit. +config FSL_ISBC_KEY_EXT + bool + help + The key used for verification of next level images is picked up from + an Extension Table which has been verified by the ISBC (Internal + Secure boot Code) in boot ROM of the SoC. The feature is only + applicable in case of NOR boot and is not applicable in case of + RAMBOOT (NAND, SD, SPI). For Layerscape, this feature is available + for all device if IE Table is copied to XIP memory Also, for + Layerscape, ISBC doesn't verify this table. + config SYS_FSL_SFP_BE def_bool y depends on PPC || FSL_LSCH2 || ARCH_LS1021A @@ -251,3 +268,6 @@ config QIXIS_I2C_ACCESS config HAS_FSL_DR_USB def_bool y depends on USB_EHCI_HCD && PPC + +config SYS_DPAA_FMAN + bool diff --git a/arch/arc/config.mk b/arch/arc/config.mk index 2b70945ac3..b713fa3054 100644 --- a/arch/arc/config.mk +++ b/arch/arc/config.mk @@ -21,6 +21,3 @@ PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections -fno-common # Needed for relocation LDFLAGS_FINAL += -pie --gc-sections - -# Load address for standalone apps -CONFIG_STANDALONE_LOAD_ADDR ?= 0x82000000 diff --git a/arch/arc/lib/cache.c b/arch/arc/lib/cache.c index 4c696cb53a..d97a578742 100644 --- a/arch/arc/lib/cache.c +++ b/arch/arc/lib/cache.c @@ -476,9 +476,9 @@ static void __slc_rgn_op(unsigned long paddr, unsigned long sz, const int op) static void arc_ioc_setup(void) { /* IOC Aperture start is equal to DDR start */ - unsigned int ap_base = CONFIG_SYS_SDRAM_BASE; + unsigned int ap_base = CFG_SYS_SDRAM_BASE; /* IOC Aperture size is equal to DDR size */ - long ap_size = CONFIG_SYS_SDRAM_SIZE; + long ap_size = CFG_SYS_SDRAM_SIZE; /* Unsupported configuration. See [ NOTE 2 ] for more details. */ if (!slc_exists()) diff --git a/arch/arc/lib/cpu.c b/arch/arc/lib/cpu.c index 6b215206a2..1567857961 100644 --- a/arch/arc/lib/cpu.c +++ b/arch/arc/lib/cpu.c @@ -20,7 +20,7 @@ int arch_cpu_init(void) timer_init(); gd->cpu_clk = get_board_sys_clk(); - gd->ram_size = CONFIG_SYS_SDRAM_SIZE; + gd->ram_size = CFG_SYS_SDRAM_SIZE; cache_init(); diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index cac4fa09fd..bbf1d5227b 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -553,6 +553,9 @@ config ARM64_SUPPORT_AARCH32 help This ARM64 system supports AArch32 execution state. +config IPROC + bool + config S5P def_bool y if ARCH_EXYNOS || ARCH_S5PC1XX @@ -586,7 +589,6 @@ config ARCH_KIRKWOOD config ARCH_MVEBU bool "Marvell MVEBU family (Armada XP/375/38x/3700/7K/8K)" select DM - select DM_ETH select DM_SERIAL select DM_SPI select DM_SPI_FLASH @@ -659,6 +661,7 @@ config TARGET_BCMCYGNUS bool "Support bcmcygnus" select CPU_V7A select GPIO_EXTRA_HEADER + select IPROC imply BCM_SF2_ETH imply BCM_SF2_ETH_GMAC imply CMD_HASH @@ -690,7 +693,6 @@ config ARCH_EXYNOS select DM select DM_GPIO select DM_I2C - select DM_ETH select DM_KEYBOARD select DM_SERIAL select DM_SPI @@ -721,7 +723,6 @@ config ARCH_HIGHBANK select CLK select CLK_CCF select AHCI - select DM_ETH select PHYS_64BIT select TIMER select SP804_TIMER @@ -918,6 +919,7 @@ config ARCH_MX7 select CPU_V7A select GPIO_EXTRA_HEADER select MACH_IMX + select MXC_GPT_HCLK select SYS_FSL_HAS_SEC select SYS_FSL_SEC_COMPAT_4 select SYS_FSL_SEC_LE @@ -931,6 +933,7 @@ config ARCH_MX6 select CPU_V7A select GPIO_EXTRA_HEADER select MACH_IMX + select MXC_GPT_HCLK select SYS_FSL_HAS_SEC select SYS_FSL_SEC_COMPAT_4 select SYS_FSL_SEC_LE @@ -995,7 +998,6 @@ config ARCH_APPLE config ARCH_OWL bool "Actions Semi OWL SoCs" select DM - select DM_ETH select DM_SERIAL select GPIO_EXTRA_HEADER select OWL_SERIAL @@ -1095,7 +1097,6 @@ config ARCH_SUNXI select CMD_USB if DISTRO_DEFAULTS && USB_HOST select CLK select DM - select DM_ETH select DM_GPIO select DM_I2C if I2C select DM_SPI if SPI @@ -1174,7 +1175,6 @@ config ARCH_VERSAL select ARM64 select CLK select DM - select DM_ETH if NET select DM_MMC if MMC select DM_SERIAL select GICV3 @@ -1188,7 +1188,6 @@ config ARCH_VERSAL_NET select ARM64 select CLK select DM - select DM_ETH if NET select DM_MMC if MMC select DM_SERIAL select OF_CONTROL @@ -1199,6 +1198,7 @@ config ARCH_VF610 bool "Freescale Vybrid" select CPU_V7A select GPIO_EXTRA_HEADER + select IOMUX_SHARE_CONF_REG select MACH_IMX select SYS_FSL_ERRATUM_ESDHC111 imply CMD_MTDPARTS @@ -1212,7 +1212,6 @@ config ARCH_ZYNQ select CPU_V7A select DEBUG_UART_BOARD_INIT if SPL && DEBUG_UART select DM - select DM_ETH if NET select DM_MMC if MMC select DM_SERIAL select DM_SPI @@ -1242,7 +1241,6 @@ config ARCH_ZYNQMP_R5 select CLK select CPU_V7R select DM - select DM_ETH if NET select DM_MMC if MMC select DM_SERIAL select OF_CONTROL @@ -1255,7 +1253,6 @@ config ARCH_ZYNQMP select CLK select DM select DEBUG_UART_BOARD_INIT if SPL && DEBUG_UART - select DM_ETH if NET imply DM_MAILBOX select DM_MMC if MMC select DM_SERIAL @@ -1606,6 +1603,7 @@ config TARGET_LS1021AQDS select CPU_V7_HAS_NONSEC select CPU_V7_HAS_VIRT select LS1_DEEP_SLEEP + select PEN_ADDR_BIG_ENDIAN select SUPPORT_SPL select SYS_FSL_DDR select FSL_DDR_INTERACTIVE @@ -1624,6 +1622,7 @@ config TARGET_LS1021ATWR select CPU_V7_HAS_NONSEC select CPU_V7_HAS_VIRT select LS1_DEEP_SLEEP + select PEN_ADDR_BIG_ENDIAN select SUPPORT_SPL select DM_SPI_FLASH if FSL_DSPI || FSL_QSPI select GPIO_EXTRA_HEADER @@ -1688,6 +1687,7 @@ config TARGET_LS1021AIOT select CPU_V7A select CPU_V7_HAS_NONSEC select CPU_V7_HAS_VIRT + select PEN_ADDR_BIG_ENDIAN select SUPPORT_SPL select DM_SPI_FLASH if FSL_DSPI || FSL_QSPI select GPIO_EXTRA_HEADER @@ -1802,7 +1802,6 @@ config TARGET_SL28 select DM_I2C select DM_MMC select DM_SPI_FLASH - select DM_ETH select DM_MDIO select PCI select DM_RNG @@ -1839,7 +1838,6 @@ config ARCH_UNIPHIER bool "Socionext UniPhier SoCs" select BOARD_LATE_INIT select DM - select DM_ETH select DM_GPIO select DM_I2C select DM_MMC @@ -2025,7 +2023,6 @@ config TARGET_POMELO select SCSI select DM_SCSI select DM_SERIAL - select DM_ETH if NET imply CMD_PCI help Support for pomelo platform. @@ -2295,6 +2292,7 @@ source "board/hisilicon/poplar/Kconfig" source "board/isee/igep003x/Kconfig" source "board/kontron/sl28/Kconfig" source "board/myir/mys_6ulx/Kconfig" +source "board/samsung/common/Kconfig" source "board/siemens/common/Kconfig" source "board/seeed/npi_imx6ull/Kconfig" source "board/socionext/developerbox/Kconfig" diff --git a/arch/arm/config.mk b/arch/arm/config.mk index 2065438d05..bf781f1026 100644 --- a/arch/arm/config.mk +++ b/arch/arm/config.mk @@ -3,14 +3,6 @@ # (C) Copyright 2000-2002 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. -ifndef CONFIG_STANDALONE_LOAD_ADDR -ifneq ($(CONFIG_ARCH_OMAP2PLUS),) -CONFIG_STANDALONE_LOAD_ADDR = 0x80300000 -else -CONFIG_STANDALONE_LOAD_ADDR = 0xc100000 -endif -endif - CFLAGS_NON_EFI := -fno-pic -ffixed-r9 -ffunction-sections -fdata-sections \ -fstack-protector-strong CFLAGS_EFI := -fpic -fshort-wchar diff --git a/arch/arm/cpu/arm1176/start.S b/arch/arm/cpu/arm1176/start.S index 5a1536539d..9e76a4a9e0 100644 --- a/arch/arm/cpu/arm1176/start.S +++ b/arch/arm/cpu/arm1176/start.S @@ -18,7 +18,7 @@ #include <linux/linkage.h> #ifndef CONFIG_SYS_PHY_UBOOT_BASE -#define CONFIG_SYS_PHY_UBOOT_BASE CONFIG_SYS_UBOOT_BASE +#define CONFIG_SYS_PHY_UBOOT_BASE CFG_SYS_UBOOT_BASE #endif /* diff --git a/arch/arm/cpu/arm920t/imx/Makefile b/arch/arm/cpu/arm920t/imx/Makefile deleted file mode 100644 index 04bc129592..0000000000 --- a/arch/arm/cpu/arm920t/imx/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. - -obj-y += generic.o -obj-y += speed.o -obj-y += timer.o diff --git a/arch/arm/cpu/arm920t/imx/generic.c b/arch/arm/cpu/arm920t/imx/generic.c deleted file mode 100644 index dbb908ecdc..0000000000 --- a/arch/arm/cpu/arm920t/imx/generic.c +++ /dev/null @@ -1,76 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * arch/arm/mach-imx/generic.c - * - * author: Sascha Hauer - * Created: april 20th, 2004 - * Copyright: Synertronixx GmbH - * - * Common code for i.MX machines - */ - -#include <common.h> - -#ifdef CONFIG_IMX - -#include <asm/arch/imx-regs.h> - -void imx_gpio_mode(int gpio_mode) -{ - unsigned int pin = gpio_mode & GPIO_PIN_MASK; - unsigned int port = (gpio_mode & GPIO_PORT_MASK) >> 5; - unsigned int ocr = (gpio_mode & GPIO_OCR_MASK) >> 10; - unsigned int tmp; - - /* Pullup enable */ - if(gpio_mode & GPIO_PUEN) - PUEN(port) |= (1<<pin); - else - PUEN(port) &= ~(1<<pin); - - /* Data direction */ - if(gpio_mode & GPIO_OUT) - DDIR(port) |= 1<<pin; - else - DDIR(port) &= ~(1<<pin); - - /* Primary / alternate function */ - if(gpio_mode & GPIO_AF) - GPR(port) |= (1<<pin); - else - GPR(port) &= ~(1<<pin); - - /* use as gpio? */ - if( ocr == 3 ) - GIUS(port) |= (1<<pin); - else - GIUS(port) &= ~(1<<pin); - - /* Output / input configuration */ - /* FIXME: I'm not very sure about OCR and ICONF, someone - * should have a look over it - */ - if(pin<16) { - tmp = OCR1(port); - tmp &= ~( 3<<(pin*2)); - tmp |= (ocr << (pin*2)); - OCR1(port) = tmp; - - if( gpio_mode & GPIO_AOUT ) - ICONFA1(port) &= ~( 3<<(pin*2)); - if( gpio_mode & GPIO_BOUT ) - ICONFB1(port) &= ~( 3<<(pin*2)); - } else { - tmp = OCR2(port); - tmp &= ~( 3<<((pin-16)*2)); - tmp |= (ocr << ((pin-16)*2)); - OCR2(port) = tmp; - - if( gpio_mode & GPIO_AOUT ) - ICONFA2(port) &= ~( 3<<((pin-16)*2)); - if( gpio_mode & GPIO_BOUT ) - ICONFB2(port) &= ~( 3<<((pin-16)*2)); - } -} - -#endif /* CONFIG_IMX */ diff --git a/arch/arm/cpu/arm920t/imx/speed.c b/arch/arm/cpu/arm920t/imx/speed.c deleted file mode 100644 index c19206ac39..0000000000 --- a/arch/arm/cpu/arm920t/imx/speed.c +++ /dev/null @@ -1,86 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * - * (c) 2004 Sascha Hauer <sascha@saschahauer.de> - */ - - -#include <common.h> -#if defined (CONFIG_IMX) -#include <clock_legacy.h> - -#include <asm/arch/imx-regs.h> - -/* ------------------------------------------------------------------------- */ -/* NOTE: This describes the proper use of this file. - * - * get_board_sys_clk() should be defined as the input frequency of the PLL. - * SH FIXME: 16780000 in our case - * get_FCLK(), get_HCLK(), get_PCLK() and get_UCLK() return the clock of - * the specified bus in HZ. - */ -/* ------------------------------------------------------------------------- */ - -ulong get_systemPLLCLK(void) -{ - /* FIXME: We assume System_SEL = 0 here */ - u32 spctl0 = SPCTL0; - u32 mfi = (spctl0 >> 10) & 0xf; - u32 mfn = spctl0 & 0x3f; - u32 mfd = (spctl0 >> 16) & 0x3f; - u32 pd = (spctl0 >> 26) & 0xf; - - mfi = mfi<=5 ? 5 : mfi; - - return (2*(CONFIG_SYSPLL_CLK_FREQ>>10)*( (mfi<<10) + (mfn<<10)/(mfd+1)))/(pd+1); -} - -ulong get_mcuPLLCLK(void) -{ - /* FIXME: We assume System_SEL = 0 here */ - u32 mpctl0 = MPCTL0; - u32 mfi = (mpctl0 >> 10) & 0xf; - u32 mfn = mpctl0 & 0x3f; - u32 mfd = (mpctl0 >> 16) & 0x3f; - u32 pd = (mpctl0 >> 26) & 0xf; - - mfi = mfi<=5 ? 5 : mfi; - - return (2*(get_board_sys_clk()>>10)*( (mfi<<10) + (mfn<<10)/(mfd+1)))/(pd+1); -} - -ulong get_FCLK(void) -{ - return (( CSCR>>15)&1) ? get_mcuPLLCLK()>>1 : get_mcuPLLCLK(); -} - -/* return HCLK frequency */ -ulong get_HCLK(void) -{ - u32 bclkdiv = (( CSCR >> 10 ) & 0xf) + 1; - printf("bclkdiv: %d\n", bclkdiv); - return get_systemPLLCLK() / bclkdiv; -} - -/* return BCLK frequency */ -ulong get_BCLK(void) -{ - return get_HCLK(); -} - -ulong get_PERCLK1(void) -{ - return get_systemPLLCLK() / (((PCDR) & 0xf)+1); -} - -ulong get_PERCLK2(void) -{ - return get_systemPLLCLK() / (((PCDR>>4) & 0xf)+1); -} - -ulong get_PERCLK3(void) -{ - return get_systemPLLCLK() / (((PCDR>>16) & 0x7f)+1); -} - -#endif /* defined (CONFIG_IMX) */ diff --git a/arch/arm/cpu/arm920t/imx/timer.c b/arch/arm/cpu/arm920t/imx/timer.c deleted file mode 100644 index 0cd3a03981..0000000000 --- a/arch/arm/cpu/arm920t/imx/timer.c +++ /dev/null @@ -1,100 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Marius Groeger <mgroeger@sysgo.de> - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Alex Zuepke <azu@sysgo.de> - * - * (C) Copyright 2002 - * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de> - */ - -#include <common.h> -#include <cpu_func.h> -#include <time.h> -#if defined (CONFIG_IMX) - -#include <asm/arch/imx-regs.h> -#include <linux/delay.h> - -int timer_init (void) -{ - int i; - /* setup GP Timer 1 */ - TCTL1 = TCTL_SWR; - for ( i=0; i<100; i++) TCTL1 = 0; /* We have no udelay by now */ - TPRER1 = get_PERCLK1() / 1000000; /* 1 MHz */ - TCTL1 |= TCTL_FRR | (1<<1); /* Freerun Mode, PERCLK1 input */ - - /* Reset the timer */ - TCTL1 &= ~TCTL_TEN; - TCTL1 |= TCTL_TEN; /* Enable timer */ - - return (0); -} - -/* - * timer without interrupts - */ -static ulong get_timer_masked (void) -{ - return TCN1; -} - -ulong get_timer (ulong base) -{ - return get_timer_masked() - base; -} - -void __udelay(unsigned long usec) -{ - ulong endtime = get_timer_masked() + usec; - signed long diff; - - do { - ulong now = get_timer_masked (); - diff = endtime - now; - } while (diff >= 0); -} - -/* - * This function is derived from PowerPC code (read timebase as long long). - * On ARM it just returns the timer value. - */ -unsigned long long get_ticks(void) -{ - return get_timer(0); -} - -/* - * This function is derived from PowerPC code (timebase clock frequency). - * On ARM it returns the number of timer ticks per second. - */ -ulong get_tbclk(void) -{ - return CONFIG_SYS_HZ; -} - -/* - * Reset the cpu by setting up the watchdog timer and let him time out - */ -void reset_cpu(void) -{ - /* Disable watchdog and set Time-Out field to 0 */ - WCR = 0x00000000; - - /* Write Service Sequence */ - WSR = 0x00005555; - WSR = 0x0000AAAA; - - /* Enable watchdog */ - WCR = 0x00000001; - - while (1); - /*NOTREACHED*/ -} - -#endif /* defined (CONFIG_IMX) */ diff --git a/arch/arm/cpu/arm926ejs/Makefile b/arch/arm/cpu/arm926ejs/Makefile index 7f1436d76e..7e7ad4f35d 100644 --- a/arch/arm/cpu/arm926ejs/Makefile +++ b/arch/arm/cpu/arm926ejs/Makefile @@ -12,7 +12,6 @@ extra-y := endif endif -obj-$(CONFIG_MX27) += mx27/ obj-$(if $(filter mxs,$(SOC)),y) += mxs/ obj-$(if $(filter spear,$(SOC)),y) += spear/ obj-$(CONFIG_ARCH_SUNXI) += sunxi/ diff --git a/arch/arm/cpu/arm926ejs/mx27/Makefile b/arch/arm/cpu/arm926ejs/mx27/Makefile deleted file mode 100644 index ac5ebaf5ef..0000000000 --- a/arch/arm/cpu/arm926ejs/mx27/Makefile +++ /dev/null @@ -1,7 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# - -obj-y += generic.o timer.o reset.o relocate.o diff --git a/arch/arm/cpu/arm926ejs/mx27/generic.c b/arch/arm/cpu/arm926ejs/mx27/generic.c deleted file mode 100644 index 8b9d3a272a..0000000000 --- a/arch/arm/cpu/arm926ejs/mx27/generic.c +++ /dev/null @@ -1,378 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (c) 2008 Eric Jarrige <eric.jarrige@armadeus.org> - * Copyright (c) 2009 Ilya Yanok <yanok@emcraft.com> - */ - -#include <common.h> -#include <div64.h> -#include <net.h> -#include <netdev.h> -#include <vsprintf.h> -#include <asm/io.h> -#include <asm/arch/imx-regs.h> -#include <asm/arch/clock.h> -#include <asm/arch/gpio.h> -#include <asm/mach-imx/sys_proto.h> -#ifdef CONFIG_MMC_MXC -#include <asm/arch/mxcmmc.h> -#endif - -/* - * get the system pll clock in Hz - * - * mfi + mfn / (mfd +1) - * f = 2 * f_ref * -------------------- - * pd + 1 - */ -static unsigned int imx_decode_pll(unsigned int pll, unsigned int f_ref) -{ - unsigned int mfi = (pll >> 10) & 0xf; - unsigned int mfn = pll & 0x3ff; - unsigned int mfd = (pll >> 16) & 0x3ff; - unsigned int pd = (pll >> 26) & 0xf; - - mfi = mfi <= 5 ? 5 : mfi; - - return lldiv(2 * (u64)f_ref * (mfi * (mfd + 1) + mfn), - (mfd + 1) * (pd + 1)); -} - -static ulong clk_in_32k(void) -{ - return 1024 * CONFIG_MX27_CLK32; -} - -static ulong clk_in_26m(void) -{ - struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE; - - if (readl(&pll->cscr) & CSCR_OSC26M_DIV1P5) { - /* divide by 1.5 */ - return 26000000 * 2 / 3; - } else { - return 26000000; - } -} - -static ulong imx_get_mpllclk(void) -{ - struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE; - ulong cscr = readl(&pll->cscr); - ulong fref; - - if (cscr & CSCR_MCU_SEL) - fref = clk_in_26m(); - else - fref = clk_in_32k(); - - return imx_decode_pll(readl(&pll->mpctl0), fref); -} - -static ulong imx_get_armclk(void) -{ - struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE; - ulong cscr = readl(&pll->cscr); - ulong fref = imx_get_mpllclk(); - ulong div; - - if (!(cscr & CSCR_ARM_SRC_MPLL)) - fref = lldiv((fref * 2), 3); - - div = ((cscr >> 12) & 0x3) + 1; - - return lldiv(fref, div); -} - -static ulong imx_get_ahbclk(void) -{ - struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE; - ulong cscr = readl(&pll->cscr); - ulong fref = imx_get_mpllclk(); - ulong div; - - div = ((cscr >> 8) & 0x3) + 1; - - return lldiv(fref * 2, 3 * div); -} - -static __attribute__((unused)) ulong imx_get_spllclk(void) -{ - struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE; - ulong cscr = readl(&pll->cscr); - ulong fref; - - if (cscr & CSCR_SP_SEL) - fref = clk_in_26m(); - else - fref = clk_in_32k(); - - return imx_decode_pll(readl(&pll->spctl0), fref); -} - -static ulong imx_decode_perclk(ulong div) -{ - return lldiv((imx_get_mpllclk() * 2), (div * 3)); -} - -static ulong imx_get_perclk1(void) -{ - struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE; - - return imx_decode_perclk((readl(&pll->pcdr1) & 0x3f) + 1); -} - -static ulong imx_get_perclk2(void) -{ - struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE; - - return imx_decode_perclk(((readl(&pll->pcdr1) >> 8) & 0x3f) + 1); -} - -static __attribute__((unused)) ulong imx_get_perclk3(void) -{ - struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE; - - return imx_decode_perclk(((readl(&pll->pcdr1) >> 16) & 0x3f) + 1); -} - -static __attribute__((unused)) ulong imx_get_perclk4(void) -{ - struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE; - - return imx_decode_perclk(((readl(&pll->pcdr1) >> 24) & 0x3f) + 1); -} - -unsigned int mxc_get_clock(enum mxc_clock clk) -{ - switch (clk) { - case MXC_ARM_CLK: - return imx_get_armclk(); - case MXC_I2C_CLK: - return imx_get_ahbclk()/2; - case MXC_UART_CLK: - return imx_get_perclk1(); - case MXC_FEC_CLK: - return imx_get_ahbclk(); - case MXC_ESDHC_CLK: - return imx_get_perclk2(); - } - return -1; -} - - -u32 get_cpu_rev(void) -{ - return MXC_CPU_MX27 << 12; -} - -#if defined(CONFIG_DISPLAY_CPUINFO) -int print_cpuinfo (void) -{ - char buf[32]; - - printf("CPU: Freescale i.MX27 at %s MHz\n\n", - strmhz(buf, imx_get_mpllclk())); - return 0; -} -#endif - -int cpu_eth_init(struct bd_info *bis) -{ -#if defined(CONFIG_FEC_MXC) - struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE; - - /* enable FEC clock */ - writel(readl(&pll->pccr1) | PCCR1_HCLK_FEC, &pll->pccr1); - writel(readl(&pll->pccr0) | PCCR0_FEC_EN, &pll->pccr0); - return fecmxc_initialize(bis); -#else - return 0; -#endif -} - -/* - * Initializes on-chip MMC controllers. - * to override, implement board_mmc_init() - */ -int cpu_mmc_init(struct bd_info *bis) -{ -#ifdef CONFIG_MMC_MXC - return mxc_mmc_init(bis); -#else - return 0; -#endif -} - -void imx_gpio_mode(int gpio_mode) -{ - struct gpio_port_regs *regs = (struct gpio_port_regs *)IMX_GPIO_BASE; - unsigned int pin = gpio_mode & GPIO_PIN_MASK; - unsigned int port = (gpio_mode & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; - unsigned int ocr = (gpio_mode & GPIO_OCR_MASK) >> GPIO_OCR_SHIFT; - unsigned int aout = (gpio_mode & GPIO_AOUT_MASK) >> GPIO_AOUT_SHIFT; - unsigned int bout = (gpio_mode & GPIO_BOUT_MASK) >> GPIO_BOUT_SHIFT; - unsigned int tmp; - - /* Pullup enable */ - if (gpio_mode & GPIO_PUEN) { - writel(readl(®s->port[port].puen) | (1 << pin), - ®s->port[port].puen); - } else { - writel(readl(®s->port[port].puen) & ~(1 << pin), - ®s->port[port].puen); - } - - /* Data direction */ - if (gpio_mode & GPIO_OUT) { - writel(readl(®s->port[port].gpio_dir) | 1 << pin, - ®s->port[port].gpio_dir); - } else { - writel(readl(®s->port[port].gpio_dir) & ~(1 << pin), - ®s->port[port].gpio_dir); - } - - /* Primary / alternate function */ - if (gpio_mode & GPIO_AF) { - writel(readl(®s->port[port].gpr) | (1 << pin), - ®s->port[port].gpr); - } else { - writel(readl(®s->port[port].gpr) & ~(1 << pin), - ®s->port[port].gpr); - } - - /* use as gpio? */ - if (!(gpio_mode & (GPIO_PF | GPIO_AF))) { - writel(readl(®s->port[port].gius) | (1 << pin), - ®s->port[port].gius); - } else { - writel(readl(®s->port[port].gius) & ~(1 << pin), - ®s->port[port].gius); - } - - /* Output / input configuration */ - if (pin < 16) { - tmp = readl(®s->port[port].ocr1); - tmp &= ~(3 << (pin * 2)); - tmp |= (ocr << (pin * 2)); - writel(tmp, ®s->port[port].ocr1); - - writel(readl(®s->port[port].iconfa1) & ~(3 << (pin * 2)), - ®s->port[port].iconfa1); - writel(readl(®s->port[port].iconfa1) | aout << (pin * 2), - ®s->port[port].iconfa1); - writel(readl(®s->port[port].iconfb1) & ~(3 << (pin * 2)), - ®s->port[port].iconfb1); - writel(readl(®s->port[port].iconfb1) | bout << (pin * 2), - ®s->port[port].iconfb1); - } else { - pin -= 16; - - tmp = readl(®s->port[port].ocr2); - tmp &= ~(3 << (pin * 2)); - tmp |= (ocr << (pin * 2)); - writel(tmp, ®s->port[port].ocr2); - - writel(readl(®s->port[port].iconfa2) & ~(3 << (pin * 2)), - ®s->port[port].iconfa2); - writel(readl(®s->port[port].iconfa2) | aout << (pin * 2), - ®s->port[port].iconfa2); - writel(readl(®s->port[port].iconfb2) & ~(3 << (pin * 2)), - ®s->port[port].iconfb2); - writel(readl(®s->port[port].iconfb2) | bout << (pin * 2), - ®s->port[port].iconfb2); - } -} - -#ifdef CONFIG_MXC_UART -void mx27_uart1_init_pins(void) -{ - int i; - unsigned int mode[] = { - PE12_PF_UART1_TXD, - PE13_PF_UART1_RXD, - }; - - for (i = 0; i < ARRAY_SIZE(mode); i++) - imx_gpio_mode(mode[i]); - -} -#endif /* CONFIG_MXC_UART */ - -#ifdef CONFIG_FEC_MXC -void mx27_fec_init_pins(void) -{ - int i; - unsigned int mode[] = { - PD0_AIN_FEC_TXD0, - PD1_AIN_FEC_TXD1, - PD2_AIN_FEC_TXD2, - PD3_AIN_FEC_TXD3, - PD4_AOUT_FEC_RX_ER, - PD5_AOUT_FEC_RXD1, - PD6_AOUT_FEC_RXD2, - PD7_AOUT_FEC_RXD3, - PD8_AF_FEC_MDIO, - PD9_AIN_FEC_MDC | GPIO_PUEN, - PD10_AOUT_FEC_CRS, - PD11_AOUT_FEC_TX_CLK, - PD12_AOUT_FEC_RXD0, - PD13_AOUT_FEC_RX_DV, - PD14_AOUT_FEC_CLR, - PD15_AOUT_FEC_COL, - PD16_AIN_FEC_TX_ER, - PF23_AIN_FEC_TX_EN, - }; - - for (i = 0; i < ARRAY_SIZE(mode); i++) - imx_gpio_mode(mode[i]); -} - -void imx_get_mac_from_fuse(int dev_id, unsigned char *mac) -{ - int i; - struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE; - struct fuse_bank *bank = &iim->bank[0]; - struct fuse_bank0_regs *fuse = - (struct fuse_bank0_regs *)bank->fuse_regs; - - for (i = 0; i < 6; i++) - mac[6 - 1 - i] = readl(&fuse->mac_addr[i]) & 0xff; -} -#endif /* CONFIG_FEC_MXC */ - -#ifdef CONFIG_MMC_MXC -void mx27_sd1_init_pins(void) -{ - int i; - unsigned int mode[] = { - PE18_PF_SD1_D0, - PE19_PF_SD1_D1, - PE20_PF_SD1_D2, - PE21_PF_SD1_D3, - PE22_PF_SD1_CMD, - PE23_PF_SD1_CLK, - }; - - for (i = 0; i < ARRAY_SIZE(mode); i++) - imx_gpio_mode(mode[i]); - -} - -void mx27_sd2_init_pins(void) -{ - int i; - unsigned int mode[] = { - PB4_PF_SD2_D0, - PB5_PF_SD2_D1, - PB6_PF_SD2_D2, - PB7_PF_SD2_D3, - PB8_PF_SD2_CMD, - PB9_PF_SD2_CLK, - }; - - for (i = 0; i < ARRAY_SIZE(mode); i++) - imx_gpio_mode(mode[i]); - -} -#endif /* CONFIG_MMC_MXC */ diff --git a/arch/arm/cpu/arm926ejs/mx27/relocate.S b/arch/arm/cpu/arm926ejs/mx27/relocate.S deleted file mode 100644 index 5dfa272be2..0000000000 --- a/arch/arm/cpu/arm926ejs/mx27/relocate.S +++ /dev/null @@ -1,50 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * relocate - i.MX27-specific vector relocation - * - * Copyright (c) 2013 Albert ARIBAUD <albert.u.boot@aribaud.net> - */ - -#include <asm-offsets.h> -#include <config.h> -#include <linux/linkage.h> - -/* - * The i.MX27 SoC is very specific with respect to exceptions: it - * does not provide RAM at the high vectors address (0xFFFF0000), - * thus only the low address (0x00000000) is useable; but that is - * in ROM. Therefore, vectors cannot be changed at all. - * - * However, these ROM-based vectors actually just perform indirect - * calls through pointers located in RAM at SoC-specific addresses, - * as follows: - * - * Offset Exception Use by ROM code - * 0x00000000 reset indirect branch to [0x00000014] - * 0x00000004 undefined instruction indirect branch to [0xfffffef0] - * 0x00000008 software interrupt indirect branch to [0xfffffef4] - * 0x0000000c prefetch abort indirect branch to [0xfffffef8] - * 0x00000010 data abort indirect branch to [0xfffffefc] - * 0x00000014 (reserved in ARMv5) vector to ROM reset: 0xc0000000 - * 0x00000018 IRQ indirect branch to [0xffffff00] - * 0x0000001c FIQ indirect branch to [0xffffff04] - * - * In order to initialize exceptions on i.MX27, we must copy U-Boot's - * indirect (not exception!) vector table into 0xfffffef0..0xffffff04 - * taking care not to copy vectors number 5 (reserved exception). - */ - - .section .text.relocate_vectors,"ax",%progbits - -ENTRY(relocate_vectors) - - ldr r0, [r9, #GD_RELOCADDR] /* r0 = gd->relocaddr */ - ldr r1, =32 /* size of vector table */ - add r0, r0, r1 /* skip to indirect table */ - ldr r1, =0xFFFFFEF0 /* i.MX27 indirect table */ - ldmia r0!, {r2-r8} /* load indirect vectors 1..7 */ - stmia r1!, {r2-r5, r7,r8} /* write all but vector 5 */ - - bx lr - -ENDPROC(relocate_vectors) diff --git a/arch/arm/cpu/arm926ejs/mx27/reset.c b/arch/arm/cpu/arm926ejs/mx27/reset.c deleted file mode 100644 index 496fb30817..0000000000 --- a/arch/arm/cpu/arm926ejs/mx27/reset.c +++ /dev/null @@ -1,41 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Marius Groeger <mgroeger@sysgo.de> - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Alex Zuepke <azu@sysgo.de> - * - * (C) Copyright 2002 - * Gary Jennejohn, DENX Software Engineering, <gj@denx.de> - * - * (C) Copyright 2009 - * Ilya Yanok, Emcraft Systems Ltd, <yanok@emcraft.com> - */ - -#include <common.h> -#include <cpu_func.h> -#include <asm/io.h> -#include <asm/arch/imx-regs.h> - -/* - * Reset the cpu by setting up the watchdog timer and let it time out - */ -void reset_cpu(void) -{ - struct wdog_regs *regs = (struct wdog_regs *)IMX_WDT_BASE; - /* Disable watchdog and set Time-Out field to 0 */ - writew(0x0000, ®s->wcr); - - /* Write Service Sequence */ - writew(0x5555, ®s->wsr); - writew(0xAAAA, ®s->wsr); - - /* Enable watchdog */ - writew(WCR_WDE, ®s->wcr); - - while (1); - /*NOTREACHED*/ -} diff --git a/arch/arm/cpu/arm926ejs/mx27/timer.c b/arch/arm/cpu/arm926ejs/mx27/timer.c deleted file mode 100644 index 4fd6a80596..0000000000 --- a/arch/arm/cpu/arm926ejs/mx27/timer.c +++ /dev/null @@ -1,166 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Marius Groeger <mgroeger@sysgo.de> - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Alex Zuepke <azu@sysgo.de> - * - * (C) Copyright 2002 - * Gary Jennejohn, DENX Software Engineering, <gj@denx.de> - * - * (C) Copyright 2009 - * Ilya Yanok, Emcraft Systems Ltd, <yanok@emcraft.com> - */ - -#include <common.h> -#include <div64.h> -#include <init.h> -#include <time.h> -#include <asm/global_data.h> -#include <asm/io.h> -#include <asm/arch/imx-regs.h> -#include <asm/ptrace.h> -#include <linux/delay.h> - -/* General purpose timers bitfields */ -#define GPTCR_SWR (1 << 15) /* Software reset */ -#define GPTCR_FRR (1 << 8) /* Freerun / restart */ -#define GPTCR_CLKSOURCE_32 (4 << 1) /* Clock source */ -#define GPTCR_TEN 1 /* Timer enable */ - -DECLARE_GLOBAL_DATA_PTR; - -#define timestamp (gd->arch.tbl) -#define lastinc (gd->arch.lastinc) - -/* - * "time" is measured in 1 / CONFIG_SYS_HZ seconds, - * "tick" is internal timer period - */ -#ifdef CONFIG_MX27_TIMER_HIGH_PRECISION -/* ~0.4% error - measured with stop-watch on 100s boot-delay */ -static inline unsigned long long tick_to_time(unsigned long long tick) -{ - tick *= CONFIG_SYS_HZ; - do_div(tick, CONFIG_MX27_CLK32); - return tick; -} - -static inline unsigned long long time_to_tick(unsigned long long time) -{ - time *= CONFIG_MX27_CLK32; - do_div(time, CONFIG_SYS_HZ); - return time; -} - -static inline unsigned long long us_to_tick(unsigned long long us) -{ - us = us * CONFIG_MX27_CLK32 + 999999; - do_div(us, 1000000); - return us; -} -#else -/* ~2% error */ -#define TICK_PER_TIME ((CONFIG_MX27_CLK32 + CONFIG_SYS_HZ / 2) / \ - CONFIG_SYS_HZ) -#define US_PER_TICK (1000000 / CONFIG_MX27_CLK32) - -static inline unsigned long long tick_to_time(unsigned long long tick) -{ - do_div(tick, TICK_PER_TIME); - return tick; -} - -static inline unsigned long long time_to_tick(unsigned long long time) -{ - return time * TICK_PER_TIME; -} - -static inline unsigned long long us_to_tick(unsigned long long us) -{ - us += US_PER_TICK - 1; - do_div(us, US_PER_TICK); - return us; -} -#endif - -/* nothing really to do with interrupts, just starts up a counter. */ -/* The 32768Hz 32-bit timer overruns in 131072 seconds */ -int timer_init(void) -{ - int i; - struct gpt_regs *regs = (struct gpt_regs *)IMX_TIM1_BASE; - struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE; - - /* setup GP Timer 1 */ - writel(GPTCR_SWR, ®s->gpt_tctl); - - writel(readl(&pll->pccr0) | PCCR0_GPT1_EN, &pll->pccr0); - writel(readl(&pll->pccr1) | PCCR1_PERCLK1_EN, &pll->pccr1); - - for (i = 0; i < 100; i++) - writel(0, ®s->gpt_tctl); /* We have no udelay by now */ - writel(0, ®s->gpt_tprer); /* 32Khz */ - /* Freerun Mode, PERCLK1 input */ - writel(readl(®s->gpt_tctl) | GPTCR_CLKSOURCE_32 | GPTCR_FRR, - ®s->gpt_tctl); - writel(readl(®s->gpt_tctl) | GPTCR_TEN, ®s->gpt_tctl); - - return 0; -} - -unsigned long long get_ticks(void) -{ - struct gpt_regs *regs = (struct gpt_regs *)IMX_TIM1_BASE; - ulong now = readl(®s->gpt_tcn); /* current tick value */ - - if (now >= lastinc) { - /* - * normal mode (non roll) - * move stamp forward with absolut diff ticks - */ - timestamp += (now - lastinc); - } else { - /* we have rollover of incrementer */ - timestamp += (0xFFFFFFFF - lastinc) + now; - } - lastinc = now; - return timestamp; -} - -static ulong get_timer_masked(void) -{ - /* - * get_ticks() returns a long long (64 bit), it wraps in - * 2^64 / CONFIG_MX27_CLK32 = 2^64 / 2^15 = 2^49 ~ 5 * 10^14 (s) ~ - * 5 * 10^9 days... and get_ticks() * CONFIG_SYS_HZ wraps in - * 5 * 10^6 days - long enough. - */ - return tick_to_time(get_ticks()); -} - -ulong get_timer(ulong base) -{ - return get_timer_masked() - base; -} - -/* delay x useconds AND preserve advance timstamp value */ -void __udelay(unsigned long usec) -{ - unsigned long long tmp; - ulong tmo; - - tmo = us_to_tick(usec); - tmp = get_ticks() + tmo; /* get current timestamp */ - - while (get_ticks() < tmp) /* loop till event */ - /*NOP*/; -} - -ulong get_tbclk(void) -{ - return CONFIG_MX27_CLK32; -} diff --git a/arch/arm/cpu/arm926ejs/start.S b/arch/arm/cpu/arm926ejs/start.S index aca7793c57..c882bd39ea 100644 --- a/arch/arm/cpu/arm926ejs/start.S +++ b/arch/arm/cpu/arm926ejs/start.S @@ -95,7 +95,7 @@ flush_dcache: mrc p15, 0, r0, c1, c0, 0 bic r0, r0, #0x00000300 /* clear bits 9:8 (---- --RS) */ bic r0, r0, #0x00000087 /* clear bits 7, 2:0 (B--- -CAM) */ -#ifdef CONFIG_SYS_EXCEPTION_VECTORS_HIGH +#ifdef CFG_SYS_EXCEPTION_VECTORS_HIGH orr r0, r0, #0x00002000 /* set bit 13 (--V- ----) */ #else bic r0, r0, #0x00002000 /* clear bit 13 (--V- ----) */ diff --git a/arch/arm/cpu/armv7/arch_timer.c b/arch/arm/cpu/armv7/arch_timer.c index d96406f762..17bd53dae8 100644 --- a/arch/arm/cpu/armv7/arch_timer.c +++ b/arch/arm/cpu/armv7/arch_timer.c @@ -14,7 +14,7 @@ DECLARE_GLOBAL_DATA_PTR; -#ifndef CONFIG_SYS_HZ_CLOCK +#ifndef CFG_SYS_HZ_CLOCK static inline u32 read_cntfrq(void) { u32 frq; @@ -29,8 +29,8 @@ int timer_init(void) gd->arch.tbl = 0; gd->arch.tbu = 0; -#ifdef CONFIG_SYS_HZ_CLOCK - gd->arch.timer_rate_hz = CONFIG_SYS_HZ_CLOCK; +#ifdef CFG_SYS_HZ_CLOCK + gd->arch.timer_rate_hz = CFG_SYS_HZ_CLOCK; #else gd->arch.timer_rate_hz = read_cntfrq(); #endif diff --git a/arch/arm/cpu/armv7/ls102xa/Kconfig b/arch/arm/cpu/armv7/ls102xa/Kconfig index e75a895e00..a83eb7e8fd 100644 --- a/arch/arm/cpu/armv7/ls102xa/Kconfig +++ b/arch/arm/cpu/armv7/ls102xa/Kconfig @@ -1,6 +1,8 @@ config ARCH_LS1021A bool + select FSL_DEVICE_DISABLE select FSL_IFC if !QSPI_BOOT && !SD_BOOT_QSPI + select LS102XA_STREAM_ID select SYS_FSL_DDR_BE if SYS_FSL_DDR select SYS_FSL_DDR_VER_50 if SYS_FSL_DDR select SYS_FSL_IFC_BE @@ -30,9 +32,15 @@ config ARCH_LS1021A menu "LS102xA architecture" depends on ARCH_LS1021A +config FSL_DEVICE_DISABLE + bool + config LS1_DEEP_SLEEP bool "Deep sleep" +config LS102XA_STREAM_ID + bool + config MAX_CPUS int "Maximum number of CPUs permitted for LS102xA" default 2 @@ -43,6 +51,9 @@ config MAX_CPUS cores, count the reserved ports. This will allocate enough memory in spin table to properly handle all cores. +config PEN_ADDR_BIG_ENDIAN + bool + config SYS_CCI400_OFFSET hex "Offset for CCI400 base" depends on SYS_FSL_HAS_CCI400 diff --git a/arch/arm/cpu/armv7/ls102xa/cpu.c b/arch/arm/cpu/armv7/ls102xa/cpu.c index d530e0655b..c455969609 100644 --- a/arch/arm/cpu/armv7/ls102xa/cpu.c +++ b/arch/arm/cpu/armv7/ls102xa/cpu.c @@ -168,18 +168,18 @@ static void mmu_setup(void) /* Level 1 has 512 entries */ for (i = 0; i < 512; i++) { /* Mapping for PCIe 1 */ - if (va_start >= CONFIG_SYS_PCIE1_VIRT_ADDR && - va_start < (CONFIG_SYS_PCIE1_VIRT_ADDR + - CONFIG_SYS_PCIE_MMAP_SIZE)) + if (va_start >= CFG_SYS_PCIE1_VIRT_ADDR && + va_start < (CFG_SYS_PCIE1_VIRT_ADDR + + CFG_SYS_PCIE_MMAP_SIZE)) set_pgsection(level1_table, i, - CONFIG_SYS_PCIE1_PHYS_BASE + va_start, + CFG_SYS_PCIE1_PHYS_BASE + va_start, MT_DEVICE_MEM); /* Mapping for PCIe 2 */ - else if (va_start >= CONFIG_SYS_PCIE2_VIRT_ADDR && - va_start < (CONFIG_SYS_PCIE2_VIRT_ADDR + - CONFIG_SYS_PCIE_MMAP_SIZE)) + else if (va_start >= CFG_SYS_PCIE2_VIRT_ADDR && + va_start < (CFG_SYS_PCIE2_VIRT_ADDR + + CFG_SYS_PCIE_MMAP_SIZE)) set_pgsection(level1_table, i, - CONFIG_SYS_PCIE2_PHYS_BASE + va_start, + CFG_SYS_PCIE2_PHYS_BASE + va_start, MT_DEVICE_MEM); else set_pgsection(level1_table, i, @@ -302,20 +302,11 @@ int cpu_mmc_init(struct bd_info *bis) } #endif -int cpu_eth_init(struct bd_info *bis) -{ -#if defined(CONFIG_TSEC_ENET) && !defined(CONFIG_DM_ETH) - tsec_standard_init(bis); -#endif - - return 0; -} - int arch_cpu_init(void) { - void *epu_base = (void *)(CONFIG_SYS_DCSRBAR + EPU_BLOCK_OFFSET); + void *epu_base = (void *)(CFG_SYS_DCSRBAR + EPU_BLOCK_OFFSET); void *rcpm2_base = - (void *)(CONFIG_SYS_DCSRBAR + DCSR_RCPM2_BLOCK_OFFSET); + (void *)(CFG_SYS_DCSRBAR + DCSR_RCPM2_BLOCK_OFFSET); struct ccsr_scfg *scfg = (void *)CFG_SYS_FSL_SCFG_ADDR; u32 state; diff --git a/arch/arm/cpu/armv7/ls102xa/fdt.c b/arch/arm/cpu/armv7/ls102xa/fdt.c index c01cebbf98..599b7e18ef 100644 --- a/arch/arm/cpu/armv7/ls102xa/fdt.c +++ b/arch/arm/cpu/armv7/ls102xa/fdt.c @@ -125,7 +125,7 @@ void ft_cpu_setup(void *blob, struct bd_info *bd) #ifdef CONFIG_SYS_NS16550 do_fixup_by_compat_u32(blob, "fsl,16550-FIFO64", - "clock-frequency", CONFIG_SYS_NS16550_CLK, 1); + "clock-frequency", CFG_SYS_NS16550_CLK, 1); #endif sysclk_path = fdt_get_alias(blob, "sysclk"); @@ -183,7 +183,7 @@ void ft_cpu_setup(void *blob, struct bd_info *bd) #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) off = fdt_node_offset_by_compat_reg(blob, FSL_IFC_COMPAT, - CONFIG_SYS_IFC_ADDR); + CFG_SYS_IFC_ADDR); fdt_set_node_status(blob, off, FDT_STATUS_DISABLED); #else off = fdt_node_offset_by_compat_reg(blob, FSL_QSPI_COMPAT, diff --git a/arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c b/arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c index b4d113dc1e..dbb0766a9c 100644 --- a/arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c +++ b/arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c @@ -29,7 +29,7 @@ */ static void __secure ls1_save_ddr_head(void) { - const char *src = (const char *)CONFIG_SYS_SDRAM_BASE; + const char *src = (const char *)CFG_SYS_SDRAM_BASE; char *dest = (char *)(OCRAM_BASE_S_ADDR + OCRAM_S_SIZE - DDR_RESV_LEN); struct ccsr_scfg __iomem *scfg = (void *)CFG_SYS_FSL_SCFG_ADDR; int i; @@ -42,7 +42,7 @@ static void __secure ls1_save_ddr_head(void) static void __secure ls1_fsm_setup(void) { - void *dcsr_epu_base = (void *)(CONFIG_SYS_DCSRBAR + EPU_BLOCK_OFFSET); + void *dcsr_epu_base = (void *)(CFG_SYS_DCSRBAR + EPU_BLOCK_OFFSET); void *dcsr_rcpm_base = (void *)SYS_FSL_DCSR_RCPM_ADDR; out_be32(dcsr_rcpm_base + DCSR_RCPM_CSTTACR0, 0x00001001); @@ -118,7 +118,7 @@ static void __secure ls1_delay(unsigned int loop) static void __secure ls1_start_fsm(void) { - void *dcsr_epu_base = (void *)(CONFIG_SYS_DCSRBAR + EPU_BLOCK_OFFSET); + void *dcsr_epu_base = (void *)(CFG_SYS_DCSRBAR + EPU_BLOCK_OFFSET); void *ccsr_gic_base = (void *)SYS_FSL_GIC_ADDR; struct ccsr_scfg __iomem *scfg = (void *)CFG_SYS_FSL_SCFG_ADDR; struct ccsr_ddr __iomem *ddr = (void *)CFG_SYS_FSL_DDR_ADDR; diff --git a/arch/arm/cpu/armv7/nonsec_virt.S b/arch/arm/cpu/armv7/nonsec_virt.S index 39aeeb423f..9004074da2 100644 --- a/arch/arm/cpu/armv7/nonsec_virt.S +++ b/arch/arm/cpu/armv7/nonsec_virt.S @@ -112,8 +112,8 @@ ENTRY(_do_nonsec_entry) ENDPROC(_do_nonsec_entry) .macro get_cbar_addr addr -#ifdef CONFIG_ARM_GIC_BASE_ADDRESS - ldr \addr, =CONFIG_ARM_GIC_BASE_ADDRESS +#ifdef CFG_ARM_GIC_BASE_ADDRESS + ldr \addr, =CFG_ARM_GIC_BASE_ADDRESS #else mrc p15, 4, \addr, c15, c0, 0 @ read CBAR bfc \addr, #0, #15 @ clear reserved bits @@ -205,11 +205,11 @@ ENTRY(_nonsec_init) bx lr ENDPROC(_nonsec_init) -#ifdef CONFIG_SMP_PEN_ADDR +#ifdef CFG_SMP_PEN_ADDR /* void __weak smp_waitloop(unsigned previous_address); */ -ENTRY(smp_waitloop) +WEAK(smp_waitloop) wfi - ldr r1, =CONFIG_SMP_PEN_ADDR @ load start address + ldr r1, =CFG_SMP_PEN_ADDR @ load start address ldr r1, [r1] #ifdef CONFIG_PEN_ADDR_BIG_ENDIAN rev r1, r1 @@ -219,7 +219,6 @@ ENTRY(smp_waitloop) mov r0, r1 b _do_nonsec_entry ENDPROC(smp_waitloop) -.weak smp_waitloop #endif .popsection diff --git a/arch/arm/cpu/armv7/psci.S b/arch/arm/cpu/armv7/psci.S index 983cd90442..6c066e50d9 100644 --- a/arch/arm/cpu/armv7/psci.S +++ b/arch/arm/cpu/armv7/psci.S @@ -36,34 +36,32 @@ _psci_vectors: b default_psci_vector @ irq b psci_fiq_enter @ fiq -ENTRY(psci_fiq_enter) +WEAK(psci_fiq_enter) movs pc, lr ENDPROC(psci_fiq_enter) -.weak psci_fiq_enter -ENTRY(default_psci_vector) +WEAK(default_psci_vector) movs pc, lr ENDPROC(default_psci_vector) -.weak default_psci_vector - -ENTRY(psci_version) -ENTRY(psci_cpu_suspend) -ENTRY(psci_cpu_off) -ENTRY(psci_cpu_on) -ENTRY(psci_affinity_info) -ENTRY(psci_migrate) -ENTRY(psci_migrate_info_type) -ENTRY(psci_migrate_info_up_cpu) -ENTRY(psci_system_off) -ENTRY(psci_system_reset) -ENTRY(psci_features) -ENTRY(psci_cpu_freeze) -ENTRY(psci_cpu_default_suspend) -ENTRY(psci_node_hw_state) -ENTRY(psci_system_suspend) -ENTRY(psci_set_suspend_mode) -ENTRY(psi_stat_residency) -ENTRY(psci_stat_count) + +WEAK(psci_version) +WEAK(psci_cpu_suspend) +WEAK(psci_cpu_off) +WEAK(psci_cpu_on) +WEAK(psci_affinity_info) +WEAK(psci_migrate) +WEAK(psci_migrate_info_type) +WEAK(psci_migrate_info_up_cpu) +WEAK(psci_system_off) +WEAK(psci_system_reset) +WEAK(psci_features) +WEAK(psci_cpu_freeze) +WEAK(psci_cpu_default_suspend) +WEAK(psci_node_hw_state) +WEAK(psci_system_suspend) +WEAK(psci_set_suspend_mode) +WEAK(psi_stat_residency) +WEAK(psci_stat_count) mov r0, #ARM_PSCI_RET_NI @ Return -1 (Not Implemented) mov pc, lr ENDPROC(psci_stat_count) @@ -84,24 +82,6 @@ ENDPROC(psci_cpu_on) ENDPROC(psci_cpu_off) ENDPROC(psci_cpu_suspend) ENDPROC(psci_version) -.weak psci_version -.weak psci_cpu_suspend -.weak psci_cpu_off -.weak psci_cpu_on -.weak psci_affinity_info -.weak psci_migrate -.weak psci_migrate_info_type -.weak psci_migrate_info_up_cpu -.weak psci_system_off -.weak psci_system_reset -.weak psci_features -.weak psci_cpu_freeze -.weak psci_cpu_default_suspend -.weak psci_node_hw_state -.weak psci_system_suspend -.weak psci_set_suspend_mode -.weak psi_stat_residency -.weak psci_stat_count _psci_table: .word ARM_PSCI_FN_CPU_SUSPEND @@ -179,12 +159,11 @@ _smc_psci: movs pc, lr @ Return to the kernel @ Requires dense and single-cluster CPU ID space -ENTRY(psci_get_cpu_id) +WEAK(psci_get_cpu_id) mrc p15, 0, r0, c0, c0, 5 /* read MPIDR */ and r0, r0, #0xff /* return CPU ID in cluster */ bx lr ENDPROC(psci_get_cpu_id) -.weak psci_get_cpu_id /* Imported from Linux kernel */ ENTRY(psci_v7_flush_dcache_all) @@ -236,7 +215,7 @@ finished: bx lr ENDPROC(psci_v7_flush_dcache_all) -ENTRY(psci_disable_smp) +WEAK(psci_disable_smp) mrc p15, 0, r0, c1, c0, 1 @ ACTLR bic r0, r0, #(1 << 6) @ Clear SMP bit mcr p15, 0, r0, c1, c0, 1 @ ACTLR @@ -244,16 +223,14 @@ ENTRY(psci_disable_smp) dsb bx lr ENDPROC(psci_disable_smp) -.weak psci_disable_smp -ENTRY(psci_enable_smp) +WEAK(psci_enable_smp) mrc p15, 0, r0, c1, c0, 1 @ ACTLR orr r0, r0, #(1 << 6) @ Set SMP bit mcr p15, 0, r0, c1, c0, 1 @ ACTLR isb bx lr ENDPROC(psci_enable_smp) -.weak psci_enable_smp ENTRY(psci_cpu_off_common) push {lr} @@ -316,15 +293,13 @@ ENTRY(psci_stack_setup) bx r6 ENDPROC(psci_stack_setup) -ENTRY(psci_arch_init) +WEAK(psci_arch_init) mov pc, lr ENDPROC(psci_arch_init) -.weak psci_arch_init -ENTRY(psci_arch_cpu_entry) +WEAK(psci_arch_cpu_entry) mov pc, lr ENDPROC(psci_arch_cpu_entry) -.weak psci_arch_cpu_entry ENTRY(psci_cpu_entry) bl psci_enable_smp diff --git a/arch/arm/cpu/armv7/s5p-common/pwm.c b/arch/arm/cpu/armv7/s5p-common/pwm.c index aef2e5574b..5068327d3c 100644 --- a/arch/arm/cpu/armv7/s5p-common/pwm.c +++ b/arch/arm/cpu/armv7/s5p-common/pwm.c @@ -7,12 +7,11 @@ #include <common.h> #include <errno.h> -#include <pwm.h> #include <asm/io.h> #include <asm/arch/pwm.h> #include <asm/arch/clk.h> -int pwm_enable(int pwm_id) +int s5p_pwm_enable(int pwm_id) { const struct s5p_timer *pwm = #if defined(CONFIG_ARCH_NEXELL) @@ -30,7 +29,7 @@ int pwm_enable(int pwm_id) return 0; } -void pwm_disable(int pwm_id) +void s5p_pwm_disable(int pwm_id) { const struct s5p_timer *pwm = #if defined(CONFIG_ARCH_NEXELL) @@ -92,7 +91,7 @@ static unsigned long pwm_calc_tin(int pwm_id, unsigned long freq) #define NS_IN_SEC 1000000000UL -int pwm_config(int pwm_id, int duty_ns, int period_ns) +int s5p_pwm_config(int pwm_id, int duty_ns, int period_ns) { const struct s5p_timer *pwm = #if defined(CONFIG_ARCH_NEXELL) @@ -157,7 +156,7 @@ int pwm_config(int pwm_id, int duty_ns, int period_ns) return 0; } -int pwm_init(int pwm_id, int div, int invert) +int s5p_pwm_init(int pwm_id, int div, int invert) { u32 val; const struct s5p_timer *pwm = @@ -219,7 +218,7 @@ int pwm_init(int pwm_id, int div, int invert) val |= TCON_INVERTER(pwm_id); writel(val, &pwm->tcon); - pwm_enable(pwm_id); + s5p_pwm_enable(pwm_id); return 0; } diff --git a/arch/arm/cpu/armv7/s5p-common/timer.c b/arch/arm/cpu/armv7/s5p-common/timer.c index 8533d04878..f4a045e2f0 100644 --- a/arch/arm/cpu/armv7/s5p-common/timer.c +++ b/arch/arm/cpu/armv7/s5p-common/timer.c @@ -16,10 +16,6 @@ #include <asm/arch/clk.h> #include <linux/delay.h> -/* Use the old PWM interface for now */ -#undef CONFIG_DM_PWM -#include <pwm.h> - DECLARE_GLOBAL_DATA_PTR; unsigned long get_current_tick(void); @@ -49,9 +45,9 @@ static unsigned long timer_get_us_down(void) int timer_init(void) { /* PWM Timer 4 */ - pwm_init(4, MUX_DIV_4, 0); - pwm_config(4, 100000, 100000); - pwm_enable(4); + s5p_pwm_init(4, MUX_DIV_4, 0); + s5p_pwm_config(4, 100000, 100000); + s5p_pwm_enable(4); /* Use this as the current monotonic time in us */ gd->arch.timer_reset_value = 0; diff --git a/arch/arm/cpu/armv7/s5p4418/cpu.c b/arch/arm/cpu/armv7/s5p4418/cpu.c index 3baa761ec7..fcaafc0ff7 100644 --- a/arch/arm/cpu/armv7/s5p4418/cpu.c +++ b/arch/arm/cpu/armv7/s5p4418/cpu.c @@ -13,10 +13,8 @@ #include <asm/io.h> #include <asm/arch/nexell.h> #include <asm/arch/clk.h> -#include <asm/arch/reset.h> #include <asm/arch/tieoff.h> #include <cpu_func.h> -#include <linux/delay.h> DECLARE_GLOBAL_DATA_PTR; @@ -45,39 +43,12 @@ static void cpu_soc_init(void) nx_tieoff_set(NX_TIEOFF_CORTEXA9MP_TOP_QUADL2C_L2RET1N_1, 1); } -#ifdef CONFIG_PL011_SERIAL -static void serial_device_init(void) -{ - char dev[10]; - int id; - - sprintf(dev, "nx-uart.%d", CONFIG_CONS_INDEX); - id = RESET_ID_UART0 + CONFIG_CONS_INDEX; - - struct clk *clk = clk_get((const char *)dev); - - /* reset control: Low active ___|--- */ - nx_rstcon_setrst(id, RSTCON_ASSERT); - udelay(10); - nx_rstcon_setrst(id, RSTCON_NEGATE); - udelay(10); - - /* set clock */ - clk_disable(clk); - clk_set_rate(clk, CONFIG_PL011_CLOCK); - clk_enable(clk); -} -#endif - int arch_cpu_init(void) { flush_dcache_all(); cpu_soc_init(); clk_init(); - if (IS_ENABLED(CONFIG_PL011_SERIAL)) - serial_device_init(); - return 0; } diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S index 4f6327fe3a..7d7aac021e 100644 --- a/arch/arm/cpu/armv7/start.S +++ b/arch/arm/cpu/armv7/start.S @@ -151,16 +151,14 @@ ENDPROC(c_runtime_cpu_setup) * Don't save anything to stack even if compiled with -O0 * *************************************************************************/ -ENTRY(save_boot_params) +WEAK(save_boot_params) b save_boot_params_ret @ back to my caller ENDPROC(save_boot_params) - .weak save_boot_params #ifdef CONFIG_ARMV7_LPAE -ENTRY(switch_to_hypervisor) +WEAK(switch_to_hypervisor) b switch_to_hypervisor_ret ENDPROC(switch_to_hypervisor) - .weak switch_to_hypervisor #endif /************************************************************************* diff --git a/arch/arm/cpu/armv7/stv0991/timer.c b/arch/arm/cpu/armv7/stv0991/timer.c index 67764ccf66..f7cc45772f 100644 --- a/arch/arm/cpu/armv7/stv0991/timer.c +++ b/arch/arm/cpu/armv7/stv0991/timer.c @@ -18,7 +18,7 @@ static struct stv0991_cgu_regs *const stv0991_cgu_regs = \ (struct stv0991_cgu_regs *) (CGU_BASE_ADDR); #define READ_TIMER() (readl(&gpt1_regs_ptr->cnt) & GPT_FREE_RUNNING) -#define GPT_RESOLUTION (CONFIG_SYS_HZ_CLOCK / CONFIG_SYS_HZ) +#define GPT_RESOLUTION (CFG_SYS_HZ_CLOCK / CONFIG_SYS_HZ) DECLARE_GLOBAL_DATA_PTR; @@ -67,7 +67,7 @@ void __udelay(unsigned long usec) { ulong tmo; ulong start = get_timer_masked(); - ulong tenudelcnt = CONFIG_SYS_HZ_CLOCK / (1000 * 100); + ulong tenudelcnt = CFG_SYS_HZ_CLOCK / (1000 * 100); ulong rndoff; rndoff = (usec % 10) ? 1 : 0; diff --git a/arch/arm/cpu/armv7/virt-v7.c b/arch/arm/cpu/armv7/virt-v7.c index 5ffeca13d9..c82b215b6f 100644 --- a/arch/arm/cpu/armv7/virt-v7.c +++ b/arch/arm/cpu/armv7/virt-v7.c @@ -26,8 +26,8 @@ static unsigned int read_id_pfr1(void) static unsigned long get_gicd_base_address(void) { -#ifdef CONFIG_ARM_GIC_BASE_ADDRESS - return CONFIG_ARM_GIC_BASE_ADDRESS + GIC_DIST_OFFSET; +#ifdef CFG_ARM_GIC_BASE_ADDRESS + return CFG_ARM_GIC_BASE_ADDRESS + GIC_DIST_OFFSET; #else unsigned periphbase; diff --git a/arch/arm/cpu/armv7m/systick-timer.c b/arch/arm/cpu/armv7m/systick-timer.c index 556eaf8c74..c30af4ff7a 100644 --- a/arch/arm/cpu/armv7m/systick-timer.c +++ b/arch/arm/cpu/armv7m/systick-timer.c @@ -18,7 +18,7 @@ * The number of reference clock ticks that correspond to 10ms is normally * defined in the SysTick Calibration register's TENMS field. However, on some * devices this is wrong, so this driver allows the clock rate to be defined - * using CONFIG_SYS_HZ_CLOCK. + * using CFG_SYS_HZ_CLOCK. */ #include <common.h> @@ -76,10 +76,10 @@ int timer_init(void) /* * If the TENMS field is inexact or wrong, specify the clock rate using - * CONFIG_SYS_HZ_CLOCK. + * CFG_SYS_HZ_CLOCK. */ -#if defined(CONFIG_SYS_HZ_CLOCK) - gd->arch.timer_rate_hz = CONFIG_SYS_HZ_CLOCK; +#if defined(CFG_SYS_HZ_CLOCK) + gd->arch.timer_rate_hz = CFG_SYS_HZ_CLOCK; #else gd->arch.timer_rate_hz = (cal & SYSTICK_CAL_TENMS_MASK) * 100; #endif diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index ebca11d174..9656c52e95 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -29,6 +29,7 @@ config ARCH_LS1028A select ESBC_HDR_LS if CHAIN_OF_TRUST select FSL_LAYERSCAPE select FSL_LSCH3 + select FSL_TZASC_400 select GICV3 select NXP_LSCH3_2 select SYS_FSL_HAS_CCI400 @@ -69,6 +70,7 @@ config ARCH_LS1043A select GICV2 select HAS_FSL_XHCI_USB if USB_HOST select SKIP_LOWLEVEL_INIT + select SYS_DPAA_FMAN select SYS_FSL_SRDS_1 select SYS_HAS_SERDES select SYS_FSL_DDR @@ -106,6 +108,7 @@ config ARCH_LS1046A select GICV2 select HAS_FSL_XHCI_USB if USB_HOST select SKIP_LOWLEVEL_INIT + select SYS_DPAA_FMAN select SYS_FSL_SRDS_1 select SYS_HAS_SERDES select SYS_FSL_DDR diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index c11341a1d3..5c45c2a5ed 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -114,7 +114,7 @@ static struct mm_region early_map[] = { CONFIG_SYS_FSL_IFC_SIZE1 - CONFIG_SYS_FSL_IFC_SIZE1_1, PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE }, - { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FSL_IFC_BASE1, + { CFG_SYS_FLASH_BASE, CONFIG_SYS_FSL_IFC_BASE1, CONFIG_SYS_FSL_IFC_SIZE1, PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE }, @@ -130,9 +130,9 @@ static struct mm_region early_map[] = { PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS }, #ifdef CONFIG_FSL_IFC - /* Map IFC region #2 up to CONFIG_SYS_FLASH_BASE for NAND boot */ + /* Map IFC region #2 up to CFG_SYS_FLASH_BASE for NAND boot */ { CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2, - CONFIG_SYS_FLASH_BASE - CONFIG_SYS_FSL_IFC_BASE2, + CFG_SYS_FLASH_BASE - CONFIG_SYS_FSL_IFC_BASE2, PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE }, #endif @@ -257,26 +257,26 @@ static struct mm_region final_map[] = { PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, - { CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR, - CONFIG_SYS_PCIE1_PHYS_SIZE, + { CFG_SYS_PCIE1_PHYS_ADDR, CFG_SYS_PCIE1_PHYS_ADDR, + CFG_SYS_PCIE1_PHYS_SIZE, PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, - { CONFIG_SYS_PCIE2_PHYS_ADDR, CONFIG_SYS_PCIE2_PHYS_ADDR, - CONFIG_SYS_PCIE2_PHYS_SIZE, + { CFG_SYS_PCIE2_PHYS_ADDR, CFG_SYS_PCIE2_PHYS_ADDR, + CFG_SYS_PCIE2_PHYS_SIZE, PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, -#ifdef CONFIG_SYS_PCIE3_PHYS_ADDR - { CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR, - CONFIG_SYS_PCIE3_PHYS_SIZE, +#ifdef CFG_SYS_PCIE3_PHYS_ADDR + { CFG_SYS_PCIE3_PHYS_ADDR, CFG_SYS_PCIE3_PHYS_ADDR, + CFG_SYS_PCIE3_PHYS_SIZE, PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, #endif -#ifdef CONFIG_SYS_PCIE4_PHYS_ADDR - { CONFIG_SYS_PCIE4_PHYS_ADDR, CONFIG_SYS_PCIE4_PHYS_ADDR, - CONFIG_SYS_PCIE4_PHYS_SIZE, +#ifdef CFG_SYS_PCIE4_PHYS_ADDR + { CFG_SYS_PCIE4_PHYS_ADDR, CFG_SYS_PCIE4_PHYS_ADDR, + CFG_SYS_PCIE4_PHYS_SIZE, PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, @@ -368,19 +368,19 @@ static struct mm_region final_map[] = { PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS }, - { CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR, - CONFIG_SYS_PCIE1_PHYS_SIZE, + { CFG_SYS_PCIE1_PHYS_ADDR, CFG_SYS_PCIE1_PHYS_ADDR, + CFG_SYS_PCIE1_PHYS_SIZE, PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, - { CONFIG_SYS_PCIE2_PHYS_ADDR, CONFIG_SYS_PCIE2_PHYS_ADDR, - CONFIG_SYS_PCIE2_PHYS_SIZE, + { CFG_SYS_PCIE2_PHYS_ADDR, CFG_SYS_PCIE2_PHYS_ADDR, + CFG_SYS_PCIE2_PHYS_SIZE, PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, -#ifdef CONFIG_SYS_PCIE3_PHYS_ADDR - { CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR, - CONFIG_SYS_PCIE3_PHYS_SIZE, +#ifdef CFG_SYS_PCIE3_PHYS_ADDR + { CFG_SYS_PCIE3_PHYS_ADDR, CFG_SYS_PCIE3_PHYS_ADDR, + CFG_SYS_PCIE3_PHYS_SIZE, PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, @@ -391,7 +391,7 @@ static struct mm_region final_map[] = { PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS }, #endif -#ifdef CONFIG_SYS_MEM_RESERVE_SECURE +#ifdef CFG_SYS_MEM_RESERVE_SECURE {}, /* space holder for secure mem */ #endif {}, @@ -445,7 +445,7 @@ static inline void early_mmu_setup(void) if (el == 3) gd->arch.tlb_addr = CFG_SYS_FSL_OCRAM_BASE; else - gd->arch.tlb_addr = CONFIG_SYS_DDR_SDRAM_BASE; + gd->arch.tlb_addr = CFG_SYS_DDR_SDRAM_BASE; gd->arch.tlb_fillptr = gd->arch.tlb_addr; gd->arch.tlb_size = EARLY_PGTABLE_SIZE; @@ -477,25 +477,25 @@ static void fix_pcie_mmu_map(void) (ver == SVR_LS2081A) || (ver == SVR_LS2041A)) { for (i = 0; i < ARRAY_SIZE(final_map); i++) { switch (final_map[i].phys) { - case CONFIG_SYS_PCIE1_PHYS_ADDR: + case CFG_SYS_PCIE1_PHYS_ADDR: final_map[i].phys = 0x2000000000ULL; final_map[i].virt = 0x2000000000ULL; final_map[i].size = 0x800000000ULL; break; - case CONFIG_SYS_PCIE2_PHYS_ADDR: + case CFG_SYS_PCIE2_PHYS_ADDR: final_map[i].phys = 0x2800000000ULL; final_map[i].virt = 0x2800000000ULL; final_map[i].size = 0x800000000ULL; break; -#ifdef CONFIG_SYS_PCIE3_PHYS_ADDR - case CONFIG_SYS_PCIE3_PHYS_ADDR: +#ifdef CFG_SYS_PCIE3_PHYS_ADDR + case CFG_SYS_PCIE3_PHYS_ADDR: final_map[i].phys = 0x3000000000ULL; final_map[i].virt = 0x3000000000ULL; final_map[i].size = 0x800000000ULL; break; #endif -#ifdef CONFIG_SYS_PCIE4_PHYS_ADDR - case CONFIG_SYS_PCIE4_PHYS_ADDR: +#ifdef CFG_SYS_PCIE4_PHYS_ADDR + case CFG_SYS_PCIE4_PHYS_ADDR: final_map[i].phys = 0x3800000000ULL; final_map[i].virt = 0x3800000000ULL; final_map[i].size = 0x800000000ULL; @@ -568,7 +568,7 @@ static inline void final_mmu_setup(void) } } -#ifdef CONFIG_SYS_MEM_RESERVE_SECURE +#ifdef CFG_SYS_MEM_RESERVE_SECURE if (gd->arch.secure_ram & MEM_RESERVE_SECURE_MAINTAINED) { if (el == 3) { /* @@ -580,7 +580,7 @@ static inline void final_mmu_setup(void) gd->arch.tlb_addr = gd->arch.secure_ram & ~0xfff; final_map[index].virt = gd->arch.secure_ram & ~0x3; final_map[index].phys = final_map[index].virt; - final_map[index].size = CONFIG_SYS_MEM_RESERVE_SECURE; + final_map[index].size = CFG_SYS_MEM_RESERVE_SECURE; final_map[index].attrs = PTE_BLOCK_OUTER_SHARE; gd->arch.secure_ram |= MEM_RESERVE_SECURE_SECURED; tlb_addr_save = gd->arch.tlb_addr; @@ -1058,9 +1058,6 @@ int cpu_eth_init(struct bd_info *bis) #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD) error = fsl_mc_ldpaa_init(bis); #endif -#ifdef CONFIG_FMAN_ENET - fm_standard_init(bis); -#endif return error; } @@ -1311,22 +1308,22 @@ phys_size_t get_effective_memsize(void) * allocated from first region. If the memory extends to the second * region (or the third region if applicable), Management Complex (MC) * memory should be put into the highest region, i.e. the end of DDR - * memory. CONFIG_MAX_MEM_MAPPED is set to the size of first region so + * memory. CFG_MAX_MEM_MAPPED is set to the size of first region so * U-Boot doesn't relocate itself into higher address. Should DDR be * configured to skip the first region, this function needs to be * adjusted. */ - if (gd->ram_size > CONFIG_MAX_MEM_MAPPED) { - ea_size = CONFIG_MAX_MEM_MAPPED; + if (gd->ram_size > CFG_MAX_MEM_MAPPED) { + ea_size = CFG_MAX_MEM_MAPPED; rem = gd->ram_size - ea_size; } else { ea_size = gd->ram_size; } -#ifdef CONFIG_SYS_MEM_RESERVE_SECURE +#ifdef CFG_SYS_MEM_RESERVE_SECURE /* Check if we have enough space for secure memory */ - if (ea_size > CONFIG_SYS_MEM_RESERVE_SECURE) - ea_size -= CONFIG_SYS_MEM_RESERVE_SECURE; + if (ea_size > CFG_SYS_MEM_RESERVE_SECURE) + ea_size -= CFG_SYS_MEM_RESERVE_SECURE; else printf("Error: No enough space for secure memory.\n"); #endif @@ -1433,7 +1430,7 @@ int dram_init_banksize(void) * gd->arch.secure_ram should be done to avoid running it repeatedly. */ -#ifdef CONFIG_SYS_MEM_RESERVE_SECURE +#ifdef CFG_SYS_MEM_RESERVE_SECURE if (gd->arch.secure_ram & MEM_RESERVE_SECURE_MAINTAINED) { debug("No need to run again, skip %s\n", __func__); @@ -1441,12 +1438,12 @@ int dram_init_banksize(void) } #endif - gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; - if (gd->ram_size > CONFIG_SYS_DDR_BLOCK1_SIZE) { - gd->bd->bi_dram[0].size = CONFIG_SYS_DDR_BLOCK1_SIZE; - gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE; + gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; + if (gd->ram_size > CFG_SYS_DDR_BLOCK1_SIZE) { + gd->bd->bi_dram[0].size = CFG_SYS_DDR_BLOCK1_SIZE; + gd->bd->bi_dram[1].start = CFG_SYS_DDR_BLOCK2_BASE; gd->bd->bi_dram[1].size = gd->ram_size - - CONFIG_SYS_DDR_BLOCK1_SIZE; + CFG_SYS_DDR_BLOCK1_SIZE; #ifdef CONFIG_SYS_DDR_BLOCK3_BASE if (gd->bi_dram[1].size > CONFIG_SYS_DDR_BLOCK2_SIZE) { gd->bd->bi_dram[2].start = CONFIG_SYS_DDR_BLOCK3_BASE; @@ -1458,17 +1455,17 @@ int dram_init_banksize(void) } else { gd->bd->bi_dram[0].size = gd->ram_size; } -#ifdef CONFIG_SYS_MEM_RESERVE_SECURE +#ifdef CFG_SYS_MEM_RESERVE_SECURE if (gd->bd->bi_dram[0].size > - CONFIG_SYS_MEM_RESERVE_SECURE) { + CFG_SYS_MEM_RESERVE_SECURE) { gd->bd->bi_dram[0].size -= - CONFIG_SYS_MEM_RESERVE_SECURE; + CFG_SYS_MEM_RESERVE_SECURE; gd->arch.secure_ram = gd->bd->bi_dram[0].start + gd->bd->bi_dram[0].size; gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; - gd->ram_size -= CONFIG_SYS_MEM_RESERVE_SECURE; + gd->ram_size -= CFG_SYS_MEM_RESERVE_SECURE; } -#endif /* CONFIG_SYS_MEM_RESERVE_SECURE */ +#endif /* CFG_SYS_MEM_RESERVE_SECURE */ #if defined(CONFIG_RESV_RAM) && !defined(CONFIG_SPL_BUILD) /* Assign memory for MC */ @@ -1520,7 +1517,7 @@ int dram_init_banksize(void) } #endif -#ifdef CONFIG_SYS_MEM_RESERVE_SECURE +#ifdef CFG_SYS_MEM_RESERVE_SECURE debug("%s is called. gd->ram_size is reduced to %lu\n", __func__, (ulong)gd->ram_size); #endif @@ -1571,7 +1568,7 @@ void update_early_mmu_table(void) if (gd->ram_size <= CONFIG_SYS_FSL_DRAM_SIZE1) { mmu_change_region_attr( - CONFIG_SYS_SDRAM_BASE, + CFG_SYS_SDRAM_BASE, gd->ram_size, PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE | @@ -1579,8 +1576,8 @@ void update_early_mmu_table(void) PTE_TYPE_VALID); } else { mmu_change_region_attr( - CONFIG_SYS_SDRAM_BASE, - CONFIG_SYS_DDR_BLOCK1_SIZE, + CFG_SYS_SDRAM_BASE, + CFG_SYS_DDR_BLOCK1_SIZE, PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS | @@ -1589,10 +1586,10 @@ void update_early_mmu_table(void) #ifndef CONFIG_SYS_DDR_BLOCK2_SIZE #error "Missing CONFIG_SYS_DDR_BLOCK2_SIZE" #endif - if (gd->ram_size - CONFIG_SYS_DDR_BLOCK1_SIZE > + if (gd->ram_size - CFG_SYS_DDR_BLOCK1_SIZE > CONFIG_SYS_DDR_BLOCK2_SIZE) { mmu_change_region_attr( - CONFIG_SYS_DDR_BLOCK2_BASE, + CFG_SYS_DDR_BLOCK2_BASE, CONFIG_SYS_DDR_BLOCK2_SIZE, PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE | @@ -1601,7 +1598,7 @@ void update_early_mmu_table(void) mmu_change_region_attr( CONFIG_SYS_DDR_BLOCK3_BASE, gd->ram_size - - CONFIG_SYS_DDR_BLOCK1_SIZE - + CFG_SYS_DDR_BLOCK1_SIZE - CONFIG_SYS_DDR_BLOCK2_SIZE, PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE | @@ -1611,9 +1608,9 @@ void update_early_mmu_table(void) #endif { mmu_change_region_attr( - CONFIG_SYS_DDR_BLOCK2_BASE, + CFG_SYS_DDR_BLOCK2_BASE, gd->ram_size - - CONFIG_SYS_DDR_BLOCK1_SIZE, + CFG_SYS_DDR_BLOCK1_SIZE, PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS | diff --git a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch3 b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch3 index 9119d60ffb..6f3fe7ca6e 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch3 +++ b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch3 @@ -116,10 +116,10 @@ Flash Layout Environment Variables ===================== mcboottimeout: MC boot timeout in milliseconds. If this variable is not defined - the value CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS will be assumed. + the value CFG_SYS_LS_MC_BOOT_TIMEOUT_MS will be assumed. mcmemsize: MC DRAM block size in hex. If this variable is not defined, the value - CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE will be assumed. + CFG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE will be assumed. mcinitcmd: This environment variable is defined to initiate MC and DPL deployment from the location where it is stored(NOR, NAND, SD, SATA, USB)during diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c index ee734577fc..4f91db49ee 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c @@ -646,7 +646,7 @@ void ft_cpu_setup(void *blob, struct bd_info *bd) #ifdef CONFIG_SYS_NS16550 do_fixup_by_compat_u32(blob, "fsl,ns16550", - "clock-frequency", CONFIG_SYS_NS16550_CLK, 1); + "clock-frequency", CFG_SYS_NS16550_CLK, 1); #endif do_fixup_by_path_u32(blob, "/sysclk", "clock-frequency", diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c index 6440ce714f..f18407b6d3 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c @@ -24,11 +24,7 @@ void get_sys_info(struct sys_info *sys_info) /* rcw_tmp is needed to get FMAN clock, or to get cluster group A * mux 2 clock for LS1043A/LS1046A. */ -#if defined(CONFIG_SYS_DPAA_FMAN) || \ - defined(CONFIG_ARCH_LS1046A) || \ - defined(CONFIG_ARCH_LS1043A) - u32 rcw_tmp; -#endif + __maybe_unused u32 rcw_tmp; struct ccsr_clk *clk = (void *)(CFG_SYS_FSL_CLK_ADDR); unsigned int cpu; const u8 core_cplx_pll[8] = { @@ -96,7 +92,7 @@ void get_sys_info(struct sys_info *sys_info) #define HWA_CGA_M1_CLK_SEL 0xe0000000 #define HWA_CGA_M1_CLK_SHIFT 29 -#ifdef CONFIG_SYS_DPAA_FMAN +#if defined(CONFIG_SYS_DPAA_FMAN) && !defined(CONFIG_SPL_BUILD) rcw_tmp = in_be32(&gur->rcwsr[7]); switch ((rcw_tmp & HWA_CGA_M1_CLK_SEL) >> HWA_CGA_M1_CLK_SHIFT) { case 2: diff --git a/arch/arm/cpu/armv8/fsl-layerscape/icid.c b/arch/arm/cpu/armv8/fsl-layerscape/icid.c index e972603f24..ad20d71717 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/icid.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/icid.c @@ -41,7 +41,7 @@ void set_icids(void) /* setup general icid offsets */ set_icid(icid_tbl, icid_tbl_sz); -#ifdef CONFIG_SYS_DPAA_FMAN +#if defined(CONFIG_SYS_DPAA_FMAN) && !defined(CONFIG_SPL_BUILD) set_fman_icids(fman_icid_tbl, fman_icid_tbl_sz); #endif } diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1043_ids.c b/arch/arm/cpu/armv8/fsl-layerscape/ls1043_ids.c index 3bd993bebf..e3c3fc6bfb 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/ls1043_ids.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1043_ids.c @@ -10,7 +10,7 @@ #include <fsl_sec.h> #ifdef CONFIG_SYS_DPAA_QBMAN -struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = { +struct qportal_info qp_info[CFG_SYS_QMAN_NUM_PORTALS] = { SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0), SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0), SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0), @@ -59,7 +59,7 @@ struct icid_id_table icid_tbl[] = { int icid_tbl_sz = ARRAY_SIZE(icid_tbl); -#ifdef CONFIG_SYS_DPAA_FMAN +#if defined(CONFIG_SYS_DPAA_FMAN) && !defined(CONFIG_SPL_BUILD) struct fman_icid_id_table fman_icid_tbl[] = { /* port id, icid */ SET_FMAN_ICID_ENTRY(0x02, FSL_DPAA1_STREAM_ID_END), diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c b/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c index abd847b5be..333d7e2fa2 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c @@ -9,7 +9,7 @@ #include <asm/arch-fsl-layerscape/fsl_portals.h> #ifdef CONFIG_SYS_DPAA_QBMAN -struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = { +struct qportal_info qp_info[CFG_SYS_QMAN_NUM_PORTALS] = { SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0), SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0), SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0), @@ -58,7 +58,7 @@ struct icid_id_table icid_tbl[] = { int icid_tbl_sz = ARRAY_SIZE(icid_tbl); -#ifdef CONFIG_SYS_DPAA_FMAN +#if defined(CONFIG_SYS_DPAA_FMAN) && !defined(CONFIG_SPL_BUILD) struct fman_icid_id_table fman_icid_tbl[] = { /* port id, icid */ SET_FMAN_ICID_ENTRY(0x02, FSL_DPAA1_STREAM_ID_END), diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index 89a6262c12..359cbc0430 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -531,7 +531,7 @@ static void erratum_a010539(void) porsr1 = in_be32(&gur->porsr1); porsr1 &= ~FSL_CHASSIS2_CCSR_PORSR1_RCW_MASK; - out_be32((void *)(CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_PORCR1), + out_be32((void *)(CFG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_PORCR1), porsr1); out_be32((void *)(CFG_SYS_FSL_SCFG_ADDR + 0x1a8), 0xffffffff); #endif @@ -643,8 +643,8 @@ void init_pfe_scfg_dcfg_regs(void) out_be32(&scfg->rd_qos1, (unsigned int)(SCFG_RD_QOS1_PFE1_QOS | SCFG_RD_QOS1_PFE2_QOS)); - ecccr2 = in_be32(CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_ECCCR2); - out_be32((void *)CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_ECCCR2, + ecccr2 = in_be32(CFG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_ECCCR2); + out_be32((void *)CFG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_ECCCR2, ecccr2 | (unsigned int)DISABLE_PFE_ECC); } #endif diff --git a/arch/arm/cpu/armv8/fsl-layerscape/spl.c b/arch/arm/cpu/armv8/fsl-layerscape/spl.c index 3a4b665f24..61fced451e 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/spl.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/spl.c @@ -116,7 +116,7 @@ void board_init_f(ulong dummy) #endif dram_init(); #ifdef CONFIG_SPL_FSL_LS_PPA -#ifndef CONFIG_SYS_MEM_RESERVE_SECURE +#ifndef CFG_SYS_MEM_RESERVE_SECURE #error Need secure RAM for PPA #endif /* diff --git a/arch/arm/cpu/armv8/psci.S b/arch/arm/cpu/armv8/psci.S index 7ffc8dbadb..6aece11987 100644 --- a/arch/arm/cpu/armv8/psci.S +++ b/arch/arm/cpu/armv8/psci.S @@ -12,11 +12,10 @@ /* Default PSCI function, return -1, Not Implemented */ #define PSCI_DEFAULT(__fn) \ - ENTRY(__fn); \ + WEAK(__fn); \ mov w0, #ARM_PSCI_RET_NI; \ ret; \ ENDPROC(__fn); \ - .weak __fn /* PSCI function and ID table definition*/ #define PSCI_TABLE(__id, __fn) \ @@ -207,7 +206,7 @@ handle_smc64: * used for the return value, while in this PSCI environment, X0 usually holds * the SMC function identifier, so X0 should be saved by caller function. */ -ENTRY(psci_get_cpu_id) +WEAK(psci_get_cpu_id) #ifdef CONFIG_ARMV8_PSCI_CPUS_PER_CLUSTER mrs x9, MPIDR_EL1 ubfx x9, x9, #8, #8 @@ -221,7 +220,6 @@ ENTRY(psci_get_cpu_id) add x0, x10, x9 ret ENDPROC(psci_get_cpu_id) -.weak psci_get_cpu_id /* CPU ID input in x0, stack top output in x0*/ LENTRY(psci_get_cpu_stack_top) @@ -261,10 +259,9 @@ handle_sync: * Override this function if custom error handling is * needed for asynchronous aborts */ -ENTRY(plat_error_handler) +WEAK(plat_error_handler) ret ENDPROC(plat_error_handler) -.weak plat_error_handler handle_error: bl psci_get_cpu_id @@ -323,9 +320,8 @@ ENTRY(psci_setup_vectors) ret ENDPROC(psci_setup_vectors) -ENTRY(psci_arch_init) +WEAK(psci_arch_init) ret ENDPROC(psci_arch_init) -.weak psci_arch_init .popsection diff --git a/arch/arm/cpu/armv8/sec_firmware.c b/arch/arm/cpu/armv8/sec_firmware.c index 540436ba02..c0e8726346 100644 --- a/arch/arm/cpu/armv8/sec_firmware.c +++ b/arch/arm/cpu/armv8/sec_firmware.c @@ -198,7 +198,7 @@ static int sec_firmware_load_image(const void *sec_firmware_img, goto out; } -#ifdef CONFIG_SYS_MEM_RESERVE_SECURE +#ifdef CFG_SYS_MEM_RESERVE_SECURE /* * The SEC Firmware must be stored in secure memory. * Append SEC Firmware to secure mmu table. @@ -211,7 +211,7 @@ static int sec_firmware_load_image(const void *sec_firmware_img, sec_firmware_addr = (gd->arch.secure_ram & MEM_RESERVE_SECURE_ADDR_MASK) + gd->arch.tlb_size; #else -#error "The CONFIG_SYS_MEM_RESERVE_SECURE must be defined when enabled SEC Firmware support" +#error "The CFG_SYS_MEM_RESERVE_SECURE must be defined when enabled SEC Firmware support" #endif /* Align SEC Firmware base address to 4K */ diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 43951a7731..b3baaf4829 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -1259,6 +1259,9 @@ dtb-$(CONFIG_SOC_K3_AM642) += k3-am642-evm.dtb \ dtb-$(CONFIG_SOC_K3_AM625) += k3-am625-sk.dtb \ k3-am625-r5-sk.dtb +dtb-$(CONFIG_SOC_K3_AM625) += k3-am62a7-sk.dtb \ + k3-am62a7-r5-sk.dtb + dtb-$(CONFIG_ARCH_MEDIATEK) += \ mt7622-rfb.dtb \ mt7623a-unielec-u7623-02-emmc.dtb \ diff --git a/arch/arm/dts/at91-sam9x60_curiosity.dts b/arch/arm/dts/at91-sam9x60_curiosity.dts index 7c5b6ae2b8..d6ae3d648d 100644 --- a/arch/arm/dts/at91-sam9x60_curiosity.dts +++ b/arch/arm/dts/at91-sam9x60_curiosity.dts @@ -49,6 +49,13 @@ atmel,pins = <AT91_PIOD 14 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>; }; + + usb1 { + pinctrl_usb_default: usb_default { + atmel,pins = <AT91_PIOD 15 AT91_PERIPH_GPIO AT91_PINCTRL_NONE + AT91_PIOD 18 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>; + }; + }; }; }; }; @@ -89,3 +96,17 @@ phy-mode = "rmii"; status = "okay"; }; + +&usb1 { + num-ports = <3>; + atmel,vbus-gpio = <0 + &pioD 15 GPIO_ACTIVE_HIGH + &pioD 18 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_default>; + status = "okay"; +}; + +&usb2 { + status = "okay"; +}; diff --git a/arch/arm/dts/at91-sama5d27_wlsom1_ek.dts b/arch/arm/dts/at91-sama5d27_wlsom1_ek.dts index eec183d5de..6d4b35ea96 100644 --- a/arch/arm/dts/at91-sama5d27_wlsom1_ek.dts +++ b/arch/arm/dts/at91-sama5d27_wlsom1_ek.dts @@ -143,7 +143,32 @@ pinmux = <PIN_PC9__GPIO>; bias-pull-up; }; + + pinctrl_usb_default: usb_default { + pinmux = <PIN_PA10__GPIO>; + bias-disable; + }; + + pinctrl_usba_vbus: usba_vbus { + pinmux = <PIN_PA16__GPIO>; + bias-disable; + }; }; }; }; }; + +&usb1 { + num-ports = <3>; + atmel,vbus-gpio = <0 + &pioA PIN_PA10 GPIO_ACTIVE_HIGH + 0 + >; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_default>; + status = "okay"; +}; + +&usb2 { + status = "okay"; +}; diff --git a/arch/arm/dts/at91-sama5d2_icp.dts b/arch/arm/dts/at91-sama5d2_icp.dts index 2dffae9c5c..4f796c6c94 100644 --- a/arch/arm/dts/at91-sama5d2_icp.dts +++ b/arch/arm/dts/at91-sama5d2_icp.dts @@ -154,7 +154,29 @@ <PIN_PA13__SDMMC0_CD>; bias-disable; }; + + pinctrl_usb_default: usb_default { + pinmux = <PIN_PC17__GPIO>; + bias-disable; + }; + + pinctrl_usba_vbus: usba_vbus { + pinmux = <PIN_PD23__GPIO>; + bias-disable; + }; }; }; }; }; + +&usb1 { + num-ports = <3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_default>; + status = "okay"; +}; + +&usb2 { + phy_type = "hsic"; + status = "okay"; +}; diff --git a/arch/arm/dts/at91-sama7g5ek-u-boot.dtsi b/arch/arm/dts/at91-sama7g5ek-u-boot.dtsi index d294ddb54a..a54cfaccbf 100644 --- a/arch/arm/dts/at91-sama7g5ek-u-boot.dtsi +++ b/arch/arm/dts/at91-sama7g5ek-u-boot.dtsi @@ -10,13 +10,88 @@ * */ +#include "sama7g5-pinfunc.h" +#include <dt-bindings/reset/sama7g5-reset.h> +#include <dt-bindings/clock/at91.h> + / { chosen { u-boot,dm-pre-reloc; }; + utmi { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + usb_phy0: phy@0 { + compatible = "microchip,sama7g5-usb-phy"; + sfr-phandle = <&sfr>; + reg = <0>; + clocks = <&utmi_clk USB_UTMI1>; + clock-names = "utmi_clk"; + status = "disabled"; + #phy-cells = <0>; + }; + + usb_phy1: phy@1 { + compatible = "microchip,sama7g5-usb-phy"; + sfr-phandle = <&sfr>; + reg = <1>; + clocks = <&utmi_clk USB_UTMI2>; + clock-names = "utmi_clk"; + status = "disabled"; + #phy-cells = <0>; + }; + + usb_phy2: phy@2 { + compatible = "microchip,sama7g5-usb-phy"; + sfr-phandle = <&sfr>; + reg = <2>; + clocks = <&utmi_clk USB_UTMI3>; + clock-names = "utmi_clk"; + status = "disabled"; + #phy-cells = <0>; + }; + }; + + utmi_clk: utmi-clk { + compatible = "microchip,sama7g5-utmi-clk"; + sfr-phandle = <&sfr>; + #clock-cells = <1>; + clocks = <&pmc PMC_TYPE_CORE 27>; + clock-names = "utmi_clk"; + resets = <&reset_controller SAMA7G5_RESET_USB_PHY1>, + <&reset_controller SAMA7G5_RESET_USB_PHY2>, + <&reset_controller SAMA7G5_RESET_USB_PHY3>; + reset-names = "usb0_reset", "usb1_reset", "usb2_reset"; + }; + soc { u-boot,dm-pre-reloc; + + usb2: usb@400000 { + compatible = "microchip,sama7g5-ohci", "usb-ohci"; + reg = <0x00400000 0x100000>; + interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 106>, <&utmi_clk USB_UTMI1>, <&usb_clk>; + clock-names = "ohci_clk", "hclk", "uhpck"; + status = "disabled"; + }; + + usb3: usb@500000 { + compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; + reg = <0x00500000 0x100000>; + interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&usb_clk>, <&pmc PMC_TYPE_PERIPHERAL 106>; + clock-names = "usb_clk", "ehci_clk"; + status = "disabled"; + }; + + sfr: sfr@e1624000 { + compatible = "microchip,sama7g5-sfr", "syscon"; + reg = <0xe1624000 0x4000>; + }; }; }; @@ -38,6 +113,11 @@ &pioA { u-boot,dm-pre-reloc; + + pinctrl_usb_default: usb_default { + pinmux = <PIN_PC6__GPIO>; + bias-disable; + }; }; &pit64b0 { @@ -60,3 +140,31 @@ u-boot,dm-pre-reloc; }; +&usb2 { + num-ports = <3>; + atmel,vbus-gpio = <0 + 0 + &pioA PIN_PC6 GPIO_ACTIVE_HIGH + >; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_default>; + phys = <&usb_phy2>; + phy-names = "usb"; + status = "okay"; +}; + +&usb3 { + status = "okay"; +}; + +&usb_phy0 { + status = "okay"; +}; + +&usb_phy1 { + status = "okay"; +}; + +&usb_phy2 { + status = "okay"; +}; diff --git a/arch/arm/dts/at91-sama7g5ek.dts b/arch/arm/dts/at91-sama7g5ek.dts index aed84f15a1..9b247fcaf6 100644 --- a/arch/arm/dts/at91-sama7g5ek.dts +++ b/arch/arm/dts/at91-sama7g5ek.dts @@ -45,13 +45,13 @@ }; }; - gpio_keys { + gpio-keys { compatible = "gpio-keys"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_key_gpio_default>; - bp1 { + button { label = "PB_USER"; gpios = <&pioA PIN_PA12 GPIO_ACTIVE_LOW>; linux,code = <KEY_PROG1>; @@ -244,8 +244,8 @@ regulators { vdd_3v3: VDD_IO { regulator-name = "VDD_IO"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <3700000>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; regulator-initial-mode = <2>; regulator-allowed-modes = <2>, <4>; regulator-always-on; @@ -264,8 +264,8 @@ vddioddr: VDD_DDR { regulator-name = "VDD_DDR"; - regulator-min-microvolt = <1300000>; - regulator-max-microvolt = <1450000>; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; regulator-initial-mode = <2>; regulator-allowed-modes = <2>, <4>; regulator-always-on; @@ -285,8 +285,8 @@ vddcore: VDD_CORE { regulator-name = "VDD_CORE"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1850000>; + regulator-min-microvolt = <1150000>; + regulator-max-microvolt = <1150000>; regulator-initial-mode = <2>; regulator-allowed-modes = <2>, <4>; regulator-always-on; @@ -306,7 +306,7 @@ vddcpu: VDD_OTHER { regulator-name = "VDD_OTHER"; regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1850000>; + regulator-max-microvolt = <1250000>; regulator-initial-mode = <2>; regulator-allowed-modes = <2>, <4>; regulator-ramp-delay = <3125>; @@ -326,8 +326,8 @@ vldo1: LDO1 { regulator-name = "LDO1"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <3700000>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; regulator-always-on; regulator-state-standby { @@ -707,7 +707,6 @@ ck_cd_rstn_vddsel { pinmux = <PIN_PA0__SDMMC0_CK>, <PIN_PA2__SDMMC0_RSTN>, - <PIN_PA14__SDMMC0_CD>, <PIN_PA11__SDMMC0_DS>; slew-rate = <0>; bias-pull-up; diff --git a/arch/arm/dts/k3-am62-main.dtsi b/arch/arm/dts/k3-am62-main.dtsi index 4b6ba98dd0..4a42f1b2e3 100644 --- a/arch/arm/dts/k3-am62-main.dtsi +++ b/arch/arm/dts/k3-am62-main.dtsi @@ -165,6 +165,19 @@ }; }; + crypto: crypto@40900000 { + compatible = "ti,am62-sa3ul"; + reg = <0x00 0x40900000 0x00 0x1200>; + power-domains = <&k3_pds 70 TI_SCI_PD_SHARED>; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x00 0x40900000 0x00 0x40900000 0x00 0x30000>; + + dmas = <&main_pktdma 0xf501 0>, <&main_pktdma 0x7506 0>, + <&main_pktdma 0x7507 0>; + dma-names = "tx", "rx1", "rx2"; + }; + main_pmx0: pinctrl@f4000 { compatible = "pinctrl-single"; reg = <0x00 0xf4000 0x00 0x2ac>; @@ -530,4 +543,45 @@ ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; }; + + ecap0: pwm@23100000 { + compatible = "ti,am3352-ecap"; + #pwm-cells = <3>; + reg = <0x00 0x23100000 0x00 0x100>; + power-domains = <&k3_pds 51 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 51 0>; + clock-names = "fck"; + }; + + ecap1: pwm@23110000 { + compatible = "ti,am3352-ecap"; + #pwm-cells = <3>; + reg = <0x00 0x23110000 0x00 0x100>; + power-domains = <&k3_pds 52 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 52 0>; + clock-names = "fck"; + }; + + ecap2: pwm@23120000 { + compatible = "ti,am3352-ecap"; + #pwm-cells = <3>; + reg = <0x00 0x23120000 0x00 0x100>; + power-domains = <&k3_pds 53 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 53 0>; + clock-names = "fck"; + }; + + main_mcan0: can@20701000 { + compatible = "bosch,m_can"; + reg = <0x00 0x20701000 0x00 0x200>, + <0x00 0x20708000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 98 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 98 6>, <&k3_clks 98 1>; + clock-names = "hclk", "cclk"; + interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + }; }; diff --git a/arch/arm/dts/k3-am62-mcu.dtsi b/arch/arm/dts/k3-am62-mcu.dtsi index d103824c96..f56c803560 100644 --- a/arch/arm/dts/k3-am62-mcu.dtsi +++ b/arch/arm/dts/k3-am62-mcu.dtsi @@ -53,4 +53,32 @@ power-domains = <&k3_pds 148 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 148 0>; }; + + mcu_gpio_intr: interrupt-controller@4210000 { + compatible = "ti,sci-intr"; + reg = <0x00 0x04210000 0x00 0x200>; + ti,intr-trigger-type = <1>; + interrupt-controller; + interrupt-parent = <&gic500>; + #interrupt-cells = <1>; + ti,sci = <&dmsc>; + ti,sci-dev-id = <5>; + ti,interrupt-ranges = <0 104 4>; + }; + + mcu_gpio0: gpio@4201000 { + compatible = "ti,am64-gpio", "ti,keystone-gpio"; + reg = <0x00 0x4201000 0x00 0x100>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&mcu_gpio_intr>; + interrupts = <30>, <31>; + interrupt-controller; + #interrupt-cells = <2>; + ti,ngpio = <24>; + ti,davinci-gpio-unbanked = <0>; + power-domains = <&k3_pds 79 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 79 0>; + clock-names = "gpio"; + }; }; diff --git a/arch/arm/dts/k3-am62.dtsi b/arch/arm/dts/k3-am62.dtsi index bc2997b185..37fcbe7a3c 100644 --- a/arch/arm/dts/k3-am62.dtsi +++ b/arch/arm/dts/k3-am62.dtsi @@ -66,6 +66,7 @@ <0x00 0x30200000 0x00 0x30200000 0x00 0x00010000>, /* DSS */ <0x00 0x31000000 0x00 0x31000000 0x00 0x00050000>, /* USB0 DWC3 Core window */ <0x00 0x31100000 0x00 0x31100000 0x00 0x00050000>, /* USB1 DWC3 Core window */ + <0x00 0x40900000 0x00 0x40900000 0x00 0x00030000>, /* SA3UL */ <0x00 0x43600000 0x00 0x43600000 0x00 0x00010000>, /* SA3 sproxy data */ <0x00 0x44043000 0x00 0x44043000 0x00 0x00000fe0>, /* TI SCI DEBUG */ <0x00 0x44860000 0x00 0x44860000 0x00 0x00040000>, /* SA3 sproxy config */ diff --git a/arch/arm/dts/k3-am625-r5-sk.dts b/arch/arm/dts/k3-am625-r5-sk.dts index 6d696e720d..d39b334ed0 100644 --- a/arch/arm/dts/k3-am625-r5-sk.dts +++ b/arch/arm/dts/k3-am625-r5-sk.dts @@ -155,3 +155,8 @@ status = "okay"; u-boot,dm-spl; }; + +&ospi0 { + reg = <0x00 0x0fc40000 0x00 0x100>, + <0x00 0x60000000 0x00 0x08000000>; +}; diff --git a/arch/arm/dts/k3-am625-sk-u-boot.dtsi b/arch/arm/dts/k3-am625-sk-u-boot.dtsi index 159fa36bbe..92788bae3e 100644 --- a/arch/arm/dts/k3-am625-sk-u-boot.dtsi +++ b/arch/arm/dts/k3-am625-sk-u-boot.dtsi @@ -102,3 +102,27 @@ &main_mmc1_pins_default { u-boot,dm-spl; }; + +&fss { + u-boot,dm-spl; +}; + +&ospi0_pins_default { + u-boot,dm-spl; +}; + +&ospi0 { + u-boot,dm-spl; + + flash@0 { + u-boot,dm-spl; + + partitions { + u-boot,dm-spl; + + partition@3fc0000 { + u-boot,dm-spl; + }; + }; + }; +}; diff --git a/arch/arm/dts/k3-am625-sk.dts b/arch/arm/dts/k3-am625-sk.dts index 76b06ea239..af5617ff44 100644 --- a/arch/arm/dts/k3-am625-sk.dts +++ b/arch/arm/dts/k3-am625-sk.dts @@ -18,7 +18,12 @@ aliases { serial2 = &main_uart0; + mmc0 = &sdhci0; mmc1 = &sdhci1; + mmc2 = &sdhci2; + spi0 = &ospi0; + ethernet0 = &cpsw_port1; + ethernet1 = &cpsw_port2; }; chosen { @@ -38,6 +43,15 @@ #size-cells = <2>; ranges; + ramoops@9ca00000 { + compatible = "ramoops"; + reg = <0x00 0x9ca00000 0x00 0x00100000>; + record-size = <0x8000>; + console-size = <0x8000>; + ftrace-size = <0x00>; + pmsg-size = <0x8000>; + }; + secure_tfa_ddr: tfa@9e780000 { reg = <0x00 0x9e780000 0x00 0x80000>; alignment = <0x1000>; @@ -56,6 +70,79 @@ no-map; }; }; + + vmain_pd: regulator-0 { + /* TPS65988 PD CONTROLLER OUTPUT */ + compatible = "regulator-fixed"; + regulator-name = "vmain_pd"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; + + vcc_5v0: regulator-1 { + /* Output of LM34936 */ + compatible = "regulator-fixed"; + regulator-name = "vcc_5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vmain_pd>; + regulator-always-on; + regulator-boot-on; + }; + + vcc_3v3_sys: regulator-2 { + /* output of LM61460-Q1 */ + compatible = "regulator-fixed"; + regulator-name = "vcc_3v3_sys"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vmain_pd>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_mmc1: regulator-3 { + /* TPS22918DBVR */ + compatible = "regulator-fixed"; + regulator-name = "vdd_mmc1"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + enable-active-high; + vin-supply = <&vcc_3v3_sys>; + gpio = <&exp1 3 GPIO_ACTIVE_HIGH>; + }; + + vdd_sd_dv: regulator-4 { + /* Output of TLV71033 */ + compatible = "regulator-gpio"; + regulator-name = "tlv71033"; + pinctrl-names = "default"; + pinctrl-0 = <&vdd_sd_dv_pins_default>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + vin-supply = <&vcc_5v0>; + gpios = <&main_gpio0 31 GPIO_ACTIVE_HIGH>; + states = <1800000 0x0>, + <3300000 0x1>; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&usr_led_pins_default>; + + led-0 { + label = "am62-sk:green:heartbeat"; + gpios = <&main_gpio1 49 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + function = LED_FUNCTION_HEARTBEAT; + default-state = "off"; + }; + }; }; &main_pmx0 { @@ -66,6 +153,42 @@ >; }; + main_i2c0_pins_default: main-i2c0-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x1e0, PIN_INPUT_PULLUP, 0) /* (B16) I2C0_SCL */ + AM62X_IOPAD(0x1e4, PIN_INPUT_PULLUP, 0) /* (A16) I2C0_SDA */ + >; + }; + + main_i2c1_pins_default: main-i2c1-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x1e8, PIN_INPUT_PULLUP, 0) /* (B17) I2C1_SCL */ + AM62X_IOPAD(0x1ec, PIN_INPUT_PULLUP, 0) /* (A17) I2C1_SDA */ + >; + }; + + main_i2c2_pins_default: main-i2c2-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x0b0, PIN_INPUT_PULLUP, 1) /* (K22) GPMC0_CSn2.I2C2_SCL */ + AM62X_IOPAD(0x0b4, PIN_INPUT_PULLUP, 1) /* (K24) GPMC0_CSn3.I2C2_SDA */ + >; + }; + + main_mmc0_pins_default: main-mmc0-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x220, PIN_INPUT, 0) /* (Y3) MMC0_CMD */ + AM62X_IOPAD(0x218, PIN_INPUT, 0) /* (AB1) MMC0_CLK */ + AM62X_IOPAD(0x214, PIN_INPUT, 0) /* (AA2) MMC0_DAT0 */ + AM62X_IOPAD(0x210, PIN_INPUT, 0) /* (AA1) MMC0_DAT1 */ + AM62X_IOPAD(0x20c, PIN_INPUT, 0) /* (AA3) MMC0_DAT2 */ + AM62X_IOPAD(0x208, PIN_INPUT, 0) /* (Y4) MMC0_DAT3 */ + AM62X_IOPAD(0x204, PIN_INPUT, 0) /* (AB2) MMC0_DAT4 */ + AM62X_IOPAD(0x200, PIN_INPUT, 0) /* (AC1) MMC0_DAT5 */ + AM62X_IOPAD(0x1fc, PIN_INPUT, 0) /* (AD2) MMC0_DAT6 */ + AM62X_IOPAD(0x1f8, PIN_INPUT, 0) /* (AC2) MMC0_DAT7 */ + >; + }; + main_mmc1_pins_default: main-mmc1-pins-default { pinctrl-single,pins = < AM62X_IOPAD(0x23c, PIN_INPUT, 0) /* (A21) MMC1_CMD */ @@ -77,6 +200,81 @@ AM62X_IOPAD(0x240, PIN_INPUT, 0) /* (D17) MMC1_SDCD */ >; }; + + usr_led_pins_default: usr-led-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x244, PIN_OUTPUT, 7) /* (C17) MMC1_SDWP.GPIO1_49 */ + >; + }; + + main_mdio1_pins_default: main-mdio1-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x160, PIN_OUTPUT, 0) /* (AD24) MDIO0_MDC */ + AM62X_IOPAD(0x15c, PIN_INPUT, 0) /* (AB22) MDIO0_MDIO */ + >; + }; + + main_rgmii1_pins_default: main-rgmii1-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x14c, PIN_INPUT, 0) /* (AB17) RGMII1_RD0 */ + AM62X_IOPAD(0x150, PIN_INPUT, 0) /* (AC17) RGMII1_RD1 */ + AM62X_IOPAD(0x154, PIN_INPUT, 0) /* (AB16) RGMII1_RD2 */ + AM62X_IOPAD(0x158, PIN_INPUT, 0) /* (AA15) RGMII1_RD3 */ + AM62X_IOPAD(0x148, PIN_INPUT, 0) /* (AD17) RGMII1_RXC */ + AM62X_IOPAD(0x144, PIN_INPUT, 0) /* (AE17) RGMII1_RX_CTL */ + AM62X_IOPAD(0x134, PIN_OUTPUT, 0) /* (AE20) RGMII1_TD0 */ + AM62X_IOPAD(0x138, PIN_OUTPUT, 0) /* (AD20) RGMII1_TD1 */ + AM62X_IOPAD(0x13c, PIN_OUTPUT, 0) /* (AE18) RGMII1_TD2 */ + AM62X_IOPAD(0x140, PIN_OUTPUT, 0) /* (AD18) RGMII1_TD3 */ + AM62X_IOPAD(0x130, PIN_OUTPUT, 0) /* (AE19) RGMII1_TXC */ + AM62X_IOPAD(0x12c, PIN_OUTPUT, 0) /* (AD19) RGMII1_TX_CTL */ + >; + }; + + main_rgmii2_pins_default: main-rgmii2-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x184, PIN_INPUT, 0) /* (AE23) RGMII2_RD0 */ + AM62X_IOPAD(0x188, PIN_INPUT, 0) /* (AB20) RGMII2_RD1 */ + AM62X_IOPAD(0x18c, PIN_INPUT, 0) /* (AC21) RGMII2_RD2 */ + AM62X_IOPAD(0x190, PIN_INPUT, 0) /* (AE22) RGMII2_RD3 */ + AM62X_IOPAD(0x180, PIN_INPUT, 0) /* (AD23) RGMII2_RXC */ + AM62X_IOPAD(0x17c, PIN_INPUT, 0) /* (AD22) RGMII2_RX_CTL */ + AM62X_IOPAD(0x16c, PIN_OUTPUT, 0) /* (Y18) RGMII2_TD0 */ + AM62X_IOPAD(0x170, PIN_OUTPUT, 0) /* (AA18) RGMII2_TD1 */ + AM62X_IOPAD(0x174, PIN_OUTPUT, 0) /* (AD21) RGMII2_TD2 */ + AM62X_IOPAD(0x178, PIN_OUTPUT, 0) /* (AC20) RGMII2_TD3 */ + AM62X_IOPAD(0x168, PIN_OUTPUT, 0) /* (AE21) RGMII2_TXC */ + AM62X_IOPAD(0x164, PIN_OUTPUT, 0) /* (AA19) RGMII2_TX_CTL */ + >; + }; + + ospi0_pins_default: ospi0-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x000, PIN_OUTPUT, 0) /* (H24) OSPI0_CLK */ + AM62X_IOPAD(0x02c, PIN_OUTPUT, 0) /* (F23) OSPI0_CSn0 */ + AM62X_IOPAD(0x00c, PIN_INPUT, 0) /* (E25) OSPI0_D0 */ + AM62X_IOPAD(0x010, PIN_INPUT, 0) /* (G24) OSPI0_D1 */ + AM62X_IOPAD(0x014, PIN_INPUT, 0) /* (F25) OSPI0_D2 */ + AM62X_IOPAD(0x018, PIN_INPUT, 0) /* (F24) OSPI0_D3 */ + AM62X_IOPAD(0x01c, PIN_INPUT, 0) /* (J23) OSPI0_D4 */ + AM62X_IOPAD(0x020, PIN_INPUT, 0) /* (J25) OSPI0_D5 */ + AM62X_IOPAD(0x024, PIN_INPUT, 0) /* (H25) OSPI0_D6 */ + AM62X_IOPAD(0x028, PIN_INPUT, 0) /* (J22) OSPI0_D7 */ + AM62X_IOPAD(0x008, PIN_INPUT, 0) /* (J24) OSPI0_DQS */ + >; + }; + + vdd_sd_dv_pins_default: vdd-sd-dv-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x07c, PIN_OUTPUT, 7) /* (P25) GPMC0_CLK.GPIO0_31 */ + >; + }; + + main_gpio1_ioexp_intr_pins_default: main-gpio1-ioexp-intr-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x01d4, PIN_INPUT, 7) /* (B15) UART0_RTSn.GPIO1_23 */ + >; + }; }; &wkup_uart0 { @@ -128,10 +326,41 @@ &main_i2c0 { status = "disabled"; + pinctrl-0 = <&main_i2c0_pins_default>; + clock-frequency = <400000>; }; &main_i2c1 { status = "disabled"; + pinctrl-0 = <&main_i2c1_pins_default>; + clock-frequency = <400000>; + + exp1: gpio@22 { + compatible = "ti,tca6424"; + reg = <0x22>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = "GPIO_CPSW2_RST", "GPIO_CPSW1_RST", + "PRU_DETECT", "MMC1_SD_EN", + "VPP_LDO_EN", "EXP_PS_3V3_En", + "EXP_PS_5V0_En", "EXP_HAT_DETECT", + "GPIO_AUD_RSTn", "GPIO_eMMC_RSTn", + "UART1_FET_BUF_EN", "WL_LT_EN", + "GPIO_HDMI_RSTn", "CSI_GPIO1", + "CSI_GPIO2", "PRU_3V3_EN", + "HDMI_INTn", "TEST_GPIO2", + "MCASP1_FET_EN", "MCASP1_BUF_BT_EN", + "MCASP1_FET_SEL", "UART1_FET_SEL", + "TSINT#", "IO_EXP_TEST_LED"; + + interrupt-parent = <&main_gpio1>; + interrupts = <23 IRQ_TYPE_EDGE_FALLING>; + interrupt-controller; + #interrupt-cells = <2>; + + pinctrl-names = "default"; + pinctrl-0 = <&main_gpio1_ioexp_intr_pins_default>; + }; }; &main_i2c2 { @@ -142,9 +371,134 @@ status = "disabled"; }; +&sdhci0 { + pinctrl-names = "default"; + pinctrl-0 = <&main_mmc0_pins_default>; + ti,driver-strength-ohm = <50>; + disable-wp; +}; + &sdhci1 { + /* SD/MMC */ + vmmc-supply = <&vdd_mmc1>; + vqmmc-supply = <&vdd_sd_dv>; pinctrl-names = "default"; pinctrl-0 = <&main_mmc1_pins_default>; ti,driver-strength-ohm = <50>; disable-wp; }; + +&cpsw3g { + pinctrl-names = "default"; + pinctrl-0 = <&main_mdio1_pins_default + &main_rgmii1_pins_default + &main_rgmii2_pins_default>; +}; + +&cpsw_port1 { + phy-mode = "rgmii-rxid"; + phy-handle = <&cpsw3g_phy0>; +}; + +&cpsw_port2 { + phy-mode = "rgmii-rxid"; + phy-handle = <&cpsw3g_phy1>; +}; + +&cpsw3g_mdio { + cpsw3g_phy0: ethernet-phy@0 { + reg = <0>; + ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; + ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; + ti,min-output-impedance; + }; + + cpsw3g_phy1: ethernet-phy@1 { + reg = <1>; + ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; + ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; + ti,min-output-impedance; + }; +}; + +&mailbox0_cluster0 { + mbox_m4_0: mbox-m4-0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; +}; + +&ospi0 { + pinctrl-names = "default"; + pinctrl-0 = <&ospi0_pins_default>; + + flash@0{ + compatible = "jedec,spi-nor"; + reg = <0x0>; + spi-tx-bus-width = <8>; + spi-rx-bus-width = <8>; + spi-max-frequency = <25000000>; + cdns,tshsl-ns = <60>; + cdns,tsd2d-ns = <60>; + cdns,tchsh-ns = <60>; + cdns,tslch-ns = <60>; + cdns,read-delay = <4>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "ospi.tiboot3"; + reg = <0x0 0x80000>; + }; + + partition@80000 { + label = "ospi.tispl"; + reg = <0x80000 0x200000>; + }; + + partition@280000 { + label = "ospi.u-boot"; + reg = <0x280000 0x400000>; + }; + + partition@680000 { + label = "ospi.env"; + reg = <0x680000 0x40000>; + }; + + partition@6c0000 { + label = "ospi.env.backup"; + reg = <0x6c0000 0x40000>; + }; + + partition@800000 { + label = "ospi.rootfs"; + reg = <0x800000 0x37c0000>; + }; + + partition@3fc0000 { + label = "ospi.phypattern"; + reg = <0x3fc0000 0x40000>; + }; + }; + }; +}; + +&ecap0 { + status = "disabled"; +}; + +&ecap1 { + status = "disabled"; +}; + +&ecap2 { + status = "disabled"; +}; + +&main_mcan0 { + status = "disabled"; +}; diff --git a/arch/arm/dts/k3-am62a-ddr-1866mhz-32bit.dtsi b/arch/arm/dts/k3-am62a-ddr-1866mhz-32bit.dtsi new file mode 100644 index 0000000000..9f50d7eae6 --- /dev/null +++ b/arch/arm/dts/k3-am62a-ddr-1866mhz-32bit.dtsi @@ -0,0 +1,2798 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * This file was generated with the + * AM62A SysConfig DDR Subsystem Register Configuration Tool v0.09.01 + * Wed Aug 10 2022 17:34:54 GMT-0500 (Central Daylight Time) + * DDR Type: LPDDR4 + * F0 = 50MHz F1 = NA F2 = 1866MHz + * Density (per channel): 8Gb + * Number of Ranks: 2 + */ + +#define DDRSS_PLL_FHS_CNT 5 +#define DDRSS_PLL_FREQUENCY_1 933000000 +#define DDRSS_PLL_FREQUENCY_2 933000000 + +#define DDRSS_CTL_0_DATA 0x00000B00 +#define DDRSS_CTL_1_DATA 0x00000000 +#define DDRSS_CTL_2_DATA 0x00000000 +#define DDRSS_CTL_3_DATA 0x00000000 +#define DDRSS_CTL_4_DATA 0x00000000 +#define DDRSS_CTL_5_DATA 0x00000000 +#define DDRSS_CTL_6_DATA 0x00000000 +#define DDRSS_CTL_7_DATA 0x00002710 +#define DDRSS_CTL_8_DATA 0x000186A0 +#define DDRSS_CTL_9_DATA 0x00000005 +#define DDRSS_CTL_10_DATA 0x00000064 +#define DDRSS_CTL_11_DATA 0x0005B18F +#define DDRSS_CTL_12_DATA 0x0038EF90 +#define DDRSS_CTL_13_DATA 0x00000005 +#define DDRSS_CTL_14_DATA 0x00000E94 +#define DDRSS_CTL_15_DATA 0x0005B18F +#define DDRSS_CTL_16_DATA 0x0038EF90 +#define DDRSS_CTL_17_DATA 0x00000005 +#define DDRSS_CTL_18_DATA 0x00000E94 +#define DDRSS_CTL_19_DATA 0x01010100 +#define DDRSS_CTL_20_DATA 0x01010100 +#define DDRSS_CTL_21_DATA 0x01000110 +#define DDRSS_CTL_22_DATA 0x02010002 +#define DDRSS_CTL_23_DATA 0x0000000A +#define DDRSS_CTL_24_DATA 0x000186A0 +#define DDRSS_CTL_25_DATA 0x00000000 +#define DDRSS_CTL_26_DATA 0x00000000 +#define DDRSS_CTL_27_DATA 0x00000000 +#define DDRSS_CTL_28_DATA 0x00000000 +#define DDRSS_CTL_29_DATA 0x00020200 +#define DDRSS_CTL_30_DATA 0x00000000 +#define DDRSS_CTL_31_DATA 0x00000000 +#define DDRSS_CTL_32_DATA 0x00000000 +#define DDRSS_CTL_33_DATA 0x00000000 +#define DDRSS_CTL_34_DATA 0x08000010 +#define DDRSS_CTL_35_DATA 0x00004B4B +#define DDRSS_CTL_36_DATA 0x00000000 +#define DDRSS_CTL_37_DATA 0x00000000 +#define DDRSS_CTL_38_DATA 0x00000000 +#define DDRSS_CTL_39_DATA 0x00000000 +#define DDRSS_CTL_40_DATA 0x0000040C +#define DDRSS_CTL_41_DATA 0x00000000 +#define DDRSS_CTL_42_DATA 0x00001040 +#define DDRSS_CTL_43_DATA 0x00000000 +#define DDRSS_CTL_44_DATA 0x00001040 +#define DDRSS_CTL_45_DATA 0x00000000 +#define DDRSS_CTL_46_DATA 0x05000804 +#define DDRSS_CTL_47_DATA 0x00000700 +#define DDRSS_CTL_48_DATA 0x09090004 +#define DDRSS_CTL_49_DATA 0x00000303 +#define DDRSS_CTL_50_DATA 0x00720014 +#define DDRSS_CTL_51_DATA 0x09140050 +#define DDRSS_CTL_52_DATA 0x00004D22 +#define DDRSS_CTL_53_DATA 0x00720014 +#define DDRSS_CTL_54_DATA 0x09140050 +#define DDRSS_CTL_55_DATA 0x09004D22 +#define DDRSS_CTL_56_DATA 0x000A0A09 +#define DDRSS_CTL_57_DATA 0x040006DB +#define DDRSS_CTL_58_DATA 0x090F2005 +#define DDRSS_CTL_59_DATA 0x00001B13 +#define DDRSS_CTL_60_DATA 0x0E00FFCD +#define DDRSS_CTL_61_DATA 0x090F200F +#define DDRSS_CTL_62_DATA 0x00001B13 +#define DDRSS_CTL_63_DATA 0x0E00FFCD +#define DDRSS_CTL_64_DATA 0x0304200F +#define DDRSS_CTL_65_DATA 0x04050002 +#define DDRSS_CTL_66_DATA 0x24232423 +#define DDRSS_CTL_67_DATA 0x01010008 +#define DDRSS_CTL_68_DATA 0x04464607 +#define DDRSS_CTL_69_DATA 0x03282803 +#define DDRSS_CTL_70_DATA 0x00002828 +#define DDRSS_CTL_71_DATA 0x00000101 +#define DDRSS_CTL_72_DATA 0x00000000 +#define DDRSS_CTL_73_DATA 0x01000000 +#define DDRSS_CTL_74_DATA 0x000E0803 +#define DDRSS_CTL_75_DATA 0x000000BB +#define DDRSS_CTL_76_DATA 0x0000020B +#define DDRSS_CTL_77_DATA 0x00001C64 +#define DDRSS_CTL_78_DATA 0x0000020B +#define DDRSS_CTL_79_DATA 0x00001C64 +#define DDRSS_CTL_80_DATA 0x00000005 +#define DDRSS_CTL_81_DATA 0x00000007 +#define DDRSS_CTL_82_DATA 0x00000010 +#define DDRSS_CTL_83_DATA 0x00000106 +#define DDRSS_CTL_84_DATA 0x00000386 +#define DDRSS_CTL_85_DATA 0x00000106 +#define DDRSS_CTL_86_DATA 0x00000386 +#define DDRSS_CTL_87_DATA 0x03004000 +#define DDRSS_CTL_88_DATA 0x00001201 +#define DDRSS_CTL_89_DATA 0x000E0005 +#define DDRSS_CTL_90_DATA 0x2608000E +#define DDRSS_CTL_91_DATA 0x0A050526 +#define DDRSS_CTL_92_DATA 0x1B0E0A03 +#define DDRSS_CTL_93_DATA 0x1B0E0A04 +#define DDRSS_CTL_94_DATA 0x04010104 +#define DDRSS_CTL_95_DATA 0x00010401 +#define DDRSS_CTL_96_DATA 0x000F000F +#define DDRSS_CTL_97_DATA 0x02190219 +#define DDRSS_CTL_98_DATA 0x02190219 +#define DDRSS_CTL_99_DATA 0x00000000 +#define DDRSS_CTL_100_DATA 0x03030000 +#define DDRSS_CTL_101_DATA 0x05050501 +#define DDRSS_CTL_102_DATA 0x04041C04 +#define DDRSS_CTL_103_DATA 0x0E0A0E0A +#define DDRSS_CTL_104_DATA 0x0A04041C +#define DDRSS_CTL_105_DATA 0x030E0A0E +#define DDRSS_CTL_106_DATA 0x00000404 +#define DDRSS_CTL_107_DATA 0x00000301 +#define DDRSS_CTL_108_DATA 0x00000001 +#define DDRSS_CTL_109_DATA 0x00000000 +#define DDRSS_CTL_110_DATA 0x40020100 +#define DDRSS_CTL_111_DATA 0x00038010 +#define DDRSS_CTL_112_DATA 0x00050004 +#define DDRSS_CTL_113_DATA 0x00000004 +#define DDRSS_CTL_114_DATA 0x00040003 +#define DDRSS_CTL_115_DATA 0x00040005 +#define DDRSS_CTL_116_DATA 0x00030000 +#define DDRSS_CTL_117_DATA 0x00050004 +#define DDRSS_CTL_118_DATA 0x00000004 +#define DDRSS_CTL_119_DATA 0x00002EC0 +#define DDRSS_CTL_120_DATA 0x00002EC0 +#define DDRSS_CTL_121_DATA 0x00002EC0 +#define DDRSS_CTL_122_DATA 0x00002EC0 +#define DDRSS_CTL_123_DATA 0x00002EC0 +#define DDRSS_CTL_124_DATA 0x00000000 +#define DDRSS_CTL_125_DATA 0x0000051D +#define DDRSS_CTL_126_DATA 0x00071900 +#define DDRSS_CTL_127_DATA 0x00071900 +#define DDRSS_CTL_128_DATA 0x00071900 +#define DDRSS_CTL_129_DATA 0x00071900 +#define DDRSS_CTL_130_DATA 0x00071900 +#define DDRSS_CTL_131_DATA 0x00000000 +#define DDRSS_CTL_132_DATA 0x0000C6BC +#define DDRSS_CTL_133_DATA 0x00071900 +#define DDRSS_CTL_134_DATA 0x00071900 +#define DDRSS_CTL_135_DATA 0x00071900 +#define DDRSS_CTL_136_DATA 0x00071900 +#define DDRSS_CTL_137_DATA 0x00071900 +#define DDRSS_CTL_138_DATA 0x00000000 +#define DDRSS_CTL_139_DATA 0x0000C6BC +#define DDRSS_CTL_140_DATA 0x00000000 +#define DDRSS_CTL_141_DATA 0x00000000 +#define DDRSS_CTL_142_DATA 0x00000000 +#define DDRSS_CTL_143_DATA 0x00000000 +#define DDRSS_CTL_144_DATA 0x00000000 +#define DDRSS_CTL_145_DATA 0x00000000 +#define DDRSS_CTL_146_DATA 0x00000000 +#define DDRSS_CTL_147_DATA 0x00000000 +#define DDRSS_CTL_148_DATA 0x00000000 +#define DDRSS_CTL_149_DATA 0x00000000 +#define DDRSS_CTL_150_DATA 0x00000000 +#define DDRSS_CTL_151_DATA 0x00000000 +#define DDRSS_CTL_152_DATA 0x00000000 +#define DDRSS_CTL_153_DATA 0x00000000 +#define DDRSS_CTL_154_DATA 0x00000000 +#define DDRSS_CTL_155_DATA 0x00000000 +#define DDRSS_CTL_156_DATA 0x00000000 +#define DDRSS_CTL_157_DATA 0x00000000 +#define DDRSS_CTL_158_DATA 0x03050000 +#define DDRSS_CTL_159_DATA 0x040A040A +#define DDRSS_CTL_160_DATA 0x00000000 +#define DDRSS_CTL_161_DATA 0x08010000 +#define DDRSS_CTL_162_DATA 0x000E0808 +#define DDRSS_CTL_163_DATA 0x01000000 +#define DDRSS_CTL_164_DATA 0x0E080808 +#define DDRSS_CTL_165_DATA 0x00000000 +#define DDRSS_CTL_166_DATA 0x08080801 +#define DDRSS_CTL_167_DATA 0x0000080E +#define DDRSS_CTL_168_DATA 0x00040003 +#define DDRSS_CTL_169_DATA 0x00000007 +#define DDRSS_CTL_170_DATA 0x00000000 +#define DDRSS_CTL_171_DATA 0x00000000 +#define DDRSS_CTL_172_DATA 0x00000000 +#define DDRSS_CTL_173_DATA 0x00000000 +#define DDRSS_CTL_174_DATA 0x00000000 +#define DDRSS_CTL_175_DATA 0x00000000 +#define DDRSS_CTL_176_DATA 0x01000000 +#define DDRSS_CTL_177_DATA 0x00000000 +#define DDRSS_CTL_178_DATA 0x00001700 +#define DDRSS_CTL_179_DATA 0x0000100E +#define DDRSS_CTL_180_DATA 0x00000002 +#define DDRSS_CTL_181_DATA 0x00000000 +#define DDRSS_CTL_182_DATA 0x00000001 +#define DDRSS_CTL_183_DATA 0x00000002 +#define DDRSS_CTL_184_DATA 0x00000C00 +#define DDRSS_CTL_185_DATA 0x00008000 +#define DDRSS_CTL_186_DATA 0x00000C00 +#define DDRSS_CTL_187_DATA 0x00008000 +#define DDRSS_CTL_188_DATA 0x00000C00 +#define DDRSS_CTL_189_DATA 0x00008000 +#define DDRSS_CTL_190_DATA 0x00000000 +#define DDRSS_CTL_191_DATA 0x00000000 +#define DDRSS_CTL_192_DATA 0x00000000 +#define DDRSS_CTL_193_DATA 0x00000000 +#define DDRSS_CTL_194_DATA 0x00000000 +#define DDRSS_CTL_195_DATA 0x0005000A +#define DDRSS_CTL_196_DATA 0x0404000D +#define DDRSS_CTL_197_DATA 0x0000000D +#define DDRSS_CTL_198_DATA 0x00BB0176 +#define DDRSS_CTL_199_DATA 0x0E0E01D3 +#define DDRSS_CTL_200_DATA 0x000001D3 +#define DDRSS_CTL_201_DATA 0x00BB0176 +#define DDRSS_CTL_202_DATA 0x0E0E01D3 +#define DDRSS_CTL_203_DATA 0x000001D3 +#define DDRSS_CTL_204_DATA 0x00000000 +#define DDRSS_CTL_205_DATA 0x00000000 +#define DDRSS_CTL_206_DATA 0x00000000 +#define DDRSS_CTL_207_DATA 0x00000000 +#define DDRSS_CTL_208_DATA 0x00000004 +#define DDRSS_CTL_209_DATA 0x00000000 +#define DDRSS_CTL_210_DATA 0x00000000 +#define DDRSS_CTL_211_DATA 0x00000064 +#define DDRSS_CTL_212_DATA 0x00000036 +#define DDRSS_CTL_213_DATA 0x00000000 +#define DDRSS_CTL_214_DATA 0x00000064 +#define DDRSS_CTL_215_DATA 0x00000036 +#define DDRSS_CTL_216_DATA 0x00000000 +#define DDRSS_CTL_217_DATA 0x00000004 +#define DDRSS_CTL_218_DATA 0x00000000 +#define DDRSS_CTL_219_DATA 0x00000000 +#define DDRSS_CTL_220_DATA 0x00000064 +#define DDRSS_CTL_221_DATA 0x00000036 +#define DDRSS_CTL_222_DATA 0x00000000 +#define DDRSS_CTL_223_DATA 0x00000064 +#define DDRSS_CTL_224_DATA 0x00000036 +#define DDRSS_CTL_225_DATA 0x00000000 +#define DDRSS_CTL_226_DATA 0x00000000 +#define DDRSS_CTL_227_DATA 0x00000031 +#define DDRSS_CTL_228_DATA 0x000000B1 +#define DDRSS_CTL_229_DATA 0x000000B1 +#define DDRSS_CTL_230_DATA 0x00000031 +#define DDRSS_CTL_231_DATA 0x000000B1 +#define DDRSS_CTL_232_DATA 0x000000B1 +#define DDRSS_CTL_233_DATA 0x00000000 +#define DDRSS_CTL_234_DATA 0x00000000 +#define DDRSS_CTL_235_DATA 0x00000000 +#define DDRSS_CTL_236_DATA 0x00000000 +#define DDRSS_CTL_237_DATA 0x00000000 +#define DDRSS_CTL_238_DATA 0x00000000 +#define DDRSS_CTL_239_DATA 0x00000000 +#define DDRSS_CTL_240_DATA 0x00000000 +#define DDRSS_CTL_241_DATA 0x00000000 +#define DDRSS_CTL_242_DATA 0x00000000 +#define DDRSS_CTL_243_DATA 0x00000000 +#define DDRSS_CTL_244_DATA 0x00000000 +#define DDRSS_CTL_245_DATA 0x00000000 +#define DDRSS_CTL_246_DATA 0x00000000 +#define DDRSS_CTL_247_DATA 0x00000000 +#define DDRSS_CTL_248_DATA 0x00000000 +#define DDRSS_CTL_249_DATA 0x00000000 +#define DDRSS_CTL_250_DATA 0x00000000 +#define DDRSS_CTL_251_DATA 0x00000000 +#define DDRSS_CTL_252_DATA 0x00000000 +#define DDRSS_CTL_253_DATA 0x00000000 +#define DDRSS_CTL_254_DATA 0x00000000 +#define DDRSS_CTL_255_DATA 0x00000000 +#define DDRSS_CTL_256_DATA 0x00000000 +#define DDRSS_CTL_257_DATA 0x55005555 +#define DDRSS_CTL_258_DATA 0x00002755 +#define DDRSS_CTL_259_DATA 0x00000027 +#define DDRSS_CTL_260_DATA 0x00000027 +#define DDRSS_CTL_261_DATA 0x00000027 +#define DDRSS_CTL_262_DATA 0x00000027 +#define DDRSS_CTL_263_DATA 0x00000027 +#define DDRSS_CTL_264_DATA 0x00000000 +#define DDRSS_CTL_265_DATA 0x00000000 +#define DDRSS_CTL_266_DATA 0x0000002B +#define DDRSS_CTL_267_DATA 0x0000002B +#define DDRSS_CTL_268_DATA 0x0000002B +#define DDRSS_CTL_269_DATA 0x0000002B +#define DDRSS_CTL_270_DATA 0x0000002B +#define DDRSS_CTL_271_DATA 0x0000002B +#define DDRSS_CTL_272_DATA 0x00000000 +#define DDRSS_CTL_273_DATA 0x00000000 +#define DDRSS_CTL_274_DATA 0x00000016 +#define DDRSS_CTL_275_DATA 0x00000016 +#define DDRSS_CTL_276_DATA 0x00000000 +#define DDRSS_CTL_277_DATA 0x00000016 +#define DDRSS_CTL_278_DATA 0x00000016 +#define DDRSS_CTL_279_DATA 0x00000020 +#define DDRSS_CTL_280_DATA 0x00010000 +#define DDRSS_CTL_281_DATA 0x00000100 +#define DDRSS_CTL_282_DATA 0x00000000 +#define DDRSS_CTL_283_DATA 0x00000000 +#define DDRSS_CTL_284_DATA 0x00000101 +#define DDRSS_CTL_285_DATA 0x00000000 +#define DDRSS_CTL_286_DATA 0x00000000 +#define DDRSS_CTL_287_DATA 0x00000000 +#define DDRSS_CTL_288_DATA 0x00000000 +#define DDRSS_CTL_289_DATA 0x00000000 +#define DDRSS_CTL_290_DATA 0x00000000 +#define DDRSS_CTL_291_DATA 0x00000000 +#define DDRSS_CTL_292_DATA 0x00000000 +#define DDRSS_CTL_293_DATA 0x00000000 +#define DDRSS_CTL_294_DATA 0x00000000 +#define DDRSS_CTL_295_DATA 0x00000000 +#define DDRSS_CTL_296_DATA 0x0C181511 +#define DDRSS_CTL_297_DATA 0x00000304 +#define DDRSS_CTL_298_DATA 0x00000000 +#define DDRSS_CTL_299_DATA 0x00000000 +#define DDRSS_CTL_300_DATA 0x00000000 +#define DDRSS_CTL_301_DATA 0x00000000 +#define DDRSS_CTL_302_DATA 0x00000000 +#define DDRSS_CTL_303_DATA 0x00000000 +#define DDRSS_CTL_304_DATA 0x00000000 +#define DDRSS_CTL_305_DATA 0x00000000 +#define DDRSS_CTL_306_DATA 0x00000000 +#define DDRSS_CTL_307_DATA 0x00000000 +#define DDRSS_CTL_308_DATA 0x00000000 +#define DDRSS_CTL_309_DATA 0x00000000 +#define DDRSS_CTL_310_DATA 0x00000000 +#define DDRSS_CTL_311_DATA 0x00020000 +#define DDRSS_CTL_312_DATA 0x00400100 +#define DDRSS_CTL_313_DATA 0x00080032 +#define DDRSS_CTL_314_DATA 0x01000200 +#define DDRSS_CTL_315_DATA 0x074A0040 +#define DDRSS_CTL_316_DATA 0x00020038 +#define DDRSS_CTL_317_DATA 0x00400100 +#define DDRSS_CTL_318_DATA 0x0038074A +#define DDRSS_CTL_319_DATA 0x00030000 +#define DDRSS_CTL_320_DATA 0x005E005E +#define DDRSS_CTL_321_DATA 0x00000100 +#define DDRSS_CTL_322_DATA 0x01010000 +#define DDRSS_CTL_323_DATA 0x00000202 +#define DDRSS_CTL_324_DATA 0x0FFF0000 +#define DDRSS_CTL_325_DATA 0x000FFF00 +#define DDRSS_CTL_326_DATA 0x1FFF1000 +#define DDRSS_CTL_327_DATA 0x000FFF00 +#define DDRSS_CTL_328_DATA 0x0B000001 +#define DDRSS_CTL_329_DATA 0x0001FFFF +#define DDRSS_CTL_330_DATA 0x01010101 +#define DDRSS_CTL_331_DATA 0x01010101 +#define DDRSS_CTL_332_DATA 0x00000118 +#define DDRSS_CTL_333_DATA 0x00000C03 +#define DDRSS_CTL_334_DATA 0x00040100 +#define DDRSS_CTL_335_DATA 0x00040100 +#define DDRSS_CTL_336_DATA 0x00000000 +#define DDRSS_CTL_337_DATA 0x00000000 +#define DDRSS_CTL_338_DATA 0x01030303 +#define DDRSS_CTL_339_DATA 0x00000001 +#define DDRSS_CTL_340_DATA 0x00000000 +#define DDRSS_CTL_341_DATA 0x00000000 +#define DDRSS_CTL_342_DATA 0x00000000 +#define DDRSS_CTL_343_DATA 0x00000000 +#define DDRSS_CTL_344_DATA 0x00000000 +#define DDRSS_CTL_345_DATA 0x00000000 +#define DDRSS_CTL_346_DATA 0x00000000 +#define DDRSS_CTL_347_DATA 0x00000000 +#define DDRSS_CTL_348_DATA 0x00000000 +#define DDRSS_CTL_349_DATA 0x00000000 +#define DDRSS_CTL_350_DATA 0x00000000 +#define DDRSS_CTL_351_DATA 0x00000000 +#define DDRSS_CTL_352_DATA 0x00000000 +#define DDRSS_CTL_353_DATA 0x00000000 +#define DDRSS_CTL_354_DATA 0x00000000 +#define DDRSS_CTL_355_DATA 0x00000000 +#define DDRSS_CTL_356_DATA 0x00000000 +#define DDRSS_CTL_357_DATA 0x00000000 +#define DDRSS_CTL_358_DATA 0x00000000 +#define DDRSS_CTL_359_DATA 0x00000000 +#define DDRSS_CTL_360_DATA 0x00000000 +#define DDRSS_CTL_361_DATA 0x00000000 +#define DDRSS_CTL_362_DATA 0x00000000 +#define DDRSS_CTL_363_DATA 0x00000000 +#define DDRSS_CTL_364_DATA 0x00000000 +#define DDRSS_CTL_365_DATA 0x00000000 +#define DDRSS_CTL_366_DATA 0x00000000 +#define DDRSS_CTL_367_DATA 0x00000000 +#define DDRSS_CTL_368_DATA 0x00000000 +#define DDRSS_CTL_369_DATA 0x00000000 +#define DDRSS_CTL_370_DATA 0x00000000 +#define DDRSS_CTL_371_DATA 0x00000000 +#define DDRSS_CTL_372_DATA 0x00000000 +#define DDRSS_CTL_373_DATA 0x00000000 +#define DDRSS_CTL_374_DATA 0x00000000 +#define DDRSS_CTL_375_DATA 0x00000000 +#define DDRSS_CTL_376_DATA 0x00000000 +#define DDRSS_CTL_377_DATA 0x00000000 +#define DDRSS_CTL_378_DATA 0x00000000 +#define DDRSS_CTL_379_DATA 0x00000000 +#define DDRSS_CTL_380_DATA 0x00000000 +#define DDRSS_CTL_381_DATA 0x00000000 +#define DDRSS_CTL_382_DATA 0x00000000 +#define DDRSS_CTL_383_DATA 0x01000101 +#define DDRSS_CTL_384_DATA 0x01010001 +#define DDRSS_CTL_385_DATA 0x00010101 +#define DDRSS_CTL_386_DATA 0x01090903 +#define DDRSS_CTL_387_DATA 0x05020201 +#define DDRSS_CTL_388_DATA 0x0E081B1B +#define DDRSS_CTL_389_DATA 0x0008030E +#define DDRSS_CTL_390_DATA 0x0B12030E +#define DDRSS_CTL_391_DATA 0x0B120314 +#define DDRSS_CTL_392_DATA 0x12120814 +#define DDRSS_CTL_393_DATA 0x01000000 +#define DDRSS_CTL_394_DATA 0x07030701 +#define DDRSS_CTL_395_DATA 0x04000103 +#define DDRSS_CTL_396_DATA 0x1B000004 +#define DDRSS_CTL_397_DATA 0x00000176 +#define DDRSS_CTL_398_DATA 0x00000200 +#define DDRSS_CTL_399_DATA 0x00000200 +#define DDRSS_CTL_400_DATA 0x00000200 +#define DDRSS_CTL_401_DATA 0x00000200 +#define DDRSS_CTL_402_DATA 0x00000693 +#define DDRSS_CTL_403_DATA 0x00000E9C +#define DDRSS_CTL_404_DATA 0x03050202 +#define DDRSS_CTL_405_DATA 0x37200201 +#define DDRSS_CTL_406_DATA 0x000038C8 +#define DDRSS_CTL_407_DATA 0x00000200 +#define DDRSS_CTL_408_DATA 0x00000200 +#define DDRSS_CTL_409_DATA 0x00000200 +#define DDRSS_CTL_410_DATA 0x00000200 +#define DDRSS_CTL_411_DATA 0x0000FF84 +#define DDRSS_CTL_412_DATA 0x000237D0 +#define DDRSS_CTL_413_DATA 0x111F0402 +#define DDRSS_CTL_414_DATA 0x37200C0D +#define DDRSS_CTL_415_DATA 0x000038C8 +#define DDRSS_CTL_416_DATA 0x00000200 +#define DDRSS_CTL_417_DATA 0x00000200 +#define DDRSS_CTL_418_DATA 0x00000200 +#define DDRSS_CTL_419_DATA 0x00000200 +#define DDRSS_CTL_420_DATA 0x0000FF84 +#define DDRSS_CTL_421_DATA 0x000237D0 +#define DDRSS_CTL_422_DATA 0x111F0402 +#define DDRSS_CTL_423_DATA 0x00200C0D +#define DDRSS_CTL_424_DATA 0x00000000 +#define DDRSS_CTL_425_DATA 0x02000A00 +#define DDRSS_CTL_426_DATA 0x00050003 +#define DDRSS_CTL_427_DATA 0x00010101 +#define DDRSS_CTL_428_DATA 0x00010101 +#define DDRSS_CTL_429_DATA 0x00010001 +#define DDRSS_CTL_430_DATA 0x00000101 +#define DDRSS_CTL_431_DATA 0x02000201 +#define DDRSS_CTL_432_DATA 0x02010000 +#define DDRSS_CTL_433_DATA 0x06000200 +#define DDRSS_CTL_434_DATA 0x00002222 +#define DDRSS_PI_0_DATA 0x00000B00 +#define DDRSS_PI_1_DATA 0x00000000 +#define DDRSS_PI_2_DATA 0x00000000 +#define DDRSS_PI_3_DATA 0x01000000 +#define DDRSS_PI_4_DATA 0x00000001 +#define DDRSS_PI_5_DATA 0x00010064 +#define DDRSS_PI_6_DATA 0x00000000 +#define DDRSS_PI_7_DATA 0x00000000 +#define DDRSS_PI_8_DATA 0x00000000 +#define DDRSS_PI_9_DATA 0x00000000 +#define DDRSS_PI_10_DATA 0x00000000 +#define DDRSS_PI_11_DATA 0x00000002 +#define DDRSS_PI_12_DATA 0x00000005 +#define DDRSS_PI_13_DATA 0x000F0001 +#define DDRSS_PI_14_DATA 0x08000000 +#define DDRSS_PI_15_DATA 0x00010300 +#define DDRSS_PI_16_DATA 0x00000005 +#define DDRSS_PI_17_DATA 0x00000000 +#define DDRSS_PI_18_DATA 0x00000000 +#define DDRSS_PI_19_DATA 0x00000000 +#define DDRSS_PI_20_DATA 0x00000000 +#define DDRSS_PI_21_DATA 0x00000000 +#define DDRSS_PI_22_DATA 0x00000000 +#define DDRSS_PI_23_DATA 0x00000000 +#define DDRSS_PI_24_DATA 0x00000000 +#define DDRSS_PI_25_DATA 0x00000000 +#define DDRSS_PI_26_DATA 0x01010000 +#define DDRSS_PI_27_DATA 0x0A000100 +#define DDRSS_PI_28_DATA 0x00000028 +#define DDRSS_PI_29_DATA 0x0F000000 +#define DDRSS_PI_30_DATA 0x00320000 +#define DDRSS_PI_31_DATA 0x00000000 +#define DDRSS_PI_32_DATA 0x00000000 +#define DDRSS_PI_33_DATA 0x01010102 +#define DDRSS_PI_34_DATA 0x00000000 +#define DDRSS_PI_35_DATA 0x00000000 +#define DDRSS_PI_36_DATA 0x00000000 +#define DDRSS_PI_37_DATA 0x00000001 +#define DDRSS_PI_38_DATA 0x000000AA +#define DDRSS_PI_39_DATA 0x00000055 +#define DDRSS_PI_40_DATA 0x000000B5 +#define DDRSS_PI_41_DATA 0x0000004A +#define DDRSS_PI_42_DATA 0x00000056 +#define DDRSS_PI_43_DATA 0x000000A9 +#define DDRSS_PI_44_DATA 0x000000A9 +#define DDRSS_PI_45_DATA 0x000000B5 +#define DDRSS_PI_46_DATA 0x00000000 +#define DDRSS_PI_47_DATA 0x00000000 +#define DDRSS_PI_48_DATA 0x000F0F00 +#define DDRSS_PI_49_DATA 0x0000001A +#define DDRSS_PI_50_DATA 0x000007D0 +#define DDRSS_PI_51_DATA 0x00000300 +#define DDRSS_PI_52_DATA 0x00000000 +#define DDRSS_PI_53_DATA 0x00000000 +#define DDRSS_PI_54_DATA 0x01000000 +#define DDRSS_PI_55_DATA 0x00010101 +#define DDRSS_PI_56_DATA 0x01000000 +#define DDRSS_PI_57_DATA 0x03000000 +#define DDRSS_PI_58_DATA 0x00000000 +#define DDRSS_PI_59_DATA 0x0000170F +#define DDRSS_PI_60_DATA 0x00000000 +#define DDRSS_PI_61_DATA 0x00000000 +#define DDRSS_PI_62_DATA 0x00000000 +#define DDRSS_PI_63_DATA 0x0A0A140A +#define DDRSS_PI_64_DATA 0x10020101 +#define DDRSS_PI_65_DATA 0x01000210 +#define DDRSS_PI_66_DATA 0x05000404 +#define DDRSS_PI_67_DATA 0x00010001 +#define DDRSS_PI_68_DATA 0x0001000E +#define DDRSS_PI_69_DATA 0x01010F00 +#define DDRSS_PI_70_DATA 0x00010000 +#define DDRSS_PI_71_DATA 0x00000034 +#define DDRSS_PI_72_DATA 0x00000000 +#define DDRSS_PI_73_DATA 0x00000000 +#define DDRSS_PI_74_DATA 0x0000FFFF +#define DDRSS_PI_75_DATA 0x00000000 +#define DDRSS_PI_76_DATA 0x00000000 +#define DDRSS_PI_77_DATA 0x00000000 +#define DDRSS_PI_78_DATA 0x00000000 +#define DDRSS_PI_79_DATA 0x01000000 +#define DDRSS_PI_80_DATA 0x02010001 +#define DDRSS_PI_81_DATA 0x02000008 +#define DDRSS_PI_82_DATA 0x01000200 +#define DDRSS_PI_83_DATA 0x00000100 +#define DDRSS_PI_84_DATA 0x02000100 +#define DDRSS_PI_85_DATA 0x02000200 +#define DDRSS_PI_86_DATA 0x00000000 +#define DDRSS_PI_87_DATA 0x00000000 +#define DDRSS_PI_88_DATA 0x00000000 +#define DDRSS_PI_89_DATA 0x00000000 +#define DDRSS_PI_90_DATA 0x00000000 +#define DDRSS_PI_91_DATA 0x00000000 +#define DDRSS_PI_92_DATA 0x00000000 +#define DDRSS_PI_93_DATA 0x00000000 +#define DDRSS_PI_94_DATA 0x00000000 +#define DDRSS_PI_95_DATA 0x00000000 +#define DDRSS_PI_96_DATA 0x00000000 +#define DDRSS_PI_97_DATA 0x00000000 +#define DDRSS_PI_98_DATA 0x00000000 +#define DDRSS_PI_99_DATA 0x01000400 +#define DDRSS_PI_100_DATA 0x0E0D0F10 +#define DDRSS_PI_101_DATA 0x080A1413 +#define DDRSS_PI_102_DATA 0x01000009 +#define DDRSS_PI_103_DATA 0x00000302 +#define DDRSS_PI_104_DATA 0x00000008 +#define DDRSS_PI_105_DATA 0x08000000 +#define DDRSS_PI_106_DATA 0x00000100 +#define DDRSS_PI_107_DATA 0x00000000 +#define DDRSS_PI_108_DATA 0x0000AA00 +#define DDRSS_PI_109_DATA 0x00000000 +#define DDRSS_PI_110_DATA 0x00000000 +#define DDRSS_PI_111_DATA 0x00010000 +#define DDRSS_PI_112_DATA 0x00000000 +#define DDRSS_PI_113_DATA 0x00000000 +#define DDRSS_PI_114_DATA 0x00000000 +#define DDRSS_PI_115_DATA 0x00000000 +#define DDRSS_PI_116_DATA 0x00000000 +#define DDRSS_PI_117_DATA 0x00000000 +#define DDRSS_PI_118_DATA 0x00000000 +#define DDRSS_PI_119_DATA 0x00000000 +#define DDRSS_PI_120_DATA 0x00000000 +#define DDRSS_PI_121_DATA 0x00000000 +#define DDRSS_PI_122_DATA 0x00000000 +#define DDRSS_PI_123_DATA 0x00000000 +#define DDRSS_PI_124_DATA 0x00000000 +#define DDRSS_PI_125_DATA 0x00000000 +#define DDRSS_PI_126_DATA 0x00000000 +#define DDRSS_PI_127_DATA 0x00000000 +#define DDRSS_PI_128_DATA 0x00000000 +#define DDRSS_PI_129_DATA 0x00000000 +#define DDRSS_PI_130_DATA 0x00000000 +#define DDRSS_PI_131_DATA 0x00000000 +#define DDRSS_PI_132_DATA 0x00000000 +#define DDRSS_PI_133_DATA 0x00000000 +#define DDRSS_PI_134_DATA 0x00000000 +#define DDRSS_PI_135_DATA 0x00000000 +#define DDRSS_PI_136_DATA 0x00000008 +#define DDRSS_PI_137_DATA 0x00000000 +#define DDRSS_PI_138_DATA 0x00000000 +#define DDRSS_PI_139_DATA 0x00000000 +#define DDRSS_PI_140_DATA 0x00000000 +#define DDRSS_PI_141_DATA 0x00000000 +#define DDRSS_PI_142_DATA 0x00000000 +#define DDRSS_PI_143_DATA 0x00000000 +#define DDRSS_PI_144_DATA 0x00000000 +#define DDRSS_PI_145_DATA 0x00010000 +#define DDRSS_PI_146_DATA 0x00000000 +#define DDRSS_PI_147_DATA 0x00000000 +#define DDRSS_PI_148_DATA 0x0000000A +#define DDRSS_PI_149_DATA 0x000186A0 +#define DDRSS_PI_150_DATA 0x00000100 +#define DDRSS_PI_151_DATA 0x00000000 +#define DDRSS_PI_152_DATA 0x00000000 +#define DDRSS_PI_153_DATA 0x00000000 +#define DDRSS_PI_154_DATA 0x00000000 +#define DDRSS_PI_155_DATA 0x00000000 +#define DDRSS_PI_156_DATA 0x01000000 +#define DDRSS_PI_157_DATA 0x00010003 +#define DDRSS_PI_158_DATA 0x02000101 +#define DDRSS_PI_159_DATA 0x01030001 +#define DDRSS_PI_160_DATA 0x00010400 +#define DDRSS_PI_161_DATA 0x06000105 +#define DDRSS_PI_162_DATA 0x01070001 +#define DDRSS_PI_163_DATA 0x00000000 +#define DDRSS_PI_164_DATA 0x00000000 +#define DDRSS_PI_165_DATA 0x00000000 +#define DDRSS_PI_166_DATA 0x00010001 +#define DDRSS_PI_167_DATA 0x00000000 +#define DDRSS_PI_168_DATA 0x00000000 +#define DDRSS_PI_169_DATA 0x00000000 +#define DDRSS_PI_170_DATA 0x00000000 +#define DDRSS_PI_171_DATA 0x00010000 +#define DDRSS_PI_172_DATA 0x00000004 +#define DDRSS_PI_173_DATA 0x00000000 +#define DDRSS_PI_174_DATA 0x00010000 +#define DDRSS_PI_175_DATA 0x00000000 +#define DDRSS_PI_176_DATA 0x00080000 +#define DDRSS_PI_177_DATA 0x01180118 +#define DDRSS_PI_178_DATA 0x00262601 +#define DDRSS_PI_179_DATA 0x00000034 +#define DDRSS_PI_180_DATA 0x0000005E +#define DDRSS_PI_181_DATA 0x0002005E +#define DDRSS_PI_182_DATA 0x02000200 +#define DDRSS_PI_183_DATA 0x00000004 +#define DDRSS_PI_184_DATA 0x0000100C +#define DDRSS_PI_185_DATA 0x00104000 +#define DDRSS_PI_186_DATA 0x00400000 +#define DDRSS_PI_187_DATA 0x0000000E +#define DDRSS_PI_188_DATA 0x000000BB +#define DDRSS_PI_189_DATA 0x0000020B +#define DDRSS_PI_190_DATA 0x00001C64 +#define DDRSS_PI_191_DATA 0x0000020B +#define DDRSS_PI_192_DATA 0x04001C64 +#define DDRSS_PI_193_DATA 0x01010404 +#define DDRSS_PI_194_DATA 0x00001501 +#define DDRSS_PI_195_DATA 0x00270027 +#define DDRSS_PI_196_DATA 0x01000100 +#define DDRSS_PI_197_DATA 0x00000100 +#define DDRSS_PI_198_DATA 0x00000000 +#define DDRSS_PI_199_DATA 0x05090903 +#define DDRSS_PI_200_DATA 0x01011B1B +#define DDRSS_PI_201_DATA 0x01010101 +#define DDRSS_PI_202_DATA 0x000C0C0A +#define DDRSS_PI_203_DATA 0x00000000 +#define DDRSS_PI_204_DATA 0x00000000 +#define DDRSS_PI_205_DATA 0x04000000 +#define DDRSS_PI_206_DATA 0x0C021212 +#define DDRSS_PI_207_DATA 0x0404020C +#define DDRSS_PI_208_DATA 0x00090031 +#define DDRSS_PI_209_DATA 0x001B0043 +#define DDRSS_PI_210_DATA 0x001B0043 +#define DDRSS_PI_211_DATA 0x01010101 +#define DDRSS_PI_212_DATA 0x0003000D +#define DDRSS_PI_213_DATA 0x000301D3 +#define DDRSS_PI_214_DATA 0x010001D3 +#define DDRSS_PI_215_DATA 0x000E000E +#define DDRSS_PI_216_DATA 0x01D40100 +#define DDRSS_PI_217_DATA 0x010001D4 +#define DDRSS_PI_218_DATA 0x01D401D4 +#define DDRSS_PI_219_DATA 0x32103200 +#define DDRSS_PI_220_DATA 0x01013210 +#define DDRSS_PI_221_DATA 0x0A070601 +#define DDRSS_PI_222_DATA 0x1C11090D +#define DDRSS_PI_223_DATA 0x1C110913 +#define DDRSS_PI_224_DATA 0x000C0013 +#define DDRSS_PI_225_DATA 0x00001000 +#define DDRSS_PI_226_DATA 0x00000C00 +#define DDRSS_PI_227_DATA 0x00001000 +#define DDRSS_PI_228_DATA 0x00000C00 +#define DDRSS_PI_229_DATA 0x02001000 +#define DDRSS_PI_230_DATA 0x0021000D +#define DDRSS_PI_231_DATA 0x002101D3 +#define DDRSS_PI_232_DATA 0x000001D3 +#define DDRSS_PI_233_DATA 0x00001900 +#define DDRSS_PI_234_DATA 0x32000056 +#define DDRSS_PI_235_DATA 0x06000101 +#define DDRSS_PI_236_DATA 0x00250204 +#define DDRSS_PI_237_DATA 0x3212005A +#define DDRSS_PI_238_DATA 0x17000101 +#define DDRSS_PI_239_DATA 0x00250C12 +#define DDRSS_PI_240_DATA 0x3212005A +#define DDRSS_PI_241_DATA 0x17000101 +#define DDRSS_PI_242_DATA 0x00000C12 +#define DDRSS_PI_243_DATA 0x05030900 +#define DDRSS_PI_244_DATA 0x00040900 +#define DDRSS_PI_245_DATA 0x0000062B +#define DDRSS_PI_246_DATA 0x20010004 +#define DDRSS_PI_247_DATA 0x0A0A0A03 +#define DDRSS_PI_248_DATA 0x280F0000 +#define DDRSS_PI_249_DATA 0x24090023 +#define DDRSS_PI_250_DATA 0x0000E638 +#define DDRSS_PI_251_DATA 0x20070050 +#define DDRSS_PI_252_DATA 0x1B131B1C +#define DDRSS_PI_253_DATA 0x280F0000 +#define DDRSS_PI_254_DATA 0x24090023 +#define DDRSS_PI_255_DATA 0x0000E638 +#define DDRSS_PI_256_DATA 0x20070050 +#define DDRSS_PI_257_DATA 0x1B131B1C +#define DDRSS_PI_258_DATA 0x00000000 +#define DDRSS_PI_259_DATA 0x00000176 +#define DDRSS_PI_260_DATA 0x00000E9C +#define DDRSS_PI_261_DATA 0x000038C8 +#define DDRSS_PI_262_DATA 0x000237D0 +#define DDRSS_PI_263_DATA 0x000038C8 +#define DDRSS_PI_264_DATA 0x000237D0 +#define DDRSS_PI_265_DATA 0x0219000F +#define DDRSS_PI_266_DATA 0x03030219 +#define DDRSS_PI_267_DATA 0x00000003 +#define DDRSS_PI_268_DATA 0x00000000 +#define DDRSS_PI_269_DATA 0x0A040503 +#define DDRSS_PI_270_DATA 0x00000A04 +#define DDRSS_PI_271_DATA 0x00002710 +#define DDRSS_PI_272_DATA 0x000186A0 +#define DDRSS_PI_273_DATA 0x00000005 +#define DDRSS_PI_274_DATA 0x00000064 +#define DDRSS_PI_275_DATA 0x0000000F +#define DDRSS_PI_276_DATA 0x0005B18F +#define DDRSS_PI_277_DATA 0x000186A0 +#define DDRSS_PI_278_DATA 0x00000005 +#define DDRSS_PI_279_DATA 0x00000E94 +#define DDRSS_PI_280_DATA 0x00000219 +#define DDRSS_PI_281_DATA 0x0005B18F +#define DDRSS_PI_282_DATA 0x000186A0 +#define DDRSS_PI_283_DATA 0x00000005 +#define DDRSS_PI_284_DATA 0x00000E94 +#define DDRSS_PI_285_DATA 0x01000219 +#define DDRSS_PI_286_DATA 0x00320040 +#define DDRSS_PI_287_DATA 0x00010008 +#define DDRSS_PI_288_DATA 0x074A0040 +#define DDRSS_PI_289_DATA 0x00010038 +#define DDRSS_PI_290_DATA 0x074A0040 +#define DDRSS_PI_291_DATA 0x00000338 +#define DDRSS_PI_292_DATA 0x0028005D +#define DDRSS_PI_293_DATA 0x03040404 +#define DDRSS_PI_294_DATA 0x00000303 +#define DDRSS_PI_295_DATA 0x01010000 +#define DDRSS_PI_296_DATA 0x04040202 +#define DDRSS_PI_297_DATA 0x67670808 +#define DDRSS_PI_298_DATA 0x67676767 +#define DDRSS_PI_299_DATA 0x67676767 +#define DDRSS_PI_300_DATA 0x67676767 +#define DDRSS_PI_301_DATA 0x00006767 +#define DDRSS_PI_302_DATA 0x00000000 +#define DDRSS_PI_303_DATA 0x00000000 +#define DDRSS_PI_304_DATA 0x00000000 +#define DDRSS_PI_305_DATA 0x00000000 +#define DDRSS_PI_306_DATA 0x55000000 +#define DDRSS_PI_307_DATA 0x00000000 +#define DDRSS_PI_308_DATA 0x3C00005A +#define DDRSS_PI_309_DATA 0x00005500 +#define DDRSS_PI_310_DATA 0x00005A00 +#define DDRSS_PI_311_DATA 0x0055003C +#define DDRSS_PI_312_DATA 0x00000000 +#define DDRSS_PI_313_DATA 0x3C00005A +#define DDRSS_PI_314_DATA 0x00005500 +#define DDRSS_PI_315_DATA 0x00005A00 +#define DDRSS_PI_316_DATA 0x1716153C +#define DDRSS_PI_317_DATA 0x13121118 +#define DDRSS_PI_318_DATA 0x06050414 +#define DDRSS_PI_319_DATA 0x02010007 +#define DDRSS_PI_320_DATA 0x00000003 +#define DDRSS_PI_321_DATA 0x00000000 +#define DDRSS_PI_322_DATA 0x00000000 +#define DDRSS_PI_323_DATA 0x01000000 +#define DDRSS_PI_324_DATA 0x04020201 +#define DDRSS_PI_325_DATA 0x00080804 +#define DDRSS_PI_326_DATA 0x00000000 +#define DDRSS_PI_327_DATA 0x00000000 +#define DDRSS_PI_328_DATA 0x00000000 +#define DDRSS_PI_329_DATA 0x00000004 +#define DDRSS_PI_330_DATA 0x00000000 +#define DDRSS_PI_331_DATA 0x00000031 +#define DDRSS_PI_332_DATA 0x00000000 +#define DDRSS_PI_333_DATA 0x00000000 +#define DDRSS_PI_334_DATA 0x00000000 +#define DDRSS_PI_335_DATA 0x20002B27 +#define DDRSS_PI_336_DATA 0x00000000 +#define DDRSS_PI_337_DATA 0x00000064 +#define DDRSS_PI_338_DATA 0x00000036 +#define DDRSS_PI_339_DATA 0x000000B1 +#define DDRSS_PI_340_DATA 0x00000000 +#define DDRSS_PI_341_DATA 0x00000000 +#define DDRSS_PI_342_DATA 0x55000000 +#define DDRSS_PI_343_DATA 0x20162B27 +#define DDRSS_PI_344_DATA 0x00000000 +#define DDRSS_PI_345_DATA 0x00000064 +#define DDRSS_PI_346_DATA 0x00000036 +#define DDRSS_PI_347_DATA 0x000000B1 +#define DDRSS_PI_348_DATA 0x00000000 +#define DDRSS_PI_349_DATA 0x00000000 +#define DDRSS_PI_350_DATA 0x55000000 +#define DDRSS_PI_351_DATA 0x20162B27 +#define DDRSS_PI_352_DATA 0x00000000 +#define DDRSS_PI_353_DATA 0x00000004 +#define DDRSS_PI_354_DATA 0x00000000 +#define DDRSS_PI_355_DATA 0x00000031 +#define DDRSS_PI_356_DATA 0x00000000 +#define DDRSS_PI_357_DATA 0x00000000 +#define DDRSS_PI_358_DATA 0x00000000 +#define DDRSS_PI_359_DATA 0x20002B27 +#define DDRSS_PI_360_DATA 0x00000000 +#define DDRSS_PI_361_DATA 0x00000064 +#define DDRSS_PI_362_DATA 0x00000036 +#define DDRSS_PI_363_DATA 0x000000B1 +#define DDRSS_PI_364_DATA 0x00000000 +#define DDRSS_PI_365_DATA 0x00000000 +#define DDRSS_PI_366_DATA 0x55000000 +#define DDRSS_PI_367_DATA 0x20162B27 +#define DDRSS_PI_368_DATA 0x00000000 +#define DDRSS_PI_369_DATA 0x00000064 +#define DDRSS_PI_370_DATA 0x00000036 +#define DDRSS_PI_371_DATA 0x000000B1 +#define DDRSS_PI_372_DATA 0x00000000 +#define DDRSS_PI_373_DATA 0x00000000 +#define DDRSS_PI_374_DATA 0x55000000 +#define DDRSS_PI_375_DATA 0x20162B27 +#define DDRSS_PI_376_DATA 0x00000000 +#define DDRSS_PI_377_DATA 0x00000004 +#define DDRSS_PI_378_DATA 0x00000000 +#define DDRSS_PI_379_DATA 0x00000031 +#define DDRSS_PI_380_DATA 0x00000000 +#define DDRSS_PI_381_DATA 0x00000000 +#define DDRSS_PI_382_DATA 0x00000000 +#define DDRSS_PI_383_DATA 0x20002B27 +#define DDRSS_PI_384_DATA 0x00000000 +#define DDRSS_PI_385_DATA 0x00000064 +#define DDRSS_PI_386_DATA 0x00000036 +#define DDRSS_PI_387_DATA 0x000000B1 +#define DDRSS_PI_388_DATA 0x00000000 +#define DDRSS_PI_389_DATA 0x00000000 +#define DDRSS_PI_390_DATA 0x55000000 +#define DDRSS_PI_391_DATA 0x20162B27 +#define DDRSS_PI_392_DATA 0x00000000 +#define DDRSS_PI_393_DATA 0x00000064 +#define DDRSS_PI_394_DATA 0x00000036 +#define DDRSS_PI_395_DATA 0x000000B1 +#define DDRSS_PI_396_DATA 0x00000000 +#define DDRSS_PI_397_DATA 0x00000000 +#define DDRSS_PI_398_DATA 0x55000000 +#define DDRSS_PI_399_DATA 0x20162B27 +#define DDRSS_PI_400_DATA 0x00000000 +#define DDRSS_PI_401_DATA 0x00000004 +#define DDRSS_PI_402_DATA 0x00000000 +#define DDRSS_PI_403_DATA 0x00000031 +#define DDRSS_PI_404_DATA 0x00000000 +#define DDRSS_PI_405_DATA 0x00000000 +#define DDRSS_PI_406_DATA 0x00000000 +#define DDRSS_PI_407_DATA 0x20002B27 +#define DDRSS_PI_408_DATA 0x00000000 +#define DDRSS_PI_409_DATA 0x00000064 +#define DDRSS_PI_410_DATA 0x00000036 +#define DDRSS_PI_411_DATA 0x000000B1 +#define DDRSS_PI_412_DATA 0x00000000 +#define DDRSS_PI_413_DATA 0x00000000 +#define DDRSS_PI_414_DATA 0x55000000 +#define DDRSS_PI_415_DATA 0x20162B27 +#define DDRSS_PI_416_DATA 0x00000000 +#define DDRSS_PI_417_DATA 0x00000064 +#define DDRSS_PI_418_DATA 0x00000036 +#define DDRSS_PI_419_DATA 0x000000B1 +#define DDRSS_PI_420_DATA 0x00000000 +#define DDRSS_PI_421_DATA 0x00000000 +#define DDRSS_PI_422_DATA 0x55000000 +#define DDRSS_PI_423_DATA 0x20162B27 +#define DDRSS_PHY_0_DATA 0x04F00000 +#define DDRSS_PHY_1_DATA 0x00000000 +#define DDRSS_PHY_2_DATA 0x00030200 +#define DDRSS_PHY_3_DATA 0x00000000 +#define DDRSS_PHY_4_DATA 0x00000000 +#define DDRSS_PHY_5_DATA 0x01030000 +#define DDRSS_PHY_6_DATA 0x00010000 +#define DDRSS_PHY_7_DATA 0x01030004 +#define DDRSS_PHY_8_DATA 0x01000000 +#define DDRSS_PHY_9_DATA 0x00000000 +#define DDRSS_PHY_10_DATA 0x00000000 +#define DDRSS_PHY_11_DATA 0x00000000 +#define DDRSS_PHY_12_DATA 0x01010000 +#define DDRSS_PHY_13_DATA 0x00010000 +#define DDRSS_PHY_14_DATA 0x00C00001 +#define DDRSS_PHY_15_DATA 0x00CC0008 +#define DDRSS_PHY_16_DATA 0x00660601 +#define DDRSS_PHY_17_DATA 0x00000003 +#define DDRSS_PHY_18_DATA 0x00000000 +#define DDRSS_PHY_19_DATA 0x00000001 +#define DDRSS_PHY_20_DATA 0x0000AAAA +#define DDRSS_PHY_21_DATA 0x00005555 +#define DDRSS_PHY_22_DATA 0x0000B5B5 +#define DDRSS_PHY_23_DATA 0x00004A4A +#define DDRSS_PHY_24_DATA 0x00005656 +#define DDRSS_PHY_25_DATA 0x0000A9A9 +#define DDRSS_PHY_26_DATA 0x0000B7B7 +#define DDRSS_PHY_27_DATA 0x00004848 +#define DDRSS_PHY_28_DATA 0x00000000 +#define DDRSS_PHY_29_DATA 0x00000000 +#define DDRSS_PHY_30_DATA 0x08000000 +#define DDRSS_PHY_31_DATA 0x0F000008 +#define DDRSS_PHY_32_DATA 0x00000F0F +#define DDRSS_PHY_33_DATA 0x00E4E400 +#define DDRSS_PHY_34_DATA 0x00071020 +#define DDRSS_PHY_35_DATA 0x000C0020 +#define DDRSS_PHY_36_DATA 0x00062000 +#define DDRSS_PHY_37_DATA 0x00000000 +#define DDRSS_PHY_38_DATA 0x55555555 +#define DDRSS_PHY_39_DATA 0xAAAAAAAA +#define DDRSS_PHY_40_DATA 0x55555555 +#define DDRSS_PHY_41_DATA 0xAAAAAAAA +#define DDRSS_PHY_42_DATA 0x00005555 +#define DDRSS_PHY_43_DATA 0x01000100 +#define DDRSS_PHY_44_DATA 0x00800180 +#define DDRSS_PHY_45_DATA 0x00000001 +#define DDRSS_PHY_46_DATA 0x00000000 +#define DDRSS_PHY_47_DATA 0x00000000 +#define DDRSS_PHY_48_DATA 0x00000000 +#define DDRSS_PHY_49_DATA 0x00000000 +#define DDRSS_PHY_50_DATA 0x00000000 +#define DDRSS_PHY_51_DATA 0x00000000 +#define DDRSS_PHY_52_DATA 0x00000000 +#define DDRSS_PHY_53_DATA 0x00000000 +#define DDRSS_PHY_54_DATA 0x00000000 +#define DDRSS_PHY_55_DATA 0x00000000 +#define DDRSS_PHY_56_DATA 0x00000000 +#define DDRSS_PHY_57_DATA 0x00000000 +#define DDRSS_PHY_58_DATA 0x00000000 +#define DDRSS_PHY_59_DATA 0x00000000 +#define DDRSS_PHY_60_DATA 0x00000000 +#define DDRSS_PHY_61_DATA 0x00000000 +#define DDRSS_PHY_62_DATA 0x00000000 +#define DDRSS_PHY_63_DATA 0x00000000 +#define DDRSS_PHY_64_DATA 0x00000000 +#define DDRSS_PHY_65_DATA 0x00000000 +#define DDRSS_PHY_66_DATA 0x00000000 +#define DDRSS_PHY_67_DATA 0x00000004 +#define DDRSS_PHY_68_DATA 0x00000000 +#define DDRSS_PHY_69_DATA 0x00000000 +#define DDRSS_PHY_70_DATA 0x00000000 +#define DDRSS_PHY_71_DATA 0x00000000 +#define DDRSS_PHY_72_DATA 0x00000000 +#define DDRSS_PHY_73_DATA 0x00000000 +#define DDRSS_PHY_74_DATA 0x081F07FF +#define DDRSS_PHY_75_DATA 0x10200080 +#define DDRSS_PHY_76_DATA 0x00000008 +#define DDRSS_PHY_77_DATA 0x00000401 +#define DDRSS_PHY_78_DATA 0x00000000 +#define DDRSS_PHY_79_DATA 0x01CC0C01 +#define DDRSS_PHY_80_DATA 0x1003CC0C +#define DDRSS_PHY_81_DATA 0x20000140 +#define DDRSS_PHY_82_DATA 0x07FF0200 +#define DDRSS_PHY_83_DATA 0x0000DD01 +#define DDRSS_PHY_84_DATA 0x00100303 +#define DDRSS_PHY_85_DATA 0x00000000 +#define DDRSS_PHY_86_DATA 0x00000000 +#define DDRSS_PHY_87_DATA 0x00041000 +#define DDRSS_PHY_88_DATA 0x00100010 +#define DDRSS_PHY_89_DATA 0x00100010 +#define DDRSS_PHY_90_DATA 0x00100010 +#define DDRSS_PHY_91_DATA 0x00100010 +#define DDRSS_PHY_92_DATA 0x02040010 +#define DDRSS_PHY_93_DATA 0x00000005 +#define DDRSS_PHY_94_DATA 0x51516042 +#define DDRSS_PHY_95_DATA 0x31C06000 +#define DDRSS_PHY_96_DATA 0x07AB0340 +#define DDRSS_PHY_97_DATA 0x00C0C001 +#define DDRSS_PHY_98_DATA 0x0D000000 +#define DDRSS_PHY_99_DATA 0x000D0C0C +#define DDRSS_PHY_100_DATA 0x42100010 +#define DDRSS_PHY_101_DATA 0x010C073E +#define DDRSS_PHY_102_DATA 0x000F0C32 +#define DDRSS_PHY_103_DATA 0x01000140 +#define DDRSS_PHY_104_DATA 0x011E0120 +#define DDRSS_PHY_105_DATA 0x00000C00 +#define DDRSS_PHY_106_DATA 0x000002DD +#define DDRSS_PHY_107_DATA 0x00030200 +#define DDRSS_PHY_108_DATA 0x02800000 +#define DDRSS_PHY_109_DATA 0x80800000 +#define DDRSS_PHY_110_DATA 0x000D2010 +#define DDRSS_PHY_111_DATA 0x76543210 +#define DDRSS_PHY_112_DATA 0x00000008 +#define DDRSS_PHY_113_DATA 0x045D045D +#define DDRSS_PHY_114_DATA 0x045D045D +#define DDRSS_PHY_115_DATA 0x045D045D +#define DDRSS_PHY_116_DATA 0x045D045D +#define DDRSS_PHY_117_DATA 0x0000045D +#define DDRSS_PHY_118_DATA 0x0000A000 +#define DDRSS_PHY_119_DATA 0x00A000A0 +#define DDRSS_PHY_120_DATA 0x00A000A0 +#define DDRSS_PHY_121_DATA 0x00A000A0 +#define DDRSS_PHY_122_DATA 0x00A000A0 +#define DDRSS_PHY_123_DATA 0x00A000A0 +#define DDRSS_PHY_124_DATA 0x00A000A0 +#define DDRSS_PHY_125_DATA 0x00A000A0 +#define DDRSS_PHY_126_DATA 0x00A000A0 +#define DDRSS_PHY_127_DATA 0x00B200A0 +#define DDRSS_PHY_128_DATA 0x01000000 +#define DDRSS_PHY_129_DATA 0x00000000 +#define DDRSS_PHY_130_DATA 0x00000000 +#define DDRSS_PHY_131_DATA 0x00080200 +#define DDRSS_PHY_132_DATA 0x00000000 +#define DDRSS_PHY_133_DATA 0x20202020 +#define DDRSS_PHY_134_DATA 0x20202020 +#define DDRSS_PHY_135_DATA 0xF0F02020 +#define DDRSS_PHY_136_DATA 0x00000000 +#define DDRSS_PHY_137_DATA 0x00000000 +#define DDRSS_PHY_138_DATA 0x00000000 +#define DDRSS_PHY_139_DATA 0x00000000 +#define DDRSS_PHY_140_DATA 0x00000000 +#define DDRSS_PHY_141_DATA 0x00000000 +#define DDRSS_PHY_142_DATA 0x00000000 +#define DDRSS_PHY_143_DATA 0x00000000 +#define DDRSS_PHY_144_DATA 0x00000000 +#define DDRSS_PHY_145_DATA 0x00000000 +#define DDRSS_PHY_146_DATA 0x00000000 +#define DDRSS_PHY_147_DATA 0x00000000 +#define DDRSS_PHY_148_DATA 0x00000000 +#define DDRSS_PHY_149_DATA 0x00000000 +#define DDRSS_PHY_150_DATA 0x00000000 +#define DDRSS_PHY_151_DATA 0x00000000 +#define DDRSS_PHY_152_DATA 0x00000000 +#define DDRSS_PHY_153_DATA 0x00000000 +#define DDRSS_PHY_154_DATA 0x00000000 +#define DDRSS_PHY_155_DATA 0x00000000 +#define DDRSS_PHY_156_DATA 0x00000000 +#define DDRSS_PHY_157_DATA 0x00000000 +#define DDRSS_PHY_158_DATA 0x00000000 +#define DDRSS_PHY_159_DATA 0x00000000 +#define DDRSS_PHY_160_DATA 0x00000000 +#define DDRSS_PHY_161_DATA 0x00000000 +#define DDRSS_PHY_162_DATA 0x00000000 +#define DDRSS_PHY_163_DATA 0x00000000 +#define DDRSS_PHY_164_DATA 0x00000000 +#define DDRSS_PHY_165_DATA 0x00000000 +#define DDRSS_PHY_166_DATA 0x00000000 +#define DDRSS_PHY_167_DATA 0x00000000 +#define DDRSS_PHY_168_DATA 0x00000000 +#define DDRSS_PHY_169_DATA 0x00000000 +#define DDRSS_PHY_170_DATA 0x00000000 +#define DDRSS_PHY_171_DATA 0x00000000 +#define DDRSS_PHY_172_DATA 0x00000000 +#define DDRSS_PHY_173_DATA 0x00000000 +#define DDRSS_PHY_174_DATA 0x00000000 +#define DDRSS_PHY_175_DATA 0x00000000 +#define DDRSS_PHY_176_DATA 0x00000000 +#define DDRSS_PHY_177_DATA 0x00000000 +#define DDRSS_PHY_178_DATA 0x00000000 +#define DDRSS_PHY_179_DATA 0x00000000 +#define DDRSS_PHY_180_DATA 0x00000000 +#define DDRSS_PHY_181_DATA 0x00000000 +#define DDRSS_PHY_182_DATA 0x00000000 +#define DDRSS_PHY_183_DATA 0x00000000 +#define DDRSS_PHY_184_DATA 0x00000000 +#define DDRSS_PHY_185_DATA 0x00000000 +#define DDRSS_PHY_186_DATA 0x00000000 +#define DDRSS_PHY_187_DATA 0x00000000 +#define DDRSS_PHY_188_DATA 0x00000000 +#define DDRSS_PHY_189_DATA 0x00000000 +#define DDRSS_PHY_190_DATA 0x00000000 +#define DDRSS_PHY_191_DATA 0x00000000 +#define DDRSS_PHY_192_DATA 0x00000000 +#define DDRSS_PHY_193_DATA 0x00000000 +#define DDRSS_PHY_194_DATA 0x00000000 +#define DDRSS_PHY_195_DATA 0x00000000 +#define DDRSS_PHY_196_DATA 0x00000000 +#define DDRSS_PHY_197_DATA 0x00000000 +#define DDRSS_PHY_198_DATA 0x00000000 +#define DDRSS_PHY_199_DATA 0x00000000 +#define DDRSS_PHY_200_DATA 0x00000000 +#define DDRSS_PHY_201_DATA 0x00000000 +#define DDRSS_PHY_202_DATA 0x00000000 +#define DDRSS_PHY_203_DATA 0x00000000 +#define DDRSS_PHY_204_DATA 0x00000000 +#define DDRSS_PHY_205_DATA 0x00000000 +#define DDRSS_PHY_206_DATA 0x00000000 +#define DDRSS_PHY_207_DATA 0x00000000 +#define DDRSS_PHY_208_DATA 0x00000000 +#define DDRSS_PHY_209_DATA 0x00000000 +#define DDRSS_PHY_210_DATA 0x00000000 +#define DDRSS_PHY_211_DATA 0x00000000 +#define DDRSS_PHY_212_DATA 0x00000000 +#define DDRSS_PHY_213_DATA 0x00000000 +#define DDRSS_PHY_214_DATA 0x00000000 +#define DDRSS_PHY_215_DATA 0x00000000 +#define DDRSS_PHY_216_DATA 0x00000000 +#define DDRSS_PHY_217_DATA 0x00000000 +#define DDRSS_PHY_218_DATA 0x00000000 +#define DDRSS_PHY_219_DATA 0x00000000 +#define DDRSS_PHY_220_DATA 0x00000000 +#define DDRSS_PHY_221_DATA 0x00000000 +#define DDRSS_PHY_222_DATA 0x00000000 +#define DDRSS_PHY_223_DATA 0x00000000 +#define DDRSS_PHY_224_DATA 0x00000000 +#define DDRSS_PHY_225_DATA 0x00000000 +#define DDRSS_PHY_226_DATA 0x00000000 +#define DDRSS_PHY_227_DATA 0x00000000 +#define DDRSS_PHY_228_DATA 0x00000000 +#define DDRSS_PHY_229_DATA 0x00000000 +#define DDRSS_PHY_230_DATA 0x00000000 +#define DDRSS_PHY_231_DATA 0x00000000 +#define DDRSS_PHY_232_DATA 0x00000000 +#define DDRSS_PHY_233_DATA 0x00000000 +#define DDRSS_PHY_234_DATA 0x00000000 +#define DDRSS_PHY_235_DATA 0x00000000 +#define DDRSS_PHY_236_DATA 0x00000000 +#define DDRSS_PHY_237_DATA 0x00000000 +#define DDRSS_PHY_238_DATA 0x00000000 +#define DDRSS_PHY_239_DATA 0x00000000 +#define DDRSS_PHY_240_DATA 0x00000000 +#define DDRSS_PHY_241_DATA 0x00000000 +#define DDRSS_PHY_242_DATA 0x00000000 +#define DDRSS_PHY_243_DATA 0x00000000 +#define DDRSS_PHY_244_DATA 0x00000000 +#define DDRSS_PHY_245_DATA 0x00000000 +#define DDRSS_PHY_246_DATA 0x00000000 +#define DDRSS_PHY_247_DATA 0x00000000 +#define DDRSS_PHY_248_DATA 0x00000000 +#define DDRSS_PHY_249_DATA 0x00000000 +#define DDRSS_PHY_250_DATA 0x00000000 +#define DDRSS_PHY_251_DATA 0x00000000 +#define DDRSS_PHY_252_DATA 0x00000000 +#define DDRSS_PHY_253_DATA 0x00000000 +#define DDRSS_PHY_254_DATA 0x00000000 +#define DDRSS_PHY_255_DATA 0x00000000 +#define DDRSS_PHY_256_DATA 0x04F00000 +#define DDRSS_PHY_257_DATA 0x00000000 +#define DDRSS_PHY_258_DATA 0x00030200 +#define DDRSS_PHY_259_DATA 0x00000000 +#define DDRSS_PHY_260_DATA 0x00000000 +#define DDRSS_PHY_261_DATA 0x01030000 +#define DDRSS_PHY_262_DATA 0x00010000 +#define DDRSS_PHY_263_DATA 0x01030004 +#define DDRSS_PHY_264_DATA 0x01000000 +#define DDRSS_PHY_265_DATA 0x00000000 +#define DDRSS_PHY_266_DATA 0x00000000 +#define DDRSS_PHY_267_DATA 0x00000000 +#define DDRSS_PHY_268_DATA 0x01010000 +#define DDRSS_PHY_269_DATA 0x00010000 +#define DDRSS_PHY_270_DATA 0x00C00001 +#define DDRSS_PHY_271_DATA 0x00CC0008 +#define DDRSS_PHY_272_DATA 0x00660601 +#define DDRSS_PHY_273_DATA 0x00000003 +#define DDRSS_PHY_274_DATA 0x00000000 +#define DDRSS_PHY_275_DATA 0x00000001 +#define DDRSS_PHY_276_DATA 0x0000AAAA +#define DDRSS_PHY_277_DATA 0x00005555 +#define DDRSS_PHY_278_DATA 0x0000B5B5 +#define DDRSS_PHY_279_DATA 0x00004A4A +#define DDRSS_PHY_280_DATA 0x00005656 +#define DDRSS_PHY_281_DATA 0x0000A9A9 +#define DDRSS_PHY_282_DATA 0x0000B7B7 +#define DDRSS_PHY_283_DATA 0x00004848 +#define DDRSS_PHY_284_DATA 0x00000000 +#define DDRSS_PHY_285_DATA 0x00000000 +#define DDRSS_PHY_286_DATA 0x08000000 +#define DDRSS_PHY_287_DATA 0x0F000008 +#define DDRSS_PHY_288_DATA 0x00000F0F +#define DDRSS_PHY_289_DATA 0x00E4E400 +#define DDRSS_PHY_290_DATA 0x00071020 +#define DDRSS_PHY_291_DATA 0x000C0020 +#define DDRSS_PHY_292_DATA 0x00062000 +#define DDRSS_PHY_293_DATA 0x00000000 +#define DDRSS_PHY_294_DATA 0x55555555 +#define DDRSS_PHY_295_DATA 0xAAAAAAAA +#define DDRSS_PHY_296_DATA 0x55555555 +#define DDRSS_PHY_297_DATA 0xAAAAAAAA +#define DDRSS_PHY_298_DATA 0x00005555 +#define DDRSS_PHY_299_DATA 0x01000100 +#define DDRSS_PHY_300_DATA 0x00800180 +#define DDRSS_PHY_301_DATA 0x00000000 +#define DDRSS_PHY_302_DATA 0x00000000 +#define DDRSS_PHY_303_DATA 0x00000000 +#define DDRSS_PHY_304_DATA 0x00000000 +#define DDRSS_PHY_305_DATA 0x00000000 +#define DDRSS_PHY_306_DATA 0x00000000 +#define DDRSS_PHY_307_DATA 0x00000000 +#define DDRSS_PHY_308_DATA 0x00000000 +#define DDRSS_PHY_309_DATA 0x00000000 +#define DDRSS_PHY_310_DATA 0x00000000 +#define DDRSS_PHY_311_DATA 0x00000000 +#define DDRSS_PHY_312_DATA 0x00000000 +#define DDRSS_PHY_313_DATA 0x00000000 +#define DDRSS_PHY_314_DATA 0x00000000 +#define DDRSS_PHY_315_DATA 0x00000000 +#define DDRSS_PHY_316_DATA 0x00000000 +#define DDRSS_PHY_317_DATA 0x00000000 +#define DDRSS_PHY_318_DATA 0x00000000 +#define DDRSS_PHY_319_DATA 0x00000000 +#define DDRSS_PHY_320_DATA 0x00000000 +#define DDRSS_PHY_321_DATA 0x00000000 +#define DDRSS_PHY_322_DATA 0x00000000 +#define DDRSS_PHY_323_DATA 0x00000004 +#define DDRSS_PHY_324_DATA 0x00000000 +#define DDRSS_PHY_325_DATA 0x00000000 +#define DDRSS_PHY_326_DATA 0x00000000 +#define DDRSS_PHY_327_DATA 0x00000000 +#define DDRSS_PHY_328_DATA 0x00000000 +#define DDRSS_PHY_329_DATA 0x00000000 +#define DDRSS_PHY_330_DATA 0x081F07FF +#define DDRSS_PHY_331_DATA 0x10200080 +#define DDRSS_PHY_332_DATA 0x00000008 +#define DDRSS_PHY_333_DATA 0x00000401 +#define DDRSS_PHY_334_DATA 0x00000000 +#define DDRSS_PHY_335_DATA 0x01CC0C01 +#define DDRSS_PHY_336_DATA 0x1003CC0C +#define DDRSS_PHY_337_DATA 0x20000140 +#define DDRSS_PHY_338_DATA 0x07FF0200 +#define DDRSS_PHY_339_DATA 0x0000DD01 +#define DDRSS_PHY_340_DATA 0x00100303 +#define DDRSS_PHY_341_DATA 0x00000000 +#define DDRSS_PHY_342_DATA 0x00000000 +#define DDRSS_PHY_343_DATA 0x00041000 +#define DDRSS_PHY_344_DATA 0x00100010 +#define DDRSS_PHY_345_DATA 0x00100010 +#define DDRSS_PHY_346_DATA 0x00100010 +#define DDRSS_PHY_347_DATA 0x00100010 +#define DDRSS_PHY_348_DATA 0x02040010 +#define DDRSS_PHY_349_DATA 0x00000005 +#define DDRSS_PHY_350_DATA 0x51516042 +#define DDRSS_PHY_351_DATA 0x31C06000 +#define DDRSS_PHY_352_DATA 0x07AB0340 +#define DDRSS_PHY_353_DATA 0x00C0C001 +#define DDRSS_PHY_354_DATA 0x0D000000 +#define DDRSS_PHY_355_DATA 0x000D0C0C +#define DDRSS_PHY_356_DATA 0x42100010 +#define DDRSS_PHY_357_DATA 0x010C073E +#define DDRSS_PHY_358_DATA 0x000F0C32 +#define DDRSS_PHY_359_DATA 0x01000140 +#define DDRSS_PHY_360_DATA 0x011E0120 +#define DDRSS_PHY_361_DATA 0x00000C00 +#define DDRSS_PHY_362_DATA 0x000002DD +#define DDRSS_PHY_363_DATA 0x00030200 +#define DDRSS_PHY_364_DATA 0x02800000 +#define DDRSS_PHY_365_DATA 0x80800000 +#define DDRSS_PHY_366_DATA 0x000D2010 +#define DDRSS_PHY_367_DATA 0x76543210 +#define DDRSS_PHY_368_DATA 0x00000008 +#define DDRSS_PHY_369_DATA 0x045D045D +#define DDRSS_PHY_370_DATA 0x045D045D +#define DDRSS_PHY_371_DATA 0x045D045D +#define DDRSS_PHY_372_DATA 0x045D045D +#define DDRSS_PHY_373_DATA 0x0000045D +#define DDRSS_PHY_374_DATA 0x0000A000 +#define DDRSS_PHY_375_DATA 0x00A000A0 +#define DDRSS_PHY_376_DATA 0x00A000A0 +#define DDRSS_PHY_377_DATA 0x00A000A0 +#define DDRSS_PHY_378_DATA 0x00A000A0 +#define DDRSS_PHY_379_DATA 0x00A000A0 +#define DDRSS_PHY_380_DATA 0x00A000A0 +#define DDRSS_PHY_381_DATA 0x00A000A0 +#define DDRSS_PHY_382_DATA 0x00A000A0 +#define DDRSS_PHY_383_DATA 0x00B200A0 +#define DDRSS_PHY_384_DATA 0x01000000 +#define DDRSS_PHY_385_DATA 0x00000000 +#define DDRSS_PHY_386_DATA 0x00000000 +#define DDRSS_PHY_387_DATA 0x00080200 +#define DDRSS_PHY_388_DATA 0x00000000 +#define DDRSS_PHY_389_DATA 0x20202020 +#define DDRSS_PHY_390_DATA 0x20202020 +#define DDRSS_PHY_391_DATA 0xF0F02020 +#define DDRSS_PHY_392_DATA 0x00000000 +#define DDRSS_PHY_393_DATA 0x00000000 +#define DDRSS_PHY_394_DATA 0x00000000 +#define DDRSS_PHY_395_DATA 0x00000000 +#define DDRSS_PHY_396_DATA 0x00000000 +#define DDRSS_PHY_397_DATA 0x00000000 +#define DDRSS_PHY_398_DATA 0x00000000 +#define DDRSS_PHY_399_DATA 0x00000000 +#define DDRSS_PHY_400_DATA 0x00000000 +#define DDRSS_PHY_401_DATA 0x00000000 +#define DDRSS_PHY_402_DATA 0x00000000 +#define DDRSS_PHY_403_DATA 0x00000000 +#define DDRSS_PHY_404_DATA 0x00000000 +#define DDRSS_PHY_405_DATA 0x00000000 +#define DDRSS_PHY_406_DATA 0x00000000 +#define DDRSS_PHY_407_DATA 0x00000000 +#define DDRSS_PHY_408_DATA 0x00000000 +#define DDRSS_PHY_409_DATA 0x00000000 +#define DDRSS_PHY_410_DATA 0x00000000 +#define DDRSS_PHY_411_DATA 0x00000000 +#define DDRSS_PHY_412_DATA 0x00000000 +#define DDRSS_PHY_413_DATA 0x00000000 +#define DDRSS_PHY_414_DATA 0x00000000 +#define DDRSS_PHY_415_DATA 0x00000000 +#define DDRSS_PHY_416_DATA 0x00000000 +#define DDRSS_PHY_417_DATA 0x00000000 +#define DDRSS_PHY_418_DATA 0x00000000 +#define DDRSS_PHY_419_DATA 0x00000000 +#define DDRSS_PHY_420_DATA 0x00000000 +#define DDRSS_PHY_421_DATA 0x00000000 +#define DDRSS_PHY_422_DATA 0x00000000 +#define DDRSS_PHY_423_DATA 0x00000000 +#define DDRSS_PHY_424_DATA 0x00000000 +#define DDRSS_PHY_425_DATA 0x00000000 +#define DDRSS_PHY_426_DATA 0x00000000 +#define DDRSS_PHY_427_DATA 0x00000000 +#define DDRSS_PHY_428_DATA 0x00000000 +#define DDRSS_PHY_429_DATA 0x00000000 +#define DDRSS_PHY_430_DATA 0x00000000 +#define DDRSS_PHY_431_DATA 0x00000000 +#define DDRSS_PHY_432_DATA 0x00000000 +#define DDRSS_PHY_433_DATA 0x00000000 +#define DDRSS_PHY_434_DATA 0x00000000 +#define DDRSS_PHY_435_DATA 0x00000000 +#define DDRSS_PHY_436_DATA 0x00000000 +#define DDRSS_PHY_437_DATA 0x00000000 +#define DDRSS_PHY_438_DATA 0x00000000 +#define DDRSS_PHY_439_DATA 0x00000000 +#define DDRSS_PHY_440_DATA 0x00000000 +#define DDRSS_PHY_441_DATA 0x00000000 +#define DDRSS_PHY_442_DATA 0x00000000 +#define DDRSS_PHY_443_DATA 0x00000000 +#define DDRSS_PHY_444_DATA 0x00000000 +#define DDRSS_PHY_445_DATA 0x00000000 +#define DDRSS_PHY_446_DATA 0x00000000 +#define DDRSS_PHY_447_DATA 0x00000000 +#define DDRSS_PHY_448_DATA 0x00000000 +#define DDRSS_PHY_449_DATA 0x00000000 +#define DDRSS_PHY_450_DATA 0x00000000 +#define DDRSS_PHY_451_DATA 0x00000000 +#define DDRSS_PHY_452_DATA 0x00000000 +#define DDRSS_PHY_453_DATA 0x00000000 +#define DDRSS_PHY_454_DATA 0x00000000 +#define DDRSS_PHY_455_DATA 0x00000000 +#define DDRSS_PHY_456_DATA 0x00000000 +#define DDRSS_PHY_457_DATA 0x00000000 +#define DDRSS_PHY_458_DATA 0x00000000 +#define DDRSS_PHY_459_DATA 0x00000000 +#define DDRSS_PHY_460_DATA 0x00000000 +#define DDRSS_PHY_461_DATA 0x00000000 +#define DDRSS_PHY_462_DATA 0x00000000 +#define DDRSS_PHY_463_DATA 0x00000000 +#define DDRSS_PHY_464_DATA 0x00000000 +#define DDRSS_PHY_465_DATA 0x00000000 +#define DDRSS_PHY_466_DATA 0x00000000 +#define DDRSS_PHY_467_DATA 0x00000000 +#define DDRSS_PHY_468_DATA 0x00000000 +#define DDRSS_PHY_469_DATA 0x00000000 +#define DDRSS_PHY_470_DATA 0x00000000 +#define DDRSS_PHY_471_DATA 0x00000000 +#define DDRSS_PHY_472_DATA 0x00000000 +#define DDRSS_PHY_473_DATA 0x00000000 +#define DDRSS_PHY_474_DATA 0x00000000 +#define DDRSS_PHY_475_DATA 0x00000000 +#define DDRSS_PHY_476_DATA 0x00000000 +#define DDRSS_PHY_477_DATA 0x00000000 +#define DDRSS_PHY_478_DATA 0x00000000 +#define DDRSS_PHY_479_DATA 0x00000000 +#define DDRSS_PHY_480_DATA 0x00000000 +#define DDRSS_PHY_481_DATA 0x00000000 +#define DDRSS_PHY_482_DATA 0x00000000 +#define DDRSS_PHY_483_DATA 0x00000000 +#define DDRSS_PHY_484_DATA 0x00000000 +#define DDRSS_PHY_485_DATA 0x00000000 +#define DDRSS_PHY_486_DATA 0x00000000 +#define DDRSS_PHY_487_DATA 0x00000000 +#define DDRSS_PHY_488_DATA 0x00000000 +#define DDRSS_PHY_489_DATA 0x00000000 +#define DDRSS_PHY_490_DATA 0x00000000 +#define DDRSS_PHY_491_DATA 0x00000000 +#define DDRSS_PHY_492_DATA 0x00000000 +#define DDRSS_PHY_493_DATA 0x00000000 +#define DDRSS_PHY_494_DATA 0x00000000 +#define DDRSS_PHY_495_DATA 0x00000000 +#define DDRSS_PHY_496_DATA 0x00000000 +#define DDRSS_PHY_497_DATA 0x00000000 +#define DDRSS_PHY_498_DATA 0x00000000 +#define DDRSS_PHY_499_DATA 0x00000000 +#define DDRSS_PHY_500_DATA 0x00000000 +#define DDRSS_PHY_501_DATA 0x00000000 +#define DDRSS_PHY_502_DATA 0x00000000 +#define DDRSS_PHY_503_DATA 0x00000000 +#define DDRSS_PHY_504_DATA 0x00000000 +#define DDRSS_PHY_505_DATA 0x00000000 +#define DDRSS_PHY_506_DATA 0x00000000 +#define DDRSS_PHY_507_DATA 0x00000000 +#define DDRSS_PHY_508_DATA 0x00000000 +#define DDRSS_PHY_509_DATA 0x00000000 +#define DDRSS_PHY_510_DATA 0x00000000 +#define DDRSS_PHY_511_DATA 0x00000000 +#define DDRSS_PHY_512_DATA 0x04F00000 +#define DDRSS_PHY_513_DATA 0x00000000 +#define DDRSS_PHY_514_DATA 0x00030200 +#define DDRSS_PHY_515_DATA 0x00000000 +#define DDRSS_PHY_516_DATA 0x00000000 +#define DDRSS_PHY_517_DATA 0x01030000 +#define DDRSS_PHY_518_DATA 0x00010000 +#define DDRSS_PHY_519_DATA 0x01030004 +#define DDRSS_PHY_520_DATA 0x01000000 +#define DDRSS_PHY_521_DATA 0x00000000 +#define DDRSS_PHY_522_DATA 0x00000000 +#define DDRSS_PHY_523_DATA 0x00000000 +#define DDRSS_PHY_524_DATA 0x01010000 +#define DDRSS_PHY_525_DATA 0x00010000 +#define DDRSS_PHY_526_DATA 0x00C00001 +#define DDRSS_PHY_527_DATA 0x00CC0008 +#define DDRSS_PHY_528_DATA 0x00660601 +#define DDRSS_PHY_529_DATA 0x00000003 +#define DDRSS_PHY_530_DATA 0x00000000 +#define DDRSS_PHY_531_DATA 0x00000001 +#define DDRSS_PHY_532_DATA 0x0000AAAA +#define DDRSS_PHY_533_DATA 0x00005555 +#define DDRSS_PHY_534_DATA 0x0000B5B5 +#define DDRSS_PHY_535_DATA 0x00004A4A +#define DDRSS_PHY_536_DATA 0x00005656 +#define DDRSS_PHY_537_DATA 0x0000A9A9 +#define DDRSS_PHY_538_DATA 0x0000B7B7 +#define DDRSS_PHY_539_DATA 0x00004848 +#define DDRSS_PHY_540_DATA 0x00000000 +#define DDRSS_PHY_541_DATA 0x00000000 +#define DDRSS_PHY_542_DATA 0x08000000 +#define DDRSS_PHY_543_DATA 0x0F000008 +#define DDRSS_PHY_544_DATA 0x00000F0F +#define DDRSS_PHY_545_DATA 0x00E4E400 +#define DDRSS_PHY_546_DATA 0x00071020 +#define DDRSS_PHY_547_DATA 0x000C0020 +#define DDRSS_PHY_548_DATA 0x00062000 +#define DDRSS_PHY_549_DATA 0x00000000 +#define DDRSS_PHY_550_DATA 0x55555555 +#define DDRSS_PHY_551_DATA 0xAAAAAAAA +#define DDRSS_PHY_552_DATA 0x55555555 +#define DDRSS_PHY_553_DATA 0xAAAAAAAA +#define DDRSS_PHY_554_DATA 0x00005555 +#define DDRSS_PHY_555_DATA 0x01000100 +#define DDRSS_PHY_556_DATA 0x00800180 +#define DDRSS_PHY_557_DATA 0x00000001 +#define DDRSS_PHY_558_DATA 0x00000000 +#define DDRSS_PHY_559_DATA 0x00000000 +#define DDRSS_PHY_560_DATA 0x00000000 +#define DDRSS_PHY_561_DATA 0x00000000 +#define DDRSS_PHY_562_DATA 0x00000000 +#define DDRSS_PHY_563_DATA 0x00000000 +#define DDRSS_PHY_564_DATA 0x00000000 +#define DDRSS_PHY_565_DATA 0x00000000 +#define DDRSS_PHY_566_DATA 0x00000000 +#define DDRSS_PHY_567_DATA 0x00000000 +#define DDRSS_PHY_568_DATA 0x00000000 +#define DDRSS_PHY_569_DATA 0x00000000 +#define DDRSS_PHY_570_DATA 0x00000000 +#define DDRSS_PHY_571_DATA 0x00000000 +#define DDRSS_PHY_572_DATA 0x00000000 +#define DDRSS_PHY_573_DATA 0x00000000 +#define DDRSS_PHY_574_DATA 0x00000000 +#define DDRSS_PHY_575_DATA 0x00000000 +#define DDRSS_PHY_576_DATA 0x00000000 +#define DDRSS_PHY_577_DATA 0x00000000 +#define DDRSS_PHY_578_DATA 0x00000000 +#define DDRSS_PHY_579_DATA 0x00000004 +#define DDRSS_PHY_580_DATA 0x00000000 +#define DDRSS_PHY_581_DATA 0x00000000 +#define DDRSS_PHY_582_DATA 0x00000000 +#define DDRSS_PHY_583_DATA 0x00000000 +#define DDRSS_PHY_584_DATA 0x00000000 +#define DDRSS_PHY_585_DATA 0x00000000 +#define DDRSS_PHY_586_DATA 0x081F07FF +#define DDRSS_PHY_587_DATA 0x10200080 +#define DDRSS_PHY_588_DATA 0x00000008 +#define DDRSS_PHY_589_DATA 0x00000401 +#define DDRSS_PHY_590_DATA 0x00000000 +#define DDRSS_PHY_591_DATA 0x01CC0C01 +#define DDRSS_PHY_592_DATA 0x1003CC0C +#define DDRSS_PHY_593_DATA 0x20000140 +#define DDRSS_PHY_594_DATA 0x07FF0200 +#define DDRSS_PHY_595_DATA 0x0000DD01 +#define DDRSS_PHY_596_DATA 0x00100303 +#define DDRSS_PHY_597_DATA 0x00000000 +#define DDRSS_PHY_598_DATA 0x00000000 +#define DDRSS_PHY_599_DATA 0x00041000 +#define DDRSS_PHY_600_DATA 0x00100010 +#define DDRSS_PHY_601_DATA 0x00100010 +#define DDRSS_PHY_602_DATA 0x00100010 +#define DDRSS_PHY_603_DATA 0x00100010 +#define DDRSS_PHY_604_DATA 0x02040010 +#define DDRSS_PHY_605_DATA 0x00000005 +#define DDRSS_PHY_606_DATA 0x51516042 +#define DDRSS_PHY_607_DATA 0x31C06000 +#define DDRSS_PHY_608_DATA 0x07AB0340 +#define DDRSS_PHY_609_DATA 0x00C0C001 +#define DDRSS_PHY_610_DATA 0x0D000000 +#define DDRSS_PHY_611_DATA 0x000D0C0C +#define DDRSS_PHY_612_DATA 0x42100010 +#define DDRSS_PHY_613_DATA 0x010C073E +#define DDRSS_PHY_614_DATA 0x000F0C32 +#define DDRSS_PHY_615_DATA 0x01000140 +#define DDRSS_PHY_616_DATA 0x011E0120 +#define DDRSS_PHY_617_DATA 0x00000C00 +#define DDRSS_PHY_618_DATA 0x000002DD +#define DDRSS_PHY_619_DATA 0x00030200 +#define DDRSS_PHY_620_DATA 0x02800000 +#define DDRSS_PHY_621_DATA 0x80800000 +#define DDRSS_PHY_622_DATA 0x000D2010 +#define DDRSS_PHY_623_DATA 0x76543210 +#define DDRSS_PHY_624_DATA 0x00000008 +#define DDRSS_PHY_625_DATA 0x045D045D +#define DDRSS_PHY_626_DATA 0x045D045D +#define DDRSS_PHY_627_DATA 0x045D045D +#define DDRSS_PHY_628_DATA 0x045D045D +#define DDRSS_PHY_629_DATA 0x0000045D +#define DDRSS_PHY_630_DATA 0x0000A000 +#define DDRSS_PHY_631_DATA 0x00A000A0 +#define DDRSS_PHY_632_DATA 0x00A000A0 +#define DDRSS_PHY_633_DATA 0x00A000A0 +#define DDRSS_PHY_634_DATA 0x00A000A0 +#define DDRSS_PHY_635_DATA 0x00A000A0 +#define DDRSS_PHY_636_DATA 0x00A000A0 +#define DDRSS_PHY_637_DATA 0x00A000A0 +#define DDRSS_PHY_638_DATA 0x00A000A0 +#define DDRSS_PHY_639_DATA 0x00B200A0 +#define DDRSS_PHY_640_DATA 0x01000000 +#define DDRSS_PHY_641_DATA 0x00000000 +#define DDRSS_PHY_642_DATA 0x00000000 +#define DDRSS_PHY_643_DATA 0x00080200 +#define DDRSS_PHY_644_DATA 0x00000000 +#define DDRSS_PHY_645_DATA 0x20202020 +#define DDRSS_PHY_646_DATA 0x20202020 +#define DDRSS_PHY_647_DATA 0xF0F02020 +#define DDRSS_PHY_648_DATA 0x00000000 +#define DDRSS_PHY_649_DATA 0x00000000 +#define DDRSS_PHY_650_DATA 0x00000000 +#define DDRSS_PHY_651_DATA 0x00000000 +#define DDRSS_PHY_652_DATA 0x00000000 +#define DDRSS_PHY_653_DATA 0x00000000 +#define DDRSS_PHY_654_DATA 0x00000000 +#define DDRSS_PHY_655_DATA 0x00000000 +#define DDRSS_PHY_656_DATA 0x00000000 +#define DDRSS_PHY_657_DATA 0x00000000 +#define DDRSS_PHY_658_DATA 0x00000000 +#define DDRSS_PHY_659_DATA 0x00000000 +#define DDRSS_PHY_660_DATA 0x00000000 +#define DDRSS_PHY_661_DATA 0x00000000 +#define DDRSS_PHY_662_DATA 0x00000000 +#define DDRSS_PHY_663_DATA 0x00000000 +#define DDRSS_PHY_664_DATA 0x00000000 +#define DDRSS_PHY_665_DATA 0x00000000 +#define DDRSS_PHY_666_DATA 0x00000000 +#define DDRSS_PHY_667_DATA 0x00000000 +#define DDRSS_PHY_668_DATA 0x00000000 +#define DDRSS_PHY_669_DATA 0x00000000 +#define DDRSS_PHY_670_DATA 0x00000000 +#define DDRSS_PHY_671_DATA 0x00000000 +#define DDRSS_PHY_672_DATA 0x00000000 +#define DDRSS_PHY_673_DATA 0x00000000 +#define DDRSS_PHY_674_DATA 0x00000000 +#define DDRSS_PHY_675_DATA 0x00000000 +#define DDRSS_PHY_676_DATA 0x00000000 +#define DDRSS_PHY_677_DATA 0x00000000 +#define DDRSS_PHY_678_DATA 0x00000000 +#define DDRSS_PHY_679_DATA 0x00000000 +#define DDRSS_PHY_680_DATA 0x00000000 +#define DDRSS_PHY_681_DATA 0x00000000 +#define DDRSS_PHY_682_DATA 0x00000000 +#define DDRSS_PHY_683_DATA 0x00000000 +#define DDRSS_PHY_684_DATA 0x00000000 +#define DDRSS_PHY_685_DATA 0x00000000 +#define DDRSS_PHY_686_DATA 0x00000000 +#define DDRSS_PHY_687_DATA 0x00000000 +#define DDRSS_PHY_688_DATA 0x00000000 +#define DDRSS_PHY_689_DATA 0x00000000 +#define DDRSS_PHY_690_DATA 0x00000000 +#define DDRSS_PHY_691_DATA 0x00000000 +#define DDRSS_PHY_692_DATA 0x00000000 +#define DDRSS_PHY_693_DATA 0x00000000 +#define DDRSS_PHY_694_DATA 0x00000000 +#define DDRSS_PHY_695_DATA 0x00000000 +#define DDRSS_PHY_696_DATA 0x00000000 +#define DDRSS_PHY_697_DATA 0x00000000 +#define DDRSS_PHY_698_DATA 0x00000000 +#define DDRSS_PHY_699_DATA 0x00000000 +#define DDRSS_PHY_700_DATA 0x00000000 +#define DDRSS_PHY_701_DATA 0x00000000 +#define DDRSS_PHY_702_DATA 0x00000000 +#define DDRSS_PHY_703_DATA 0x00000000 +#define DDRSS_PHY_704_DATA 0x00000000 +#define DDRSS_PHY_705_DATA 0x00000000 +#define DDRSS_PHY_706_DATA 0x00000000 +#define DDRSS_PHY_707_DATA 0x00000000 +#define DDRSS_PHY_708_DATA 0x00000000 +#define DDRSS_PHY_709_DATA 0x00000000 +#define DDRSS_PHY_710_DATA 0x00000000 +#define DDRSS_PHY_711_DATA 0x00000000 +#define DDRSS_PHY_712_DATA 0x00000000 +#define DDRSS_PHY_713_DATA 0x00000000 +#define DDRSS_PHY_714_DATA 0x00000000 +#define DDRSS_PHY_715_DATA 0x00000000 +#define DDRSS_PHY_716_DATA 0x00000000 +#define DDRSS_PHY_717_DATA 0x00000000 +#define DDRSS_PHY_718_DATA 0x00000000 +#define DDRSS_PHY_719_DATA 0x00000000 +#define DDRSS_PHY_720_DATA 0x00000000 +#define DDRSS_PHY_721_DATA 0x00000000 +#define DDRSS_PHY_722_DATA 0x00000000 +#define DDRSS_PHY_723_DATA 0x00000000 +#define DDRSS_PHY_724_DATA 0x00000000 +#define DDRSS_PHY_725_DATA 0x00000000 +#define DDRSS_PHY_726_DATA 0x00000000 +#define DDRSS_PHY_727_DATA 0x00000000 +#define DDRSS_PHY_728_DATA 0x00000000 +#define DDRSS_PHY_729_DATA 0x00000000 +#define DDRSS_PHY_730_DATA 0x00000000 +#define DDRSS_PHY_731_DATA 0x00000000 +#define DDRSS_PHY_732_DATA 0x00000000 +#define DDRSS_PHY_733_DATA 0x00000000 +#define DDRSS_PHY_734_DATA 0x00000000 +#define DDRSS_PHY_735_DATA 0x00000000 +#define DDRSS_PHY_736_DATA 0x00000000 +#define DDRSS_PHY_737_DATA 0x00000000 +#define DDRSS_PHY_738_DATA 0x00000000 +#define DDRSS_PHY_739_DATA 0x00000000 +#define DDRSS_PHY_740_DATA 0x00000000 +#define DDRSS_PHY_741_DATA 0x00000000 +#define DDRSS_PHY_742_DATA 0x00000000 +#define DDRSS_PHY_743_DATA 0x00000000 +#define DDRSS_PHY_744_DATA 0x00000000 +#define DDRSS_PHY_745_DATA 0x00000000 +#define DDRSS_PHY_746_DATA 0x00000000 +#define DDRSS_PHY_747_DATA 0x00000000 +#define DDRSS_PHY_748_DATA 0x00000000 +#define DDRSS_PHY_749_DATA 0x00000000 +#define DDRSS_PHY_750_DATA 0x00000000 +#define DDRSS_PHY_751_DATA 0x00000000 +#define DDRSS_PHY_752_DATA 0x00000000 +#define DDRSS_PHY_753_DATA 0x00000000 +#define DDRSS_PHY_754_DATA 0x00000000 +#define DDRSS_PHY_755_DATA 0x00000000 +#define DDRSS_PHY_756_DATA 0x00000000 +#define DDRSS_PHY_757_DATA 0x00000000 +#define DDRSS_PHY_758_DATA 0x00000000 +#define DDRSS_PHY_759_DATA 0x00000000 +#define DDRSS_PHY_760_DATA 0x00000000 +#define DDRSS_PHY_761_DATA 0x00000000 +#define DDRSS_PHY_762_DATA 0x00000000 +#define DDRSS_PHY_763_DATA 0x00000000 +#define DDRSS_PHY_764_DATA 0x00000000 +#define DDRSS_PHY_765_DATA 0x00000000 +#define DDRSS_PHY_766_DATA 0x00000000 +#define DDRSS_PHY_767_DATA 0x00000000 +#define DDRSS_PHY_768_DATA 0x04F00000 +#define DDRSS_PHY_769_DATA 0x00000000 +#define DDRSS_PHY_770_DATA 0x00030200 +#define DDRSS_PHY_771_DATA 0x00000000 +#define DDRSS_PHY_772_DATA 0x00000000 +#define DDRSS_PHY_773_DATA 0x01030000 +#define DDRSS_PHY_774_DATA 0x00010000 +#define DDRSS_PHY_775_DATA 0x01030004 +#define DDRSS_PHY_776_DATA 0x01000000 +#define DDRSS_PHY_777_DATA 0x00000000 +#define DDRSS_PHY_778_DATA 0x00000000 +#define DDRSS_PHY_779_DATA 0x00000000 +#define DDRSS_PHY_780_DATA 0x01010000 +#define DDRSS_PHY_781_DATA 0x00010000 +#define DDRSS_PHY_782_DATA 0x00C00001 +#define DDRSS_PHY_783_DATA 0x00CC0008 +#define DDRSS_PHY_784_DATA 0x00660601 +#define DDRSS_PHY_785_DATA 0x00000003 +#define DDRSS_PHY_786_DATA 0x00000000 +#define DDRSS_PHY_787_DATA 0x00000001 +#define DDRSS_PHY_788_DATA 0x0000AAAA +#define DDRSS_PHY_789_DATA 0x00005555 +#define DDRSS_PHY_790_DATA 0x0000B5B5 +#define DDRSS_PHY_791_DATA 0x00004A4A +#define DDRSS_PHY_792_DATA 0x00005656 +#define DDRSS_PHY_793_DATA 0x0000A9A9 +#define DDRSS_PHY_794_DATA 0x0000B7B7 +#define DDRSS_PHY_795_DATA 0x00004848 +#define DDRSS_PHY_796_DATA 0x00000000 +#define DDRSS_PHY_797_DATA 0x00000000 +#define DDRSS_PHY_798_DATA 0x08000000 +#define DDRSS_PHY_799_DATA 0x0F000008 +#define DDRSS_PHY_800_DATA 0x00000F0F +#define DDRSS_PHY_801_DATA 0x00E4E400 +#define DDRSS_PHY_802_DATA 0x00071020 +#define DDRSS_PHY_803_DATA 0x000C0020 +#define DDRSS_PHY_804_DATA 0x00062000 +#define DDRSS_PHY_805_DATA 0x00000000 +#define DDRSS_PHY_806_DATA 0x55555555 +#define DDRSS_PHY_807_DATA 0xAAAAAAAA +#define DDRSS_PHY_808_DATA 0x55555555 +#define DDRSS_PHY_809_DATA 0xAAAAAAAA +#define DDRSS_PHY_810_DATA 0x00005555 +#define DDRSS_PHY_811_DATA 0x01000100 +#define DDRSS_PHY_812_DATA 0x00800180 +#define DDRSS_PHY_813_DATA 0x00000000 +#define DDRSS_PHY_814_DATA 0x00000000 +#define DDRSS_PHY_815_DATA 0x00000000 +#define DDRSS_PHY_816_DATA 0x00000000 +#define DDRSS_PHY_817_DATA 0x00000000 +#define DDRSS_PHY_818_DATA 0x00000000 +#define DDRSS_PHY_819_DATA 0x00000000 +#define DDRSS_PHY_820_DATA 0x00000000 +#define DDRSS_PHY_821_DATA 0x00000000 +#define DDRSS_PHY_822_DATA 0x00000000 +#define DDRSS_PHY_823_DATA 0x00000000 +#define DDRSS_PHY_824_DATA 0x00000000 +#define DDRSS_PHY_825_DATA 0x00000000 +#define DDRSS_PHY_826_DATA 0x00000000 +#define DDRSS_PHY_827_DATA 0x00000000 +#define DDRSS_PHY_828_DATA 0x00000000 +#define DDRSS_PHY_829_DATA 0x00000000 +#define DDRSS_PHY_830_DATA 0x00000000 +#define DDRSS_PHY_831_DATA 0x00000000 +#define DDRSS_PHY_832_DATA 0x00000000 +#define DDRSS_PHY_833_DATA 0x00000000 +#define DDRSS_PHY_834_DATA 0x00000000 +#define DDRSS_PHY_835_DATA 0x00000004 +#define DDRSS_PHY_836_DATA 0x00000000 +#define DDRSS_PHY_837_DATA 0x00000000 +#define DDRSS_PHY_838_DATA 0x00000000 +#define DDRSS_PHY_839_DATA 0x00000000 +#define DDRSS_PHY_840_DATA 0x00000000 +#define DDRSS_PHY_841_DATA 0x00000000 +#define DDRSS_PHY_842_DATA 0x081F07FF +#define DDRSS_PHY_843_DATA 0x10200080 +#define DDRSS_PHY_844_DATA 0x00000008 +#define DDRSS_PHY_845_DATA 0x00000401 +#define DDRSS_PHY_846_DATA 0x00000000 +#define DDRSS_PHY_847_DATA 0x01CC0C01 +#define DDRSS_PHY_848_DATA 0x1003CC0C +#define DDRSS_PHY_849_DATA 0x20000140 +#define DDRSS_PHY_850_DATA 0x07FF0200 +#define DDRSS_PHY_851_DATA 0x0000DD01 +#define DDRSS_PHY_852_DATA 0x00100303 +#define DDRSS_PHY_853_DATA 0x00000000 +#define DDRSS_PHY_854_DATA 0x00000000 +#define DDRSS_PHY_855_DATA 0x00041000 +#define DDRSS_PHY_856_DATA 0x00100010 +#define DDRSS_PHY_857_DATA 0x00100010 +#define DDRSS_PHY_858_DATA 0x00100010 +#define DDRSS_PHY_859_DATA 0x00100010 +#define DDRSS_PHY_860_DATA 0x02040010 +#define DDRSS_PHY_861_DATA 0x00000005 +#define DDRSS_PHY_862_DATA 0x51516042 +#define DDRSS_PHY_863_DATA 0x31C06000 +#define DDRSS_PHY_864_DATA 0x07AB0340 +#define DDRSS_PHY_865_DATA 0x00C0C001 +#define DDRSS_PHY_866_DATA 0x0D000000 +#define DDRSS_PHY_867_DATA 0x000D0C0C +#define DDRSS_PHY_868_DATA 0x42100010 +#define DDRSS_PHY_869_DATA 0x010C073E +#define DDRSS_PHY_870_DATA 0x000F0C32 +#define DDRSS_PHY_871_DATA 0x01000140 +#define DDRSS_PHY_872_DATA 0x011E0120 +#define DDRSS_PHY_873_DATA 0x00000C00 +#define DDRSS_PHY_874_DATA 0x000002DD +#define DDRSS_PHY_875_DATA 0x00030200 +#define DDRSS_PHY_876_DATA 0x02800000 +#define DDRSS_PHY_877_DATA 0x80800000 +#define DDRSS_PHY_878_DATA 0x000D2010 +#define DDRSS_PHY_879_DATA 0x76543210 +#define DDRSS_PHY_880_DATA 0x00000008 +#define DDRSS_PHY_881_DATA 0x045D045D +#define DDRSS_PHY_882_DATA 0x045D045D +#define DDRSS_PHY_883_DATA 0x045D045D +#define DDRSS_PHY_884_DATA 0x045D045D +#define DDRSS_PHY_885_DATA 0x0000045D +#define DDRSS_PHY_886_DATA 0x0000A000 +#define DDRSS_PHY_887_DATA 0x00A000A0 +#define DDRSS_PHY_888_DATA 0x00A000A0 +#define DDRSS_PHY_889_DATA 0x00A000A0 +#define DDRSS_PHY_890_DATA 0x00A000A0 +#define DDRSS_PHY_891_DATA 0x00A000A0 +#define DDRSS_PHY_892_DATA 0x00A000A0 +#define DDRSS_PHY_893_DATA 0x00A000A0 +#define DDRSS_PHY_894_DATA 0x00A000A0 +#define DDRSS_PHY_895_DATA 0x00B200A0 +#define DDRSS_PHY_896_DATA 0x01000000 +#define DDRSS_PHY_897_DATA 0x00000000 +#define DDRSS_PHY_898_DATA 0x00000000 +#define DDRSS_PHY_899_DATA 0x00080200 +#define DDRSS_PHY_900_DATA 0x00000000 +#define DDRSS_PHY_901_DATA 0x20202020 +#define DDRSS_PHY_902_DATA 0x20202020 +#define DDRSS_PHY_903_DATA 0xF0F02020 +#define DDRSS_PHY_904_DATA 0x00000000 +#define DDRSS_PHY_905_DATA 0x00000000 +#define DDRSS_PHY_906_DATA 0x00000000 +#define DDRSS_PHY_907_DATA 0x00000000 +#define DDRSS_PHY_908_DATA 0x00000000 +#define DDRSS_PHY_909_DATA 0x00000000 +#define DDRSS_PHY_910_DATA 0x00000000 +#define DDRSS_PHY_911_DATA 0x00000000 +#define DDRSS_PHY_912_DATA 0x00000000 +#define DDRSS_PHY_913_DATA 0x00000000 +#define DDRSS_PHY_914_DATA 0x00000000 +#define DDRSS_PHY_915_DATA 0x00000000 +#define DDRSS_PHY_916_DATA 0x00000000 +#define DDRSS_PHY_917_DATA 0x00000000 +#define DDRSS_PHY_918_DATA 0x00000000 +#define DDRSS_PHY_919_DATA 0x00000000 +#define DDRSS_PHY_920_DATA 0x00000000 +#define DDRSS_PHY_921_DATA 0x00000000 +#define DDRSS_PHY_922_DATA 0x00000000 +#define DDRSS_PHY_923_DATA 0x00000000 +#define DDRSS_PHY_924_DATA 0x00000000 +#define DDRSS_PHY_925_DATA 0x00000000 +#define DDRSS_PHY_926_DATA 0x00000000 +#define DDRSS_PHY_927_DATA 0x00000000 +#define DDRSS_PHY_928_DATA 0x00000000 +#define DDRSS_PHY_929_DATA 0x00000000 +#define DDRSS_PHY_930_DATA 0x00000000 +#define DDRSS_PHY_931_DATA 0x00000000 +#define DDRSS_PHY_932_DATA 0x00000000 +#define DDRSS_PHY_933_DATA 0x00000000 +#define DDRSS_PHY_934_DATA 0x00000000 +#define DDRSS_PHY_935_DATA 0x00000000 +#define DDRSS_PHY_936_DATA 0x00000000 +#define DDRSS_PHY_937_DATA 0x00000000 +#define DDRSS_PHY_938_DATA 0x00000000 +#define DDRSS_PHY_939_DATA 0x00000000 +#define DDRSS_PHY_940_DATA 0x00000000 +#define DDRSS_PHY_941_DATA 0x00000000 +#define DDRSS_PHY_942_DATA 0x00000000 +#define DDRSS_PHY_943_DATA 0x00000000 +#define DDRSS_PHY_944_DATA 0x00000000 +#define DDRSS_PHY_945_DATA 0x00000000 +#define DDRSS_PHY_946_DATA 0x00000000 +#define DDRSS_PHY_947_DATA 0x00000000 +#define DDRSS_PHY_948_DATA 0x00000000 +#define DDRSS_PHY_949_DATA 0x00000000 +#define DDRSS_PHY_950_DATA 0x00000000 +#define DDRSS_PHY_951_DATA 0x00000000 +#define DDRSS_PHY_952_DATA 0x00000000 +#define DDRSS_PHY_953_DATA 0x00000000 +#define DDRSS_PHY_954_DATA 0x00000000 +#define DDRSS_PHY_955_DATA 0x00000000 +#define DDRSS_PHY_956_DATA 0x00000000 +#define DDRSS_PHY_957_DATA 0x00000000 +#define DDRSS_PHY_958_DATA 0x00000000 +#define DDRSS_PHY_959_DATA 0x00000000 +#define DDRSS_PHY_960_DATA 0x00000000 +#define DDRSS_PHY_961_DATA 0x00000000 +#define DDRSS_PHY_962_DATA 0x00000000 +#define DDRSS_PHY_963_DATA 0x00000000 +#define DDRSS_PHY_964_DATA 0x00000000 +#define DDRSS_PHY_965_DATA 0x00000000 +#define DDRSS_PHY_966_DATA 0x00000000 +#define DDRSS_PHY_967_DATA 0x00000000 +#define DDRSS_PHY_968_DATA 0x00000000 +#define DDRSS_PHY_969_DATA 0x00000000 +#define DDRSS_PHY_970_DATA 0x00000000 +#define DDRSS_PHY_971_DATA 0x00000000 +#define DDRSS_PHY_972_DATA 0x00000000 +#define DDRSS_PHY_973_DATA 0x00000000 +#define DDRSS_PHY_974_DATA 0x00000000 +#define DDRSS_PHY_975_DATA 0x00000000 +#define DDRSS_PHY_976_DATA 0x00000000 +#define DDRSS_PHY_977_DATA 0x00000000 +#define DDRSS_PHY_978_DATA 0x00000000 +#define DDRSS_PHY_979_DATA 0x00000000 +#define DDRSS_PHY_980_DATA 0x00000000 +#define DDRSS_PHY_981_DATA 0x00000000 +#define DDRSS_PHY_982_DATA 0x00000000 +#define DDRSS_PHY_983_DATA 0x00000000 +#define DDRSS_PHY_984_DATA 0x00000000 +#define DDRSS_PHY_985_DATA 0x00000000 +#define DDRSS_PHY_986_DATA 0x00000000 +#define DDRSS_PHY_987_DATA 0x00000000 +#define DDRSS_PHY_988_DATA 0x00000000 +#define DDRSS_PHY_989_DATA 0x00000000 +#define DDRSS_PHY_990_DATA 0x00000000 +#define DDRSS_PHY_991_DATA 0x00000000 +#define DDRSS_PHY_992_DATA 0x00000000 +#define DDRSS_PHY_993_DATA 0x00000000 +#define DDRSS_PHY_994_DATA 0x00000000 +#define DDRSS_PHY_995_DATA 0x00000000 +#define DDRSS_PHY_996_DATA 0x00000000 +#define DDRSS_PHY_997_DATA 0x00000000 +#define DDRSS_PHY_998_DATA 0x00000000 +#define DDRSS_PHY_999_DATA 0x00000000 +#define DDRSS_PHY_1000_DATA 0x00000000 +#define DDRSS_PHY_1001_DATA 0x00000000 +#define DDRSS_PHY_1002_DATA 0x00000000 +#define DDRSS_PHY_1003_DATA 0x00000000 +#define DDRSS_PHY_1004_DATA 0x00000000 +#define DDRSS_PHY_1005_DATA 0x00000000 +#define DDRSS_PHY_1006_DATA 0x00000000 +#define DDRSS_PHY_1007_DATA 0x00000000 +#define DDRSS_PHY_1008_DATA 0x00000000 +#define DDRSS_PHY_1009_DATA 0x00000000 +#define DDRSS_PHY_1010_DATA 0x00000000 +#define DDRSS_PHY_1011_DATA 0x00000000 +#define DDRSS_PHY_1012_DATA 0x00000000 +#define DDRSS_PHY_1013_DATA 0x00000000 +#define DDRSS_PHY_1014_DATA 0x00000000 +#define DDRSS_PHY_1015_DATA 0x00000000 +#define DDRSS_PHY_1016_DATA 0x00000000 +#define DDRSS_PHY_1017_DATA 0x00000000 +#define DDRSS_PHY_1018_DATA 0x00000000 +#define DDRSS_PHY_1019_DATA 0x00000000 +#define DDRSS_PHY_1020_DATA 0x00000000 +#define DDRSS_PHY_1021_DATA 0x00000000 +#define DDRSS_PHY_1022_DATA 0x00000000 +#define DDRSS_PHY_1023_DATA 0x00000000 +#define DDRSS_PHY_1024_DATA 0x00000000 +#define DDRSS_PHY_1025_DATA 0x00000000 +#define DDRSS_PHY_1026_DATA 0x00000000 +#define DDRSS_PHY_1027_DATA 0x00000000 +#define DDRSS_PHY_1028_DATA 0x00000000 +#define DDRSS_PHY_1029_DATA 0x00000100 +#define DDRSS_PHY_1030_DATA 0x00000200 +#define DDRSS_PHY_1031_DATA 0x00000000 +#define DDRSS_PHY_1032_DATA 0x00000000 +#define DDRSS_PHY_1033_DATA 0x00000000 +#define DDRSS_PHY_1034_DATA 0x00000000 +#define DDRSS_PHY_1035_DATA 0x00400000 +#define DDRSS_PHY_1036_DATA 0x00000080 +#define DDRSS_PHY_1037_DATA 0x00DCBA98 +#define DDRSS_PHY_1038_DATA 0x03000000 +#define DDRSS_PHY_1039_DATA 0x00200000 +#define DDRSS_PHY_1040_DATA 0x00000000 +#define DDRSS_PHY_1041_DATA 0x00000000 +#define DDRSS_PHY_1042_DATA 0x00000000 +#define DDRSS_PHY_1043_DATA 0x00000000 +#define DDRSS_PHY_1044_DATA 0x00000000 +#define DDRSS_PHY_1045_DATA 0x0000002A +#define DDRSS_PHY_1046_DATA 0x00000015 +#define DDRSS_PHY_1047_DATA 0x00000015 +#define DDRSS_PHY_1048_DATA 0x0000002A +#define DDRSS_PHY_1049_DATA 0x00000033 +#define DDRSS_PHY_1050_DATA 0x0000000C +#define DDRSS_PHY_1051_DATA 0x0000000C +#define DDRSS_PHY_1052_DATA 0x00000033 +#define DDRSS_PHY_1053_DATA 0x0A418820 +#define DDRSS_PHY_1054_DATA 0x003F0000 +#define DDRSS_PHY_1055_DATA 0x000F013F +#define DDRSS_PHY_1056_DATA 0x20202003 +#define DDRSS_PHY_1057_DATA 0x00202020 +#define DDRSS_PHY_1058_DATA 0x20008008 +#define DDRSS_PHY_1059_DATA 0x00000810 +#define DDRSS_PHY_1060_DATA 0x00000F00 +#define DDRSS_PHY_1061_DATA 0x000405CC +#define DDRSS_PHY_1062_DATA 0x03000004 +#define DDRSS_PHY_1063_DATA 0x00030000 +#define DDRSS_PHY_1064_DATA 0x00000300 +#define DDRSS_PHY_1065_DATA 0x00000300 +#define DDRSS_PHY_1066_DATA 0x00000300 +#define DDRSS_PHY_1067_DATA 0x00000300 +#define DDRSS_PHY_1068_DATA 0x42080010 +#define DDRSS_PHY_1069_DATA 0x0000803E +#define DDRSS_PHY_1070_DATA 0x00000001 +#define DDRSS_PHY_1071_DATA 0x01000002 +#define DDRSS_PHY_1072_DATA 0x00008000 +#define DDRSS_PHY_1073_DATA 0x00000000 +#define DDRSS_PHY_1074_DATA 0x00000000 +#define DDRSS_PHY_1075_DATA 0x00000000 +#define DDRSS_PHY_1076_DATA 0x00000000 +#define DDRSS_PHY_1077_DATA 0x00000000 +#define DDRSS_PHY_1078_DATA 0x00000000 +#define DDRSS_PHY_1079_DATA 0x00000000 +#define DDRSS_PHY_1080_DATA 0x00000000 +#define DDRSS_PHY_1081_DATA 0x00000000 +#define DDRSS_PHY_1082_DATA 0x00000000 +#define DDRSS_PHY_1083_DATA 0x00000000 +#define DDRSS_PHY_1084_DATA 0x00000000 +#define DDRSS_PHY_1085_DATA 0x00000000 +#define DDRSS_PHY_1086_DATA 0x00000000 +#define DDRSS_PHY_1087_DATA 0x00000000 +#define DDRSS_PHY_1088_DATA 0x00000000 +#define DDRSS_PHY_1089_DATA 0x00000000 +#define DDRSS_PHY_1090_DATA 0x00000000 +#define DDRSS_PHY_1091_DATA 0x00000000 +#define DDRSS_PHY_1092_DATA 0x00000000 +#define DDRSS_PHY_1093_DATA 0x00000000 +#define DDRSS_PHY_1094_DATA 0x00000000 +#define DDRSS_PHY_1095_DATA 0x00000000 +#define DDRSS_PHY_1096_DATA 0x00000000 +#define DDRSS_PHY_1097_DATA 0x00000000 +#define DDRSS_PHY_1098_DATA 0x00000000 +#define DDRSS_PHY_1099_DATA 0x00000000 +#define DDRSS_PHY_1100_DATA 0x00000000 +#define DDRSS_PHY_1101_DATA 0x00000000 +#define DDRSS_PHY_1102_DATA 0x00000000 +#define DDRSS_PHY_1103_DATA 0x00000000 +#define DDRSS_PHY_1104_DATA 0x00000000 +#define DDRSS_PHY_1105_DATA 0x00000000 +#define DDRSS_PHY_1106_DATA 0x00000000 +#define DDRSS_PHY_1107_DATA 0x00000000 +#define DDRSS_PHY_1108_DATA 0x00000000 +#define DDRSS_PHY_1109_DATA 0x00000000 +#define DDRSS_PHY_1110_DATA 0x00000000 +#define DDRSS_PHY_1111_DATA 0x00000000 +#define DDRSS_PHY_1112_DATA 0x00000000 +#define DDRSS_PHY_1113_DATA 0x00000000 +#define DDRSS_PHY_1114_DATA 0x00000000 +#define DDRSS_PHY_1115_DATA 0x00000000 +#define DDRSS_PHY_1116_DATA 0x00000000 +#define DDRSS_PHY_1117_DATA 0x00000000 +#define DDRSS_PHY_1118_DATA 0x00000000 +#define DDRSS_PHY_1119_DATA 0x00000000 +#define DDRSS_PHY_1120_DATA 0x00000000 +#define DDRSS_PHY_1121_DATA 0x00000000 +#define DDRSS_PHY_1122_DATA 0x00000000 +#define DDRSS_PHY_1123_DATA 0x00000000 +#define DDRSS_PHY_1124_DATA 0x00000000 +#define DDRSS_PHY_1125_DATA 0x00000000 +#define DDRSS_PHY_1126_DATA 0x00000000 +#define DDRSS_PHY_1127_DATA 0x00000000 +#define DDRSS_PHY_1128_DATA 0x00000000 +#define DDRSS_PHY_1129_DATA 0x00000000 +#define DDRSS_PHY_1130_DATA 0x00000000 +#define DDRSS_PHY_1131_DATA 0x00000000 +#define DDRSS_PHY_1132_DATA 0x00000000 +#define DDRSS_PHY_1133_DATA 0x00000000 +#define DDRSS_PHY_1134_DATA 0x00000000 +#define DDRSS_PHY_1135_DATA 0x00000000 +#define DDRSS_PHY_1136_DATA 0x00000000 +#define DDRSS_PHY_1137_DATA 0x00000000 +#define DDRSS_PHY_1138_DATA 0x00000000 +#define DDRSS_PHY_1139_DATA 0x00000000 +#define DDRSS_PHY_1140_DATA 0x00000000 +#define DDRSS_PHY_1141_DATA 0x00000000 +#define DDRSS_PHY_1142_DATA 0x00000000 +#define DDRSS_PHY_1143_DATA 0x00000000 +#define DDRSS_PHY_1144_DATA 0x00000000 +#define DDRSS_PHY_1145_DATA 0x00000000 +#define DDRSS_PHY_1146_DATA 0x00000000 +#define DDRSS_PHY_1147_DATA 0x00000000 +#define DDRSS_PHY_1148_DATA 0x00000000 +#define DDRSS_PHY_1149_DATA 0x00000000 +#define DDRSS_PHY_1150_DATA 0x00000000 +#define DDRSS_PHY_1151_DATA 0x00000000 +#define DDRSS_PHY_1152_DATA 0x00000000 +#define DDRSS_PHY_1153_DATA 0x00000000 +#define DDRSS_PHY_1154_DATA 0x00000000 +#define DDRSS_PHY_1155_DATA 0x00000000 +#define DDRSS_PHY_1156_DATA 0x00000000 +#define DDRSS_PHY_1157_DATA 0x00000000 +#define DDRSS_PHY_1158_DATA 0x00000000 +#define DDRSS_PHY_1159_DATA 0x00000000 +#define DDRSS_PHY_1160_DATA 0x00000000 +#define DDRSS_PHY_1161_DATA 0x00000000 +#define DDRSS_PHY_1162_DATA 0x00000000 +#define DDRSS_PHY_1163_DATA 0x00000000 +#define DDRSS_PHY_1164_DATA 0x00000000 +#define DDRSS_PHY_1165_DATA 0x00000000 +#define DDRSS_PHY_1166_DATA 0x00000000 +#define DDRSS_PHY_1167_DATA 0x00000000 +#define DDRSS_PHY_1168_DATA 0x00000000 +#define DDRSS_PHY_1169_DATA 0x00000000 +#define DDRSS_PHY_1170_DATA 0x00000000 +#define DDRSS_PHY_1171_DATA 0x00000000 +#define DDRSS_PHY_1172_DATA 0x00000000 +#define DDRSS_PHY_1173_DATA 0x00000000 +#define DDRSS_PHY_1174_DATA 0x00000000 +#define DDRSS_PHY_1175_DATA 0x00000000 +#define DDRSS_PHY_1176_DATA 0x00000000 +#define DDRSS_PHY_1177_DATA 0x00000000 +#define DDRSS_PHY_1178_DATA 0x00000000 +#define DDRSS_PHY_1179_DATA 0x00000000 +#define DDRSS_PHY_1180_DATA 0x00000000 +#define DDRSS_PHY_1181_DATA 0x00000000 +#define DDRSS_PHY_1182_DATA 0x00000000 +#define DDRSS_PHY_1183_DATA 0x00000000 +#define DDRSS_PHY_1184_DATA 0x00000000 +#define DDRSS_PHY_1185_DATA 0x00000000 +#define DDRSS_PHY_1186_DATA 0x00000000 +#define DDRSS_PHY_1187_DATA 0x00000000 +#define DDRSS_PHY_1188_DATA 0x00000000 +#define DDRSS_PHY_1189_DATA 0x00000000 +#define DDRSS_PHY_1190_DATA 0x00000000 +#define DDRSS_PHY_1191_DATA 0x00000000 +#define DDRSS_PHY_1192_DATA 0x00000000 +#define DDRSS_PHY_1193_DATA 0x00000000 +#define DDRSS_PHY_1194_DATA 0x00000000 +#define DDRSS_PHY_1195_DATA 0x00000000 +#define DDRSS_PHY_1196_DATA 0x00000000 +#define DDRSS_PHY_1197_DATA 0x00000000 +#define DDRSS_PHY_1198_DATA 0x00000000 +#define DDRSS_PHY_1199_DATA 0x00000000 +#define DDRSS_PHY_1200_DATA 0x00000000 +#define DDRSS_PHY_1201_DATA 0x00000000 +#define DDRSS_PHY_1202_DATA 0x00000000 +#define DDRSS_PHY_1203_DATA 0x00000000 +#define DDRSS_PHY_1204_DATA 0x00000000 +#define DDRSS_PHY_1205_DATA 0x00000000 +#define DDRSS_PHY_1206_DATA 0x00000000 +#define DDRSS_PHY_1207_DATA 0x00000000 +#define DDRSS_PHY_1208_DATA 0x00000000 +#define DDRSS_PHY_1209_DATA 0x00000000 +#define DDRSS_PHY_1210_DATA 0x00000000 +#define DDRSS_PHY_1211_DATA 0x00000000 +#define DDRSS_PHY_1212_DATA 0x00000000 +#define DDRSS_PHY_1213_DATA 0x00000000 +#define DDRSS_PHY_1214_DATA 0x00000000 +#define DDRSS_PHY_1215_DATA 0x00000000 +#define DDRSS_PHY_1216_DATA 0x00000000 +#define DDRSS_PHY_1217_DATA 0x00000000 +#define DDRSS_PHY_1218_DATA 0x00000000 +#define DDRSS_PHY_1219_DATA 0x00000000 +#define DDRSS_PHY_1220_DATA 0x00000000 +#define DDRSS_PHY_1221_DATA 0x00000000 +#define DDRSS_PHY_1222_DATA 0x00000000 +#define DDRSS_PHY_1223_DATA 0x00000000 +#define DDRSS_PHY_1224_DATA 0x00000000 +#define DDRSS_PHY_1225_DATA 0x00000000 +#define DDRSS_PHY_1226_DATA 0x00000000 +#define DDRSS_PHY_1227_DATA 0x00000000 +#define DDRSS_PHY_1228_DATA 0x00000000 +#define DDRSS_PHY_1229_DATA 0x00000000 +#define DDRSS_PHY_1230_DATA 0x00000000 +#define DDRSS_PHY_1231_DATA 0x00000000 +#define DDRSS_PHY_1232_DATA 0x00000000 +#define DDRSS_PHY_1233_DATA 0x00000000 +#define DDRSS_PHY_1234_DATA 0x00000000 +#define DDRSS_PHY_1235_DATA 0x00000000 +#define DDRSS_PHY_1236_DATA 0x00000000 +#define DDRSS_PHY_1237_DATA 0x00000000 +#define DDRSS_PHY_1238_DATA 0x00000000 +#define DDRSS_PHY_1239_DATA 0x00000000 +#define DDRSS_PHY_1240_DATA 0x00000000 +#define DDRSS_PHY_1241_DATA 0x00000000 +#define DDRSS_PHY_1242_DATA 0x00000000 +#define DDRSS_PHY_1243_DATA 0x00000000 +#define DDRSS_PHY_1244_DATA 0x00000000 +#define DDRSS_PHY_1245_DATA 0x00000000 +#define DDRSS_PHY_1246_DATA 0x00000000 +#define DDRSS_PHY_1247_DATA 0x00000000 +#define DDRSS_PHY_1248_DATA 0x00000000 +#define DDRSS_PHY_1249_DATA 0x00000000 +#define DDRSS_PHY_1250_DATA 0x00000000 +#define DDRSS_PHY_1251_DATA 0x00000000 +#define DDRSS_PHY_1252_DATA 0x00000000 +#define DDRSS_PHY_1253_DATA 0x00000000 +#define DDRSS_PHY_1254_DATA 0x00000000 +#define DDRSS_PHY_1255_DATA 0x00000000 +#define DDRSS_PHY_1256_DATA 0x00000000 +#define DDRSS_PHY_1257_DATA 0x00000000 +#define DDRSS_PHY_1258_DATA 0x00000000 +#define DDRSS_PHY_1259_DATA 0x00000000 +#define DDRSS_PHY_1260_DATA 0x00000000 +#define DDRSS_PHY_1261_DATA 0x00000000 +#define DDRSS_PHY_1262_DATA 0x00000000 +#define DDRSS_PHY_1263_DATA 0x00000000 +#define DDRSS_PHY_1264_DATA 0x00000000 +#define DDRSS_PHY_1265_DATA 0x00000000 +#define DDRSS_PHY_1266_DATA 0x00000000 +#define DDRSS_PHY_1267_DATA 0x00000000 +#define DDRSS_PHY_1268_DATA 0x00000000 +#define DDRSS_PHY_1269_DATA 0x00000000 +#define DDRSS_PHY_1270_DATA 0x00000000 +#define DDRSS_PHY_1271_DATA 0x00000000 +#define DDRSS_PHY_1272_DATA 0x00000000 +#define DDRSS_PHY_1273_DATA 0x00000000 +#define DDRSS_PHY_1274_DATA 0x00000000 +#define DDRSS_PHY_1275_DATA 0x00000000 +#define DDRSS_PHY_1276_DATA 0x00000000 +#define DDRSS_PHY_1277_DATA 0x00000000 +#define DDRSS_PHY_1278_DATA 0x00000000 +#define DDRSS_PHY_1279_DATA 0x00000000 +#define DDRSS_PHY_1280_DATA 0x00000000 +#define DDRSS_PHY_1281_DATA 0x00000000 +#define DDRSS_PHY_1282_DATA 0x00000000 +#define DDRSS_PHY_1283_DATA 0x00000000 +#define DDRSS_PHY_1284_DATA 0x00000000 +#define DDRSS_PHY_1285_DATA 0x00000100 +#define DDRSS_PHY_1286_DATA 0x00000200 +#define DDRSS_PHY_1287_DATA 0x00000000 +#define DDRSS_PHY_1288_DATA 0x00000000 +#define DDRSS_PHY_1289_DATA 0x00000000 +#define DDRSS_PHY_1290_DATA 0x00000000 +#define DDRSS_PHY_1291_DATA 0x00400000 +#define DDRSS_PHY_1292_DATA 0x00000080 +#define DDRSS_PHY_1293_DATA 0x00DCBA98 +#define DDRSS_PHY_1294_DATA 0x03000000 +#define DDRSS_PHY_1295_DATA 0x00200000 +#define DDRSS_PHY_1296_DATA 0x00000000 +#define DDRSS_PHY_1297_DATA 0x00000000 +#define DDRSS_PHY_1298_DATA 0x00000000 +#define DDRSS_PHY_1299_DATA 0x00000000 +#define DDRSS_PHY_1300_DATA 0x00000000 +#define DDRSS_PHY_1301_DATA 0x0000002A +#define DDRSS_PHY_1302_DATA 0x00000015 +#define DDRSS_PHY_1303_DATA 0x00000015 +#define DDRSS_PHY_1304_DATA 0x0000002A +#define DDRSS_PHY_1305_DATA 0x00000033 +#define DDRSS_PHY_1306_DATA 0x0000000C +#define DDRSS_PHY_1307_DATA 0x0000000C +#define DDRSS_PHY_1308_DATA 0x00000033 +#define DDRSS_PHY_1309_DATA 0x0A418820 +#define DDRSS_PHY_1310_DATA 0x00000000 +#define DDRSS_PHY_1311_DATA 0x000F0000 +#define DDRSS_PHY_1312_DATA 0x20202003 +#define DDRSS_PHY_1313_DATA 0x00202020 +#define DDRSS_PHY_1314_DATA 0x20008008 +#define DDRSS_PHY_1315_DATA 0x00000810 +#define DDRSS_PHY_1316_DATA 0x00000F00 +#define DDRSS_PHY_1317_DATA 0x000405CC +#define DDRSS_PHY_1318_DATA 0x03000004 +#define DDRSS_PHY_1319_DATA 0x00030000 +#define DDRSS_PHY_1320_DATA 0x00000300 +#define DDRSS_PHY_1321_DATA 0x00000300 +#define DDRSS_PHY_1322_DATA 0x00000300 +#define DDRSS_PHY_1323_DATA 0x00000300 +#define DDRSS_PHY_1324_DATA 0x42080010 +#define DDRSS_PHY_1325_DATA 0x0000803E +#define DDRSS_PHY_1326_DATA 0x00000001 +#define DDRSS_PHY_1327_DATA 0x01000002 +#define DDRSS_PHY_1328_DATA 0x00008000 +#define DDRSS_PHY_1329_DATA 0x00000000 +#define DDRSS_PHY_1330_DATA 0x00000000 +#define DDRSS_PHY_1331_DATA 0x00000000 +#define DDRSS_PHY_1332_DATA 0x00000000 +#define DDRSS_PHY_1333_DATA 0x00000000 +#define DDRSS_PHY_1334_DATA 0x00000000 +#define DDRSS_PHY_1335_DATA 0x00000000 +#define DDRSS_PHY_1336_DATA 0x00000000 +#define DDRSS_PHY_1337_DATA 0x00000000 +#define DDRSS_PHY_1338_DATA 0x00000000 +#define DDRSS_PHY_1339_DATA 0x00000000 +#define DDRSS_PHY_1340_DATA 0x00000000 +#define DDRSS_PHY_1341_DATA 0x00000000 +#define DDRSS_PHY_1342_DATA 0x00000000 +#define DDRSS_PHY_1343_DATA 0x00000000 +#define DDRSS_PHY_1344_DATA 0x00000000 +#define DDRSS_PHY_1345_DATA 0x00000000 +#define DDRSS_PHY_1346_DATA 0x00000000 +#define DDRSS_PHY_1347_DATA 0x00000000 +#define DDRSS_PHY_1348_DATA 0x00000000 +#define DDRSS_PHY_1349_DATA 0x00000000 +#define DDRSS_PHY_1350_DATA 0x00000000 +#define DDRSS_PHY_1351_DATA 0x00000000 +#define DDRSS_PHY_1352_DATA 0x00000000 +#define DDRSS_PHY_1353_DATA 0x00000000 +#define DDRSS_PHY_1354_DATA 0x00000000 +#define DDRSS_PHY_1355_DATA 0x00000000 +#define DDRSS_PHY_1356_DATA 0x00000000 +#define DDRSS_PHY_1357_DATA 0x00000000 +#define DDRSS_PHY_1358_DATA 0x00000000 +#define DDRSS_PHY_1359_DATA 0x00000000 +#define DDRSS_PHY_1360_DATA 0x00000000 +#define DDRSS_PHY_1361_DATA 0x00000000 +#define DDRSS_PHY_1362_DATA 0x00000000 +#define DDRSS_PHY_1363_DATA 0x00000000 +#define DDRSS_PHY_1364_DATA 0x00000000 +#define DDRSS_PHY_1365_DATA 0x00000000 +#define DDRSS_PHY_1366_DATA 0x00000000 +#define DDRSS_PHY_1367_DATA 0x00000000 +#define DDRSS_PHY_1368_DATA 0x00000000 +#define DDRSS_PHY_1369_DATA 0x00000000 +#define DDRSS_PHY_1370_DATA 0x00000000 +#define DDRSS_PHY_1371_DATA 0x00000000 +#define DDRSS_PHY_1372_DATA 0x00000000 +#define DDRSS_PHY_1373_DATA 0x00000000 +#define DDRSS_PHY_1374_DATA 0x00000000 +#define DDRSS_PHY_1375_DATA 0x00000000 +#define DDRSS_PHY_1376_DATA 0x00000000 +#define DDRSS_PHY_1377_DATA 0x00000000 +#define DDRSS_PHY_1378_DATA 0x00000000 +#define DDRSS_PHY_1379_DATA 0x00000000 +#define DDRSS_PHY_1380_DATA 0x00000000 +#define DDRSS_PHY_1381_DATA 0x00000000 +#define DDRSS_PHY_1382_DATA 0x00000000 +#define DDRSS_PHY_1383_DATA 0x00000000 +#define DDRSS_PHY_1384_DATA 0x00000000 +#define DDRSS_PHY_1385_DATA 0x00000000 +#define DDRSS_PHY_1386_DATA 0x00000000 +#define DDRSS_PHY_1387_DATA 0x00000000 +#define DDRSS_PHY_1388_DATA 0x00000000 +#define DDRSS_PHY_1389_DATA 0x00000000 +#define DDRSS_PHY_1390_DATA 0x00000000 +#define DDRSS_PHY_1391_DATA 0x00000000 +#define DDRSS_PHY_1392_DATA 0x00000000 +#define DDRSS_PHY_1393_DATA 0x00000000 +#define DDRSS_PHY_1394_DATA 0x00000000 +#define DDRSS_PHY_1395_DATA 0x00000000 +#define DDRSS_PHY_1396_DATA 0x00000000 +#define DDRSS_PHY_1397_DATA 0x00000000 +#define DDRSS_PHY_1398_DATA 0x00000000 +#define DDRSS_PHY_1399_DATA 0x00000000 +#define DDRSS_PHY_1400_DATA 0x00000000 +#define DDRSS_PHY_1401_DATA 0x00000000 +#define DDRSS_PHY_1402_DATA 0x00000000 +#define DDRSS_PHY_1403_DATA 0x00000000 +#define DDRSS_PHY_1404_DATA 0x00000000 +#define DDRSS_PHY_1405_DATA 0x00000000 +#define DDRSS_PHY_1406_DATA 0x00000000 +#define DDRSS_PHY_1407_DATA 0x00000000 +#define DDRSS_PHY_1408_DATA 0x00000000 +#define DDRSS_PHY_1409_DATA 0x00000000 +#define DDRSS_PHY_1410_DATA 0x00000000 +#define DDRSS_PHY_1411_DATA 0x00000000 +#define DDRSS_PHY_1412_DATA 0x00000000 +#define DDRSS_PHY_1413_DATA 0x00000000 +#define DDRSS_PHY_1414_DATA 0x00000000 +#define DDRSS_PHY_1415_DATA 0x00000000 +#define DDRSS_PHY_1416_DATA 0x00000000 +#define DDRSS_PHY_1417_DATA 0x00000000 +#define DDRSS_PHY_1418_DATA 0x00000000 +#define DDRSS_PHY_1419_DATA 0x00000000 +#define DDRSS_PHY_1420_DATA 0x00000000 +#define DDRSS_PHY_1421_DATA 0x00000000 +#define DDRSS_PHY_1422_DATA 0x00000000 +#define DDRSS_PHY_1423_DATA 0x00000000 +#define DDRSS_PHY_1424_DATA 0x00000000 +#define DDRSS_PHY_1425_DATA 0x00000000 +#define DDRSS_PHY_1426_DATA 0x00000000 +#define DDRSS_PHY_1427_DATA 0x00000000 +#define DDRSS_PHY_1428_DATA 0x00000000 +#define DDRSS_PHY_1429_DATA 0x00000000 +#define DDRSS_PHY_1430_DATA 0x00000000 +#define DDRSS_PHY_1431_DATA 0x00000000 +#define DDRSS_PHY_1432_DATA 0x00000000 +#define DDRSS_PHY_1433_DATA 0x00000000 +#define DDRSS_PHY_1434_DATA 0x00000000 +#define DDRSS_PHY_1435_DATA 0x00000000 +#define DDRSS_PHY_1436_DATA 0x00000000 +#define DDRSS_PHY_1437_DATA 0x00000000 +#define DDRSS_PHY_1438_DATA 0x00000000 +#define DDRSS_PHY_1439_DATA 0x00000000 +#define DDRSS_PHY_1440_DATA 0x00000000 +#define DDRSS_PHY_1441_DATA 0x00000000 +#define DDRSS_PHY_1442_DATA 0x00000000 +#define DDRSS_PHY_1443_DATA 0x00000000 +#define DDRSS_PHY_1444_DATA 0x00000000 +#define DDRSS_PHY_1445_DATA 0x00000000 +#define DDRSS_PHY_1446_DATA 0x00000000 +#define DDRSS_PHY_1447_DATA 0x00000000 +#define DDRSS_PHY_1448_DATA 0x00000000 +#define DDRSS_PHY_1449_DATA 0x00000000 +#define DDRSS_PHY_1450_DATA 0x00000000 +#define DDRSS_PHY_1451_DATA 0x00000000 +#define DDRSS_PHY_1452_DATA 0x00000000 +#define DDRSS_PHY_1453_DATA 0x00000000 +#define DDRSS_PHY_1454_DATA 0x00000000 +#define DDRSS_PHY_1455_DATA 0x00000000 +#define DDRSS_PHY_1456_DATA 0x00000000 +#define DDRSS_PHY_1457_DATA 0x00000000 +#define DDRSS_PHY_1458_DATA 0x00000000 +#define DDRSS_PHY_1459_DATA 0x00000000 +#define DDRSS_PHY_1460_DATA 0x00000000 +#define DDRSS_PHY_1461_DATA 0x00000000 +#define DDRSS_PHY_1462_DATA 0x00000000 +#define DDRSS_PHY_1463_DATA 0x00000000 +#define DDRSS_PHY_1464_DATA 0x00000000 +#define DDRSS_PHY_1465_DATA 0x00000000 +#define DDRSS_PHY_1466_DATA 0x00000000 +#define DDRSS_PHY_1467_DATA 0x00000000 +#define DDRSS_PHY_1468_DATA 0x00000000 +#define DDRSS_PHY_1469_DATA 0x00000000 +#define DDRSS_PHY_1470_DATA 0x00000000 +#define DDRSS_PHY_1471_DATA 0x00000000 +#define DDRSS_PHY_1472_DATA 0x00000000 +#define DDRSS_PHY_1473_DATA 0x00000000 +#define DDRSS_PHY_1474_DATA 0x00000000 +#define DDRSS_PHY_1475_DATA 0x00000000 +#define DDRSS_PHY_1476_DATA 0x00000000 +#define DDRSS_PHY_1477_DATA 0x00000000 +#define DDRSS_PHY_1478_DATA 0x00000000 +#define DDRSS_PHY_1479_DATA 0x00000000 +#define DDRSS_PHY_1480_DATA 0x00000000 +#define DDRSS_PHY_1481_DATA 0x00000000 +#define DDRSS_PHY_1482_DATA 0x00000000 +#define DDRSS_PHY_1483_DATA 0x00000000 +#define DDRSS_PHY_1484_DATA 0x00000000 +#define DDRSS_PHY_1485_DATA 0x00000000 +#define DDRSS_PHY_1486_DATA 0x00000000 +#define DDRSS_PHY_1487_DATA 0x00000000 +#define DDRSS_PHY_1488_DATA 0x00000000 +#define DDRSS_PHY_1489_DATA 0x00000000 +#define DDRSS_PHY_1490_DATA 0x00000000 +#define DDRSS_PHY_1491_DATA 0x00000000 +#define DDRSS_PHY_1492_DATA 0x00000000 +#define DDRSS_PHY_1493_DATA 0x00000000 +#define DDRSS_PHY_1494_DATA 0x00000000 +#define DDRSS_PHY_1495_DATA 0x00000000 +#define DDRSS_PHY_1496_DATA 0x00000000 +#define DDRSS_PHY_1497_DATA 0x00000000 +#define DDRSS_PHY_1498_DATA 0x00000000 +#define DDRSS_PHY_1499_DATA 0x00000000 +#define DDRSS_PHY_1500_DATA 0x00000000 +#define DDRSS_PHY_1501_DATA 0x00000000 +#define DDRSS_PHY_1502_DATA 0x00000000 +#define DDRSS_PHY_1503_DATA 0x00000000 +#define DDRSS_PHY_1504_DATA 0x00000000 +#define DDRSS_PHY_1505_DATA 0x00000000 +#define DDRSS_PHY_1506_DATA 0x00000000 +#define DDRSS_PHY_1507_DATA 0x00000000 +#define DDRSS_PHY_1508_DATA 0x00000000 +#define DDRSS_PHY_1509_DATA 0x00000000 +#define DDRSS_PHY_1510_DATA 0x00000000 +#define DDRSS_PHY_1511_DATA 0x00000000 +#define DDRSS_PHY_1512_DATA 0x00000000 +#define DDRSS_PHY_1513_DATA 0x00000000 +#define DDRSS_PHY_1514_DATA 0x00000000 +#define DDRSS_PHY_1515_DATA 0x00000000 +#define DDRSS_PHY_1516_DATA 0x00000000 +#define DDRSS_PHY_1517_DATA 0x00000000 +#define DDRSS_PHY_1518_DATA 0x00000000 +#define DDRSS_PHY_1519_DATA 0x00000000 +#define DDRSS_PHY_1520_DATA 0x00000000 +#define DDRSS_PHY_1521_DATA 0x00000000 +#define DDRSS_PHY_1522_DATA 0x00000000 +#define DDRSS_PHY_1523_DATA 0x00000000 +#define DDRSS_PHY_1524_DATA 0x00000000 +#define DDRSS_PHY_1525_DATA 0x00000000 +#define DDRSS_PHY_1526_DATA 0x00000000 +#define DDRSS_PHY_1527_DATA 0x00000000 +#define DDRSS_PHY_1528_DATA 0x00000000 +#define DDRSS_PHY_1529_DATA 0x00000000 +#define DDRSS_PHY_1530_DATA 0x00000000 +#define DDRSS_PHY_1531_DATA 0x00000000 +#define DDRSS_PHY_1532_DATA 0x00000000 +#define DDRSS_PHY_1533_DATA 0x00000000 +#define DDRSS_PHY_1534_DATA 0x00000000 +#define DDRSS_PHY_1535_DATA 0x00000000 +#define DDRSS_PHY_1536_DATA 0x00000000 +#define DDRSS_PHY_1537_DATA 0x00000000 +#define DDRSS_PHY_1538_DATA 0x00000000 +#define DDRSS_PHY_1539_DATA 0x00000000 +#define DDRSS_PHY_1540_DATA 0x00000000 +#define DDRSS_PHY_1541_DATA 0x00000100 +#define DDRSS_PHY_1542_DATA 0x00000200 +#define DDRSS_PHY_1543_DATA 0x00000000 +#define DDRSS_PHY_1544_DATA 0x00000000 +#define DDRSS_PHY_1545_DATA 0x00000000 +#define DDRSS_PHY_1546_DATA 0x00000000 +#define DDRSS_PHY_1547_DATA 0x00400000 +#define DDRSS_PHY_1548_DATA 0x00000080 +#define DDRSS_PHY_1549_DATA 0x00DCBA98 +#define DDRSS_PHY_1550_DATA 0x03000000 +#define DDRSS_PHY_1551_DATA 0x00200000 +#define DDRSS_PHY_1552_DATA 0x00000000 +#define DDRSS_PHY_1553_DATA 0x00000000 +#define DDRSS_PHY_1554_DATA 0x00000000 +#define DDRSS_PHY_1555_DATA 0x00000000 +#define DDRSS_PHY_1556_DATA 0x00000000 +#define DDRSS_PHY_1557_DATA 0x0000002A +#define DDRSS_PHY_1558_DATA 0x00000015 +#define DDRSS_PHY_1559_DATA 0x00000015 +#define DDRSS_PHY_1560_DATA 0x0000002A +#define DDRSS_PHY_1561_DATA 0x00000033 +#define DDRSS_PHY_1562_DATA 0x0000000C +#define DDRSS_PHY_1563_DATA 0x0000000C +#define DDRSS_PHY_1564_DATA 0x00000033 +#define DDRSS_PHY_1565_DATA 0x0A418820 +#define DDRSS_PHY_1566_DATA 0x10000000 +#define DDRSS_PHY_1567_DATA 0x000F0000 +#define DDRSS_PHY_1568_DATA 0x20202003 +#define DDRSS_PHY_1569_DATA 0x00202020 +#define DDRSS_PHY_1570_DATA 0x20008008 +#define DDRSS_PHY_1571_DATA 0x00000810 +#define DDRSS_PHY_1572_DATA 0x00000F00 +#define DDRSS_PHY_1573_DATA 0x000405CC +#define DDRSS_PHY_1574_DATA 0x03000004 +#define DDRSS_PHY_1575_DATA 0x00030000 +#define DDRSS_PHY_1576_DATA 0x00000300 +#define DDRSS_PHY_1577_DATA 0x00000300 +#define DDRSS_PHY_1578_DATA 0x00000300 +#define DDRSS_PHY_1579_DATA 0x00000300 +#define DDRSS_PHY_1580_DATA 0x42080010 +#define DDRSS_PHY_1581_DATA 0x0000803E +#define DDRSS_PHY_1582_DATA 0x00000001 +#define DDRSS_PHY_1583_DATA 0x01000002 +#define DDRSS_PHY_1584_DATA 0x00008000 +#define DDRSS_PHY_1585_DATA 0x00000000 +#define DDRSS_PHY_1586_DATA 0x00000000 +#define DDRSS_PHY_1587_DATA 0x00000000 +#define DDRSS_PHY_1588_DATA 0x00000000 +#define DDRSS_PHY_1589_DATA 0x00000000 +#define DDRSS_PHY_1590_DATA 0x00000000 +#define DDRSS_PHY_1591_DATA 0x00000000 +#define DDRSS_PHY_1592_DATA 0x00000000 +#define DDRSS_PHY_1593_DATA 0x00000000 +#define DDRSS_PHY_1594_DATA 0x00000000 +#define DDRSS_PHY_1595_DATA 0x00000000 +#define DDRSS_PHY_1596_DATA 0x00000000 +#define DDRSS_PHY_1597_DATA 0x00000000 +#define DDRSS_PHY_1598_DATA 0x00000000 +#define DDRSS_PHY_1599_DATA 0x00000000 +#define DDRSS_PHY_1600_DATA 0x00000000 +#define DDRSS_PHY_1601_DATA 0x00000000 +#define DDRSS_PHY_1602_DATA 0x00000000 +#define DDRSS_PHY_1603_DATA 0x00000000 +#define DDRSS_PHY_1604_DATA 0x00000000 +#define DDRSS_PHY_1605_DATA 0x00000000 +#define DDRSS_PHY_1606_DATA 0x00000000 +#define DDRSS_PHY_1607_DATA 0x00000000 +#define DDRSS_PHY_1608_DATA 0x00000000 +#define DDRSS_PHY_1609_DATA 0x00000000 +#define DDRSS_PHY_1610_DATA 0x00000000 +#define DDRSS_PHY_1611_DATA 0x00000000 +#define DDRSS_PHY_1612_DATA 0x00000000 +#define DDRSS_PHY_1613_DATA 0x00000000 +#define DDRSS_PHY_1614_DATA 0x00000000 +#define DDRSS_PHY_1615_DATA 0x00000000 +#define DDRSS_PHY_1616_DATA 0x00000000 +#define DDRSS_PHY_1617_DATA 0x00000000 +#define DDRSS_PHY_1618_DATA 0x00000000 +#define DDRSS_PHY_1619_DATA 0x00000000 +#define DDRSS_PHY_1620_DATA 0x00000000 +#define DDRSS_PHY_1621_DATA 0x00000000 +#define DDRSS_PHY_1622_DATA 0x00000000 +#define DDRSS_PHY_1623_DATA 0x00000000 +#define DDRSS_PHY_1624_DATA 0x00000000 +#define DDRSS_PHY_1625_DATA 0x00000000 +#define DDRSS_PHY_1626_DATA 0x00000000 +#define DDRSS_PHY_1627_DATA 0x00000000 +#define DDRSS_PHY_1628_DATA 0x00000000 +#define DDRSS_PHY_1629_DATA 0x00000000 +#define DDRSS_PHY_1630_DATA 0x00000000 +#define DDRSS_PHY_1631_DATA 0x00000000 +#define DDRSS_PHY_1632_DATA 0x00000000 +#define DDRSS_PHY_1633_DATA 0x00000000 +#define DDRSS_PHY_1634_DATA 0x00000000 +#define DDRSS_PHY_1635_DATA 0x00000000 +#define DDRSS_PHY_1636_DATA 0x00000000 +#define DDRSS_PHY_1637_DATA 0x00000000 +#define DDRSS_PHY_1638_DATA 0x00000000 +#define DDRSS_PHY_1639_DATA 0x00000000 +#define DDRSS_PHY_1640_DATA 0x00000000 +#define DDRSS_PHY_1641_DATA 0x00000000 +#define DDRSS_PHY_1642_DATA 0x00000000 +#define DDRSS_PHY_1643_DATA 0x00000000 +#define DDRSS_PHY_1644_DATA 0x00000000 +#define DDRSS_PHY_1645_DATA 0x00000000 +#define DDRSS_PHY_1646_DATA 0x00000000 +#define DDRSS_PHY_1647_DATA 0x00000000 +#define DDRSS_PHY_1648_DATA 0x00000000 +#define DDRSS_PHY_1649_DATA 0x00000000 +#define DDRSS_PHY_1650_DATA 0x00000000 +#define DDRSS_PHY_1651_DATA 0x00000000 +#define DDRSS_PHY_1652_DATA 0x00000000 +#define DDRSS_PHY_1653_DATA 0x00000000 +#define DDRSS_PHY_1654_DATA 0x00000000 +#define DDRSS_PHY_1655_DATA 0x00000000 +#define DDRSS_PHY_1656_DATA 0x00000000 +#define DDRSS_PHY_1657_DATA 0x00000000 +#define DDRSS_PHY_1658_DATA 0x00000000 +#define DDRSS_PHY_1659_DATA 0x00000000 +#define DDRSS_PHY_1660_DATA 0x00000000 +#define DDRSS_PHY_1661_DATA 0x00000000 +#define DDRSS_PHY_1662_DATA 0x00000000 +#define DDRSS_PHY_1663_DATA 0x00000000 +#define DDRSS_PHY_1664_DATA 0x00000000 +#define DDRSS_PHY_1665_DATA 0x00000000 +#define DDRSS_PHY_1666_DATA 0x00000000 +#define DDRSS_PHY_1667_DATA 0x00000000 +#define DDRSS_PHY_1668_DATA 0x00000000 +#define DDRSS_PHY_1669_DATA 0x00000000 +#define DDRSS_PHY_1670_DATA 0x00000000 +#define DDRSS_PHY_1671_DATA 0x00000000 +#define DDRSS_PHY_1672_DATA 0x00000000 +#define DDRSS_PHY_1673_DATA 0x00000000 +#define DDRSS_PHY_1674_DATA 0x00000000 +#define DDRSS_PHY_1675_DATA 0x00000000 +#define DDRSS_PHY_1676_DATA 0x00000000 +#define DDRSS_PHY_1677_DATA 0x00000000 +#define DDRSS_PHY_1678_DATA 0x00000000 +#define DDRSS_PHY_1679_DATA 0x00000000 +#define DDRSS_PHY_1680_DATA 0x00000000 +#define DDRSS_PHY_1681_DATA 0x00000000 +#define DDRSS_PHY_1682_DATA 0x00000000 +#define DDRSS_PHY_1683_DATA 0x00000000 +#define DDRSS_PHY_1684_DATA 0x00000000 +#define DDRSS_PHY_1685_DATA 0x00000000 +#define DDRSS_PHY_1686_DATA 0x00000000 +#define DDRSS_PHY_1687_DATA 0x00000000 +#define DDRSS_PHY_1688_DATA 0x00000000 +#define DDRSS_PHY_1689_DATA 0x00000000 +#define DDRSS_PHY_1690_DATA 0x00000000 +#define DDRSS_PHY_1691_DATA 0x00000000 +#define DDRSS_PHY_1692_DATA 0x00000000 +#define DDRSS_PHY_1693_DATA 0x00000000 +#define DDRSS_PHY_1694_DATA 0x00000000 +#define DDRSS_PHY_1695_DATA 0x00000000 +#define DDRSS_PHY_1696_DATA 0x00000000 +#define DDRSS_PHY_1697_DATA 0x00000000 +#define DDRSS_PHY_1698_DATA 0x00000000 +#define DDRSS_PHY_1699_DATA 0x00000000 +#define DDRSS_PHY_1700_DATA 0x00000000 +#define DDRSS_PHY_1701_DATA 0x00000000 +#define DDRSS_PHY_1702_DATA 0x00000000 +#define DDRSS_PHY_1703_DATA 0x00000000 +#define DDRSS_PHY_1704_DATA 0x00000000 +#define DDRSS_PHY_1705_DATA 0x00000000 +#define DDRSS_PHY_1706_DATA 0x00000000 +#define DDRSS_PHY_1707_DATA 0x00000000 +#define DDRSS_PHY_1708_DATA 0x00000000 +#define DDRSS_PHY_1709_DATA 0x00000000 +#define DDRSS_PHY_1710_DATA 0x00000000 +#define DDRSS_PHY_1711_DATA 0x00000000 +#define DDRSS_PHY_1712_DATA 0x00000000 +#define DDRSS_PHY_1713_DATA 0x00000000 +#define DDRSS_PHY_1714_DATA 0x00000000 +#define DDRSS_PHY_1715_DATA 0x00000000 +#define DDRSS_PHY_1716_DATA 0x00000000 +#define DDRSS_PHY_1717_DATA 0x00000000 +#define DDRSS_PHY_1718_DATA 0x00000000 +#define DDRSS_PHY_1719_DATA 0x00000000 +#define DDRSS_PHY_1720_DATA 0x00000000 +#define DDRSS_PHY_1721_DATA 0x00000000 +#define DDRSS_PHY_1722_DATA 0x00000000 +#define DDRSS_PHY_1723_DATA 0x00000000 +#define DDRSS_PHY_1724_DATA 0x00000000 +#define DDRSS_PHY_1725_DATA 0x00000000 +#define DDRSS_PHY_1726_DATA 0x00000000 +#define DDRSS_PHY_1727_DATA 0x00000000 +#define DDRSS_PHY_1728_DATA 0x00000000 +#define DDRSS_PHY_1729_DATA 0x00000000 +#define DDRSS_PHY_1730_DATA 0x00000000 +#define DDRSS_PHY_1731_DATA 0x00000000 +#define DDRSS_PHY_1732_DATA 0x00000000 +#define DDRSS_PHY_1733_DATA 0x00000000 +#define DDRSS_PHY_1734_DATA 0x00000000 +#define DDRSS_PHY_1735_DATA 0x00000000 +#define DDRSS_PHY_1736_DATA 0x00000000 +#define DDRSS_PHY_1737_DATA 0x00000000 +#define DDRSS_PHY_1738_DATA 0x00000000 +#define DDRSS_PHY_1739_DATA 0x00000000 +#define DDRSS_PHY_1740_DATA 0x00000000 +#define DDRSS_PHY_1741_DATA 0x00000000 +#define DDRSS_PHY_1742_DATA 0x00000000 +#define DDRSS_PHY_1743_DATA 0x00000000 +#define DDRSS_PHY_1744_DATA 0x00000000 +#define DDRSS_PHY_1745_DATA 0x00000000 +#define DDRSS_PHY_1746_DATA 0x00000000 +#define DDRSS_PHY_1747_DATA 0x00000000 +#define DDRSS_PHY_1748_DATA 0x00000000 +#define DDRSS_PHY_1749_DATA 0x00000000 +#define DDRSS_PHY_1750_DATA 0x00000000 +#define DDRSS_PHY_1751_DATA 0x00000000 +#define DDRSS_PHY_1752_DATA 0x00000000 +#define DDRSS_PHY_1753_DATA 0x00000000 +#define DDRSS_PHY_1754_DATA 0x00000000 +#define DDRSS_PHY_1755_DATA 0x00000000 +#define DDRSS_PHY_1756_DATA 0x00000000 +#define DDRSS_PHY_1757_DATA 0x00000000 +#define DDRSS_PHY_1758_DATA 0x00000000 +#define DDRSS_PHY_1759_DATA 0x00000000 +#define DDRSS_PHY_1760_DATA 0x00000000 +#define DDRSS_PHY_1761_DATA 0x00000000 +#define DDRSS_PHY_1762_DATA 0x00000000 +#define DDRSS_PHY_1763_DATA 0x00000000 +#define DDRSS_PHY_1764_DATA 0x00000000 +#define DDRSS_PHY_1765_DATA 0x00000000 +#define DDRSS_PHY_1766_DATA 0x00000000 +#define DDRSS_PHY_1767_DATA 0x00000000 +#define DDRSS_PHY_1768_DATA 0x00000000 +#define DDRSS_PHY_1769_DATA 0x00000000 +#define DDRSS_PHY_1770_DATA 0x00000000 +#define DDRSS_PHY_1771_DATA 0x00000000 +#define DDRSS_PHY_1772_DATA 0x00000000 +#define DDRSS_PHY_1773_DATA 0x00000000 +#define DDRSS_PHY_1774_DATA 0x00000000 +#define DDRSS_PHY_1775_DATA 0x00000000 +#define DDRSS_PHY_1776_DATA 0x00000000 +#define DDRSS_PHY_1777_DATA 0x00000000 +#define DDRSS_PHY_1778_DATA 0x00000000 +#define DDRSS_PHY_1779_DATA 0x00000000 +#define DDRSS_PHY_1780_DATA 0x00000000 +#define DDRSS_PHY_1781_DATA 0x00000000 +#define DDRSS_PHY_1782_DATA 0x00000000 +#define DDRSS_PHY_1783_DATA 0x00000000 +#define DDRSS_PHY_1784_DATA 0x00000000 +#define DDRSS_PHY_1785_DATA 0x00000000 +#define DDRSS_PHY_1786_DATA 0x00000000 +#define DDRSS_PHY_1787_DATA 0x00000000 +#define DDRSS_PHY_1788_DATA 0x00000000 +#define DDRSS_PHY_1789_DATA 0x00000000 +#define DDRSS_PHY_1790_DATA 0x00000000 +#define DDRSS_PHY_1791_DATA 0x00000000 +#define DDRSS_PHY_1792_DATA 0x00000000 +#define DDRSS_PHY_1793_DATA 0x00010100 +#define DDRSS_PHY_1794_DATA 0x00000000 +#define DDRSS_PHY_1795_DATA 0x00000000 +#define DDRSS_PHY_1796_DATA 0x00000000 +#define DDRSS_PHY_1797_DATA 0x00000000 +#define DDRSS_PHY_1798_DATA 0x00050000 +#define DDRSS_PHY_1799_DATA 0x04000000 +#define DDRSS_PHY_1800_DATA 0x00000055 +#define DDRSS_PHY_1801_DATA 0x00000000 +#define DDRSS_PHY_1802_DATA 0x00000000 +#define DDRSS_PHY_1803_DATA 0x00000000 +#define DDRSS_PHY_1804_DATA 0x00000000 +#define DDRSS_PHY_1805_DATA 0x00002001 +#define DDRSS_PHY_1806_DATA 0x00004003 +#define DDRSS_PHY_1807_DATA 0x50020028 +#define DDRSS_PHY_1808_DATA 0x01010000 +#define DDRSS_PHY_1809_DATA 0x80080001 +#define DDRSS_PHY_1810_DATA 0x10200000 +#define DDRSS_PHY_1811_DATA 0x00000008 +#define DDRSS_PHY_1812_DATA 0x00000000 +#define DDRSS_PHY_1813_DATA 0x06000000 +#define DDRSS_PHY_1814_DATA 0x010F0F0E +#define DDRSS_PHY_1815_DATA 0x00040101 +#define DDRSS_PHY_1816_DATA 0x0000010F +#define DDRSS_PHY_1817_DATA 0x00000000 +#define DDRSS_PHY_1818_DATA 0x00000064 +#define DDRSS_PHY_1819_DATA 0x00000000 +#define DDRSS_PHY_1820_DATA 0x00000000 +#define DDRSS_PHY_1821_DATA 0x0F0F0F01 +#define DDRSS_PHY_1822_DATA 0x0F0F0F02 +#define DDRSS_PHY_1823_DATA 0x0F0F0F0F +#define DDRSS_PHY_1824_DATA 0x0F0F0804 +#define DDRSS_PHY_1825_DATA 0x00800120 +#define DDRSS_PHY_1826_DATA 0x00041B42 +#define DDRSS_PHY_1827_DATA 0x00005201 +#define DDRSS_PHY_1828_DATA 0x00000000 +#define DDRSS_PHY_1829_DATA 0x00000000 +#define DDRSS_PHY_1830_DATA 0x00000000 +#define DDRSS_PHY_1831_DATA 0x00000000 +#define DDRSS_PHY_1832_DATA 0x00000000 +#define DDRSS_PHY_1833_DATA 0x00000000 +#define DDRSS_PHY_1834_DATA 0x03010100 +#define DDRSS_PHY_1835_DATA 0x00540007 +#define DDRSS_PHY_1836_DATA 0x000040A2 +#define DDRSS_PHY_1837_DATA 0x00024410 +#define DDRSS_PHY_1838_DATA 0x00004410 +#define DDRSS_PHY_1839_DATA 0x00004410 +#define DDRSS_PHY_1840_DATA 0x00004410 +#define DDRSS_PHY_1841_DATA 0x00004410 +#define DDRSS_PHY_1842_DATA 0x00004410 +#define DDRSS_PHY_1843_DATA 0x00004410 +#define DDRSS_PHY_1844_DATA 0x00004410 +#define DDRSS_PHY_1845_DATA 0x00004410 +#define DDRSS_PHY_1846_DATA 0x00004410 +#define DDRSS_PHY_1847_DATA 0x00000000 +#define DDRSS_PHY_1848_DATA 0x00000076 +#define DDRSS_PHY_1849_DATA 0x00000400 +#define DDRSS_PHY_1850_DATA 0x00000008 +#define DDRSS_PHY_1851_DATA 0x00000000 +#define DDRSS_PHY_1852_DATA 0x00000000 +#define DDRSS_PHY_1853_DATA 0x00000000 +#define DDRSS_PHY_1854_DATA 0x00000000 +#define DDRSS_PHY_1855_DATA 0x00000000 +#define DDRSS_PHY_1856_DATA 0x03000000 +#define DDRSS_PHY_1857_DATA 0x00000000 +#define DDRSS_PHY_1858_DATA 0x00000000 +#define DDRSS_PHY_1859_DATA 0x00000000 +#define DDRSS_PHY_1860_DATA 0x04102006 +#define DDRSS_PHY_1861_DATA 0x00041020 +#define DDRSS_PHY_1862_DATA 0x01C98C98 +#define DDRSS_PHY_1863_DATA 0x3F400000 +#define DDRSS_PHY_1864_DATA 0x3F3F1F3F +#define DDRSS_PHY_1865_DATA 0x0000001F +#define DDRSS_PHY_1866_DATA 0x00000000 +#define DDRSS_PHY_1867_DATA 0x00000000 +#define DDRSS_PHY_1868_DATA 0x00000000 +#define DDRSS_PHY_1869_DATA 0x00000001 +#define DDRSS_PHY_1870_DATA 0x00000000 +#define DDRSS_PHY_1871_DATA 0x00000000 +#define DDRSS_PHY_1872_DATA 0x00000000 +#define DDRSS_PHY_1873_DATA 0x00000000 +#define DDRSS_PHY_1874_DATA 0x76543210 +#define DDRSS_PHY_1875_DATA 0x06010198 +#define DDRSS_PHY_1876_DATA 0x00000000 +#define DDRSS_PHY_1877_DATA 0x00000000 +#define DDRSS_PHY_1878_DATA 0x00000000 +#define DDRSS_PHY_1879_DATA 0x00040700 +#define DDRSS_PHY_1880_DATA 0x00000000 +#define DDRSS_PHY_1881_DATA 0x00000000 +#define DDRSS_PHY_1882_DATA 0x00000000 +#define DDRSS_PHY_1883_DATA 0x00000000 +#define DDRSS_PHY_1884_DATA 0x00000000 +#define DDRSS_PHY_1885_DATA 0x00000002 +#define DDRSS_PHY_1886_DATA 0x00000000 +#define DDRSS_PHY_1887_DATA 0x00000000 +#define DDRSS_PHY_1888_DATA 0x00000AC4 +#define DDRSS_PHY_1889_DATA 0x04000004 +#define DDRSS_PHY_1890_DATA 0x00000000 +#define DDRSS_PHY_1891_DATA 0x00001142 +#define DDRSS_PHY_1892_DATA 0x01020000 +#define DDRSS_PHY_1893_DATA 0x00000080 +#define DDRSS_PHY_1894_DATA 0x03900390 +#define DDRSS_PHY_1895_DATA 0x03900390 +#define DDRSS_PHY_1896_DATA 0x03900390 +#define DDRSS_PHY_1897_DATA 0x03900390 +#define DDRSS_PHY_1898_DATA 0x03000300 +#define DDRSS_PHY_1899_DATA 0x03000300 +#define DDRSS_PHY_1900_DATA 0x00000300 +#define DDRSS_PHY_1901_DATA 0x00000300 +#define DDRSS_PHY_1902_DATA 0x00000300 +#define DDRSS_PHY_1903_DATA 0x00000300 +#define DDRSS_PHY_1904_DATA 0x00000005 +#define DDRSS_PHY_1905_DATA 0x3183BF77 +#define DDRSS_PHY_1906_DATA 0x00000000 +#define DDRSS_PHY_1907_DATA 0x0C000DFF +#define DDRSS_PHY_1908_DATA 0x30000DFF +#define DDRSS_PHY_1909_DATA 0x3F0DFF11 +#define DDRSS_PHY_1910_DATA 0x00EF0000 +#define DDRSS_PHY_1911_DATA 0x780DFFCC +#define DDRSS_PHY_1912_DATA 0x00000C11 +#define DDRSS_PHY_1913_DATA 0x00018011 +#define DDRSS_PHY_1914_DATA 0x0089FF00 +#define DDRSS_PHY_1915_DATA 0x000C3F11 +#define DDRSS_PHY_1916_DATA 0x01990000 +#define DDRSS_PHY_1917_DATA 0x000C3F11 +#define DDRSS_PHY_1918_DATA 0x01990000 +#define DDRSS_PHY_1919_DATA 0x3F0DFF11 +#define DDRSS_PHY_1920_DATA 0x00EF0000 +#define DDRSS_PHY_1921_DATA 0x00018011 +#define DDRSS_PHY_1922_DATA 0x0089FF00 +#define DDRSS_PHY_1923_DATA 0x20040004 diff --git a/arch/arm/dts/k3-am62a-ddr.dtsi b/arch/arm/dts/k3-am62a-ddr.dtsi new file mode 100644 index 0000000000..15a0799550 --- /dev/null +++ b/arch/arm/dts/k3-am62a-ddr.dtsi @@ -0,0 +1,2814 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/ { + memorycontroller: memory-controller@f308000 { + compatible = "ti,am62a-ddrss"; + reg = <0x00 0x0f308000 0x00 0x4000>, + <0x00 0x43014000 0x00 0x100>; + reg-names = "cfg", "ctrl_mmr_lp4"; + ti,ddr-freq1 = <DDRSS_PLL_FREQUENCY_1>; + ti,ddr-freq2 = <DDRSS_PLL_FREQUENCY_2>; + ti,ddr-fhs-cnt = <DDRSS_PLL_FHS_CNT>; + + power-domains = <&k3_pds 170 TI_SCI_PD_SHARED>, + <&k3_pds 55 TI_SCI_PD_SHARED>; + clocks = <&k3_clks 170 1>, <&k3_clks 16 4>; + + u-boot,dm-spl; + + ti,ctl-data = < + DDRSS_CTL_0_DATA + DDRSS_CTL_1_DATA + DDRSS_CTL_2_DATA + DDRSS_CTL_3_DATA + DDRSS_CTL_4_DATA + DDRSS_CTL_5_DATA + DDRSS_CTL_6_DATA + DDRSS_CTL_7_DATA + DDRSS_CTL_8_DATA + DDRSS_CTL_9_DATA + DDRSS_CTL_10_DATA + DDRSS_CTL_11_DATA + DDRSS_CTL_12_DATA + DDRSS_CTL_13_DATA + DDRSS_CTL_14_DATA + DDRSS_CTL_15_DATA + DDRSS_CTL_16_DATA + DDRSS_CTL_17_DATA + DDRSS_CTL_18_DATA + DDRSS_CTL_19_DATA + DDRSS_CTL_20_DATA + DDRSS_CTL_21_DATA + DDRSS_CTL_22_DATA + DDRSS_CTL_23_DATA + DDRSS_CTL_24_DATA + DDRSS_CTL_25_DATA + DDRSS_CTL_26_DATA + DDRSS_CTL_27_DATA + DDRSS_CTL_28_DATA + DDRSS_CTL_29_DATA + DDRSS_CTL_30_DATA + DDRSS_CTL_31_DATA + DDRSS_CTL_32_DATA + DDRSS_CTL_33_DATA + DDRSS_CTL_34_DATA + DDRSS_CTL_35_DATA + DDRSS_CTL_36_DATA + DDRSS_CTL_37_DATA + DDRSS_CTL_38_DATA + DDRSS_CTL_39_DATA + DDRSS_CTL_40_DATA + DDRSS_CTL_41_DATA + DDRSS_CTL_42_DATA + DDRSS_CTL_43_DATA + DDRSS_CTL_44_DATA + DDRSS_CTL_45_DATA + DDRSS_CTL_46_DATA + DDRSS_CTL_47_DATA + DDRSS_CTL_48_DATA + DDRSS_CTL_49_DATA + DDRSS_CTL_50_DATA + DDRSS_CTL_51_DATA + DDRSS_CTL_52_DATA + DDRSS_CTL_53_DATA + DDRSS_CTL_54_DATA + DDRSS_CTL_55_DATA + DDRSS_CTL_56_DATA + DDRSS_CTL_57_DATA + DDRSS_CTL_58_DATA + DDRSS_CTL_59_DATA + DDRSS_CTL_60_DATA + DDRSS_CTL_61_DATA + DDRSS_CTL_62_DATA + DDRSS_CTL_63_DATA + DDRSS_CTL_64_DATA + DDRSS_CTL_65_DATA + DDRSS_CTL_66_DATA + DDRSS_CTL_67_DATA + DDRSS_CTL_68_DATA + DDRSS_CTL_69_DATA + DDRSS_CTL_70_DATA + DDRSS_CTL_71_DATA + DDRSS_CTL_72_DATA + DDRSS_CTL_73_DATA + DDRSS_CTL_74_DATA + DDRSS_CTL_75_DATA + DDRSS_CTL_76_DATA + DDRSS_CTL_77_DATA + DDRSS_CTL_78_DATA + DDRSS_CTL_79_DATA + DDRSS_CTL_80_DATA + DDRSS_CTL_81_DATA + DDRSS_CTL_82_DATA + DDRSS_CTL_83_DATA + DDRSS_CTL_84_DATA + DDRSS_CTL_85_DATA + DDRSS_CTL_86_DATA + DDRSS_CTL_87_DATA + DDRSS_CTL_88_DATA + DDRSS_CTL_89_DATA + DDRSS_CTL_90_DATA + DDRSS_CTL_91_DATA + DDRSS_CTL_92_DATA + DDRSS_CTL_93_DATA + DDRSS_CTL_94_DATA + DDRSS_CTL_95_DATA + DDRSS_CTL_96_DATA + DDRSS_CTL_97_DATA + DDRSS_CTL_98_DATA + DDRSS_CTL_99_DATA + DDRSS_CTL_100_DATA + DDRSS_CTL_101_DATA + DDRSS_CTL_102_DATA + DDRSS_CTL_103_DATA + DDRSS_CTL_104_DATA + DDRSS_CTL_105_DATA + DDRSS_CTL_106_DATA + DDRSS_CTL_107_DATA + DDRSS_CTL_108_DATA + DDRSS_CTL_109_DATA + DDRSS_CTL_110_DATA + DDRSS_CTL_111_DATA + DDRSS_CTL_112_DATA + DDRSS_CTL_113_DATA + DDRSS_CTL_114_DATA + DDRSS_CTL_115_DATA + DDRSS_CTL_116_DATA + DDRSS_CTL_117_DATA + DDRSS_CTL_118_DATA + DDRSS_CTL_119_DATA + DDRSS_CTL_120_DATA + DDRSS_CTL_121_DATA + DDRSS_CTL_122_DATA + DDRSS_CTL_123_DATA + DDRSS_CTL_124_DATA + DDRSS_CTL_125_DATA + DDRSS_CTL_126_DATA + DDRSS_CTL_127_DATA + DDRSS_CTL_128_DATA + DDRSS_CTL_129_DATA + DDRSS_CTL_130_DATA + DDRSS_CTL_131_DATA + DDRSS_CTL_132_DATA + DDRSS_CTL_133_DATA + DDRSS_CTL_134_DATA + DDRSS_CTL_135_DATA + DDRSS_CTL_136_DATA + DDRSS_CTL_137_DATA + DDRSS_CTL_138_DATA + DDRSS_CTL_139_DATA + DDRSS_CTL_140_DATA + DDRSS_CTL_141_DATA + DDRSS_CTL_142_DATA + DDRSS_CTL_143_DATA + DDRSS_CTL_144_DATA + DDRSS_CTL_145_DATA + DDRSS_CTL_146_DATA + DDRSS_CTL_147_DATA + DDRSS_CTL_148_DATA + DDRSS_CTL_149_DATA + DDRSS_CTL_150_DATA + DDRSS_CTL_151_DATA + DDRSS_CTL_152_DATA + DDRSS_CTL_153_DATA + DDRSS_CTL_154_DATA + DDRSS_CTL_155_DATA + DDRSS_CTL_156_DATA + DDRSS_CTL_157_DATA + DDRSS_CTL_158_DATA + DDRSS_CTL_159_DATA + DDRSS_CTL_160_DATA + DDRSS_CTL_161_DATA + DDRSS_CTL_162_DATA + DDRSS_CTL_163_DATA + DDRSS_CTL_164_DATA + DDRSS_CTL_165_DATA + DDRSS_CTL_166_DATA + DDRSS_CTL_167_DATA + DDRSS_CTL_168_DATA + DDRSS_CTL_169_DATA + DDRSS_CTL_170_DATA + DDRSS_CTL_171_DATA + DDRSS_CTL_172_DATA + DDRSS_CTL_173_DATA + DDRSS_CTL_174_DATA + DDRSS_CTL_175_DATA + DDRSS_CTL_176_DATA + DDRSS_CTL_177_DATA + DDRSS_CTL_178_DATA + DDRSS_CTL_179_DATA + DDRSS_CTL_180_DATA + DDRSS_CTL_181_DATA + DDRSS_CTL_182_DATA + DDRSS_CTL_183_DATA + DDRSS_CTL_184_DATA + DDRSS_CTL_185_DATA + DDRSS_CTL_186_DATA + DDRSS_CTL_187_DATA + DDRSS_CTL_188_DATA + DDRSS_CTL_189_DATA + DDRSS_CTL_190_DATA + DDRSS_CTL_191_DATA + DDRSS_CTL_192_DATA + DDRSS_CTL_193_DATA + DDRSS_CTL_194_DATA + DDRSS_CTL_195_DATA + DDRSS_CTL_196_DATA + DDRSS_CTL_197_DATA + DDRSS_CTL_198_DATA + DDRSS_CTL_199_DATA + DDRSS_CTL_200_DATA + DDRSS_CTL_201_DATA + DDRSS_CTL_202_DATA + DDRSS_CTL_203_DATA + DDRSS_CTL_204_DATA + DDRSS_CTL_205_DATA + DDRSS_CTL_206_DATA + DDRSS_CTL_207_DATA + DDRSS_CTL_208_DATA + DDRSS_CTL_209_DATA + DDRSS_CTL_210_DATA + DDRSS_CTL_211_DATA + DDRSS_CTL_212_DATA + DDRSS_CTL_213_DATA + DDRSS_CTL_214_DATA + DDRSS_CTL_215_DATA + DDRSS_CTL_216_DATA + DDRSS_CTL_217_DATA + DDRSS_CTL_218_DATA + DDRSS_CTL_219_DATA + DDRSS_CTL_220_DATA + DDRSS_CTL_221_DATA + DDRSS_CTL_222_DATA + DDRSS_CTL_223_DATA + DDRSS_CTL_224_DATA + DDRSS_CTL_225_DATA + DDRSS_CTL_226_DATA + DDRSS_CTL_227_DATA + DDRSS_CTL_228_DATA + DDRSS_CTL_229_DATA + DDRSS_CTL_230_DATA + DDRSS_CTL_231_DATA + DDRSS_CTL_232_DATA + DDRSS_CTL_233_DATA + DDRSS_CTL_234_DATA + DDRSS_CTL_235_DATA + DDRSS_CTL_236_DATA + DDRSS_CTL_237_DATA + DDRSS_CTL_238_DATA + DDRSS_CTL_239_DATA + DDRSS_CTL_240_DATA + DDRSS_CTL_241_DATA + DDRSS_CTL_242_DATA + DDRSS_CTL_243_DATA + DDRSS_CTL_244_DATA + DDRSS_CTL_245_DATA + DDRSS_CTL_246_DATA + DDRSS_CTL_247_DATA + DDRSS_CTL_248_DATA + DDRSS_CTL_249_DATA + DDRSS_CTL_250_DATA + DDRSS_CTL_251_DATA + DDRSS_CTL_252_DATA + DDRSS_CTL_253_DATA + DDRSS_CTL_254_DATA + DDRSS_CTL_255_DATA + DDRSS_CTL_256_DATA + DDRSS_CTL_257_DATA + DDRSS_CTL_258_DATA + DDRSS_CTL_259_DATA + DDRSS_CTL_260_DATA + DDRSS_CTL_261_DATA + DDRSS_CTL_262_DATA + DDRSS_CTL_263_DATA + DDRSS_CTL_264_DATA + DDRSS_CTL_265_DATA + DDRSS_CTL_266_DATA + DDRSS_CTL_267_DATA + DDRSS_CTL_268_DATA + DDRSS_CTL_269_DATA + DDRSS_CTL_270_DATA + DDRSS_CTL_271_DATA + DDRSS_CTL_272_DATA + DDRSS_CTL_273_DATA + DDRSS_CTL_274_DATA + DDRSS_CTL_275_DATA + DDRSS_CTL_276_DATA + DDRSS_CTL_277_DATA + DDRSS_CTL_278_DATA + DDRSS_CTL_279_DATA + DDRSS_CTL_280_DATA + DDRSS_CTL_281_DATA + DDRSS_CTL_282_DATA + DDRSS_CTL_283_DATA + DDRSS_CTL_284_DATA + DDRSS_CTL_285_DATA + DDRSS_CTL_286_DATA + DDRSS_CTL_287_DATA + DDRSS_CTL_288_DATA + DDRSS_CTL_289_DATA + DDRSS_CTL_290_DATA + DDRSS_CTL_291_DATA + DDRSS_CTL_292_DATA + DDRSS_CTL_293_DATA + DDRSS_CTL_294_DATA + DDRSS_CTL_295_DATA + DDRSS_CTL_296_DATA + DDRSS_CTL_297_DATA + DDRSS_CTL_298_DATA + DDRSS_CTL_299_DATA + DDRSS_CTL_300_DATA + DDRSS_CTL_301_DATA + DDRSS_CTL_302_DATA + DDRSS_CTL_303_DATA + DDRSS_CTL_304_DATA + DDRSS_CTL_305_DATA + DDRSS_CTL_306_DATA + DDRSS_CTL_307_DATA + DDRSS_CTL_308_DATA + DDRSS_CTL_309_DATA + DDRSS_CTL_310_DATA + DDRSS_CTL_311_DATA + DDRSS_CTL_312_DATA + DDRSS_CTL_313_DATA + DDRSS_CTL_314_DATA + DDRSS_CTL_315_DATA + DDRSS_CTL_316_DATA + DDRSS_CTL_317_DATA + DDRSS_CTL_318_DATA + DDRSS_CTL_319_DATA + DDRSS_CTL_320_DATA + DDRSS_CTL_321_DATA + DDRSS_CTL_322_DATA + DDRSS_CTL_323_DATA + DDRSS_CTL_324_DATA + DDRSS_CTL_325_DATA + DDRSS_CTL_326_DATA + DDRSS_CTL_327_DATA + DDRSS_CTL_328_DATA + DDRSS_CTL_329_DATA + DDRSS_CTL_330_DATA + DDRSS_CTL_331_DATA + DDRSS_CTL_332_DATA + DDRSS_CTL_333_DATA + DDRSS_CTL_334_DATA + DDRSS_CTL_335_DATA + DDRSS_CTL_336_DATA + DDRSS_CTL_337_DATA + DDRSS_CTL_338_DATA + DDRSS_CTL_339_DATA + DDRSS_CTL_340_DATA + DDRSS_CTL_341_DATA + DDRSS_CTL_342_DATA + DDRSS_CTL_343_DATA + DDRSS_CTL_344_DATA + DDRSS_CTL_345_DATA + DDRSS_CTL_346_DATA + DDRSS_CTL_347_DATA + DDRSS_CTL_348_DATA + DDRSS_CTL_349_DATA + DDRSS_CTL_350_DATA + DDRSS_CTL_351_DATA + DDRSS_CTL_352_DATA + DDRSS_CTL_353_DATA + DDRSS_CTL_354_DATA + DDRSS_CTL_355_DATA + DDRSS_CTL_356_DATA + DDRSS_CTL_357_DATA + DDRSS_CTL_358_DATA + DDRSS_CTL_359_DATA + DDRSS_CTL_360_DATA + DDRSS_CTL_361_DATA + DDRSS_CTL_362_DATA + DDRSS_CTL_363_DATA + DDRSS_CTL_364_DATA + DDRSS_CTL_365_DATA + DDRSS_CTL_366_DATA + DDRSS_CTL_367_DATA + DDRSS_CTL_368_DATA + DDRSS_CTL_369_DATA + DDRSS_CTL_370_DATA + DDRSS_CTL_371_DATA + DDRSS_CTL_372_DATA + DDRSS_CTL_373_DATA + DDRSS_CTL_374_DATA + DDRSS_CTL_375_DATA + DDRSS_CTL_376_DATA + DDRSS_CTL_377_DATA + DDRSS_CTL_378_DATA + DDRSS_CTL_379_DATA + DDRSS_CTL_380_DATA + DDRSS_CTL_381_DATA + DDRSS_CTL_382_DATA + DDRSS_CTL_383_DATA + DDRSS_CTL_384_DATA + DDRSS_CTL_385_DATA + DDRSS_CTL_386_DATA + DDRSS_CTL_387_DATA + DDRSS_CTL_388_DATA + DDRSS_CTL_389_DATA + DDRSS_CTL_390_DATA + DDRSS_CTL_391_DATA + DDRSS_CTL_392_DATA + DDRSS_CTL_393_DATA + DDRSS_CTL_394_DATA + DDRSS_CTL_395_DATA + DDRSS_CTL_396_DATA + DDRSS_CTL_397_DATA + DDRSS_CTL_398_DATA + DDRSS_CTL_399_DATA + DDRSS_CTL_400_DATA + DDRSS_CTL_401_DATA + DDRSS_CTL_402_DATA + DDRSS_CTL_403_DATA + DDRSS_CTL_404_DATA + DDRSS_CTL_405_DATA + DDRSS_CTL_406_DATA + DDRSS_CTL_407_DATA + DDRSS_CTL_408_DATA + DDRSS_CTL_409_DATA + DDRSS_CTL_410_DATA + DDRSS_CTL_411_DATA + DDRSS_CTL_412_DATA + DDRSS_CTL_413_DATA + DDRSS_CTL_414_DATA + DDRSS_CTL_415_DATA + DDRSS_CTL_416_DATA + DDRSS_CTL_417_DATA + DDRSS_CTL_418_DATA + DDRSS_CTL_419_DATA + DDRSS_CTL_420_DATA + DDRSS_CTL_421_DATA + DDRSS_CTL_422_DATA + DDRSS_CTL_423_DATA + DDRSS_CTL_424_DATA + DDRSS_CTL_425_DATA + DDRSS_CTL_426_DATA + DDRSS_CTL_427_DATA + DDRSS_CTL_428_DATA + DDRSS_CTL_429_DATA + DDRSS_CTL_430_DATA + DDRSS_CTL_431_DATA + DDRSS_CTL_432_DATA + DDRSS_CTL_433_DATA + DDRSS_CTL_434_DATA + >; + + ti,pi-data = < + DDRSS_PI_0_DATA + DDRSS_PI_1_DATA + DDRSS_PI_2_DATA + DDRSS_PI_3_DATA + DDRSS_PI_4_DATA + DDRSS_PI_5_DATA + DDRSS_PI_6_DATA + DDRSS_PI_7_DATA + DDRSS_PI_8_DATA + DDRSS_PI_9_DATA + DDRSS_PI_10_DATA + DDRSS_PI_11_DATA + DDRSS_PI_12_DATA + DDRSS_PI_13_DATA + DDRSS_PI_14_DATA + DDRSS_PI_15_DATA + DDRSS_PI_16_DATA + DDRSS_PI_17_DATA + DDRSS_PI_18_DATA + DDRSS_PI_19_DATA + DDRSS_PI_20_DATA + DDRSS_PI_21_DATA + DDRSS_PI_22_DATA + DDRSS_PI_23_DATA + DDRSS_PI_24_DATA + DDRSS_PI_25_DATA + DDRSS_PI_26_DATA + DDRSS_PI_27_DATA + DDRSS_PI_28_DATA + DDRSS_PI_29_DATA + DDRSS_PI_30_DATA + DDRSS_PI_31_DATA + DDRSS_PI_32_DATA + DDRSS_PI_33_DATA + DDRSS_PI_34_DATA + DDRSS_PI_35_DATA + DDRSS_PI_36_DATA + DDRSS_PI_37_DATA + DDRSS_PI_38_DATA + DDRSS_PI_39_DATA + DDRSS_PI_40_DATA + DDRSS_PI_41_DATA + DDRSS_PI_42_DATA + DDRSS_PI_43_DATA + DDRSS_PI_44_DATA + DDRSS_PI_45_DATA + DDRSS_PI_46_DATA + DDRSS_PI_47_DATA + DDRSS_PI_48_DATA + DDRSS_PI_49_DATA + DDRSS_PI_50_DATA + DDRSS_PI_51_DATA + DDRSS_PI_52_DATA + DDRSS_PI_53_DATA + DDRSS_PI_54_DATA + DDRSS_PI_55_DATA + DDRSS_PI_56_DATA + DDRSS_PI_57_DATA + DDRSS_PI_58_DATA + DDRSS_PI_59_DATA + DDRSS_PI_60_DATA + DDRSS_PI_61_DATA + DDRSS_PI_62_DATA + DDRSS_PI_63_DATA + DDRSS_PI_64_DATA + DDRSS_PI_65_DATA + DDRSS_PI_66_DATA + DDRSS_PI_67_DATA + DDRSS_PI_68_DATA + DDRSS_PI_69_DATA + DDRSS_PI_70_DATA + DDRSS_PI_71_DATA + DDRSS_PI_72_DATA + DDRSS_PI_73_DATA + DDRSS_PI_74_DATA + DDRSS_PI_75_DATA + DDRSS_PI_76_DATA + DDRSS_PI_77_DATA + DDRSS_PI_78_DATA + DDRSS_PI_79_DATA + DDRSS_PI_80_DATA + DDRSS_PI_81_DATA + DDRSS_PI_82_DATA + DDRSS_PI_83_DATA + DDRSS_PI_84_DATA + DDRSS_PI_85_DATA + DDRSS_PI_86_DATA + DDRSS_PI_87_DATA + DDRSS_PI_88_DATA + DDRSS_PI_89_DATA + DDRSS_PI_90_DATA + DDRSS_PI_91_DATA + DDRSS_PI_92_DATA + DDRSS_PI_93_DATA + DDRSS_PI_94_DATA + DDRSS_PI_95_DATA + DDRSS_PI_96_DATA + DDRSS_PI_97_DATA + DDRSS_PI_98_DATA + DDRSS_PI_99_DATA + DDRSS_PI_100_DATA + DDRSS_PI_101_DATA + DDRSS_PI_102_DATA + DDRSS_PI_103_DATA + DDRSS_PI_104_DATA + DDRSS_PI_105_DATA + DDRSS_PI_106_DATA + DDRSS_PI_107_DATA + DDRSS_PI_108_DATA + DDRSS_PI_109_DATA + DDRSS_PI_110_DATA + DDRSS_PI_111_DATA + DDRSS_PI_112_DATA + DDRSS_PI_113_DATA + DDRSS_PI_114_DATA + DDRSS_PI_115_DATA + DDRSS_PI_116_DATA + DDRSS_PI_117_DATA + DDRSS_PI_118_DATA + DDRSS_PI_119_DATA + DDRSS_PI_120_DATA + DDRSS_PI_121_DATA + DDRSS_PI_122_DATA + DDRSS_PI_123_DATA + DDRSS_PI_124_DATA + DDRSS_PI_125_DATA + DDRSS_PI_126_DATA + DDRSS_PI_127_DATA + DDRSS_PI_128_DATA + DDRSS_PI_129_DATA + DDRSS_PI_130_DATA + DDRSS_PI_131_DATA + DDRSS_PI_132_DATA + DDRSS_PI_133_DATA + DDRSS_PI_134_DATA + DDRSS_PI_135_DATA + DDRSS_PI_136_DATA + DDRSS_PI_137_DATA + DDRSS_PI_138_DATA + DDRSS_PI_139_DATA + DDRSS_PI_140_DATA + DDRSS_PI_141_DATA + DDRSS_PI_142_DATA + DDRSS_PI_143_DATA + DDRSS_PI_144_DATA + DDRSS_PI_145_DATA + DDRSS_PI_146_DATA + DDRSS_PI_147_DATA + DDRSS_PI_148_DATA + DDRSS_PI_149_DATA + DDRSS_PI_150_DATA + DDRSS_PI_151_DATA + DDRSS_PI_152_DATA + DDRSS_PI_153_DATA + DDRSS_PI_154_DATA + DDRSS_PI_155_DATA + DDRSS_PI_156_DATA + DDRSS_PI_157_DATA + DDRSS_PI_158_DATA + DDRSS_PI_159_DATA + DDRSS_PI_160_DATA + DDRSS_PI_161_DATA + DDRSS_PI_162_DATA + DDRSS_PI_163_DATA + DDRSS_PI_164_DATA + DDRSS_PI_165_DATA + DDRSS_PI_166_DATA + DDRSS_PI_167_DATA + DDRSS_PI_168_DATA + DDRSS_PI_169_DATA + DDRSS_PI_170_DATA + DDRSS_PI_171_DATA + DDRSS_PI_172_DATA + DDRSS_PI_173_DATA + DDRSS_PI_174_DATA + DDRSS_PI_175_DATA + DDRSS_PI_176_DATA + DDRSS_PI_177_DATA + DDRSS_PI_178_DATA + DDRSS_PI_179_DATA + DDRSS_PI_180_DATA + DDRSS_PI_181_DATA + DDRSS_PI_182_DATA + DDRSS_PI_183_DATA + DDRSS_PI_184_DATA + DDRSS_PI_185_DATA + DDRSS_PI_186_DATA + DDRSS_PI_187_DATA + DDRSS_PI_188_DATA + DDRSS_PI_189_DATA + DDRSS_PI_190_DATA + DDRSS_PI_191_DATA + DDRSS_PI_192_DATA + DDRSS_PI_193_DATA + DDRSS_PI_194_DATA + DDRSS_PI_195_DATA + DDRSS_PI_196_DATA + DDRSS_PI_197_DATA + DDRSS_PI_198_DATA + DDRSS_PI_199_DATA + DDRSS_PI_200_DATA + DDRSS_PI_201_DATA + DDRSS_PI_202_DATA + DDRSS_PI_203_DATA + DDRSS_PI_204_DATA + DDRSS_PI_205_DATA + DDRSS_PI_206_DATA + DDRSS_PI_207_DATA + DDRSS_PI_208_DATA + DDRSS_PI_209_DATA + DDRSS_PI_210_DATA + DDRSS_PI_211_DATA + DDRSS_PI_212_DATA + DDRSS_PI_213_DATA + DDRSS_PI_214_DATA + DDRSS_PI_215_DATA + DDRSS_PI_216_DATA + DDRSS_PI_217_DATA + DDRSS_PI_218_DATA + DDRSS_PI_219_DATA + DDRSS_PI_220_DATA + DDRSS_PI_221_DATA + DDRSS_PI_222_DATA + DDRSS_PI_223_DATA + DDRSS_PI_224_DATA + DDRSS_PI_225_DATA + DDRSS_PI_226_DATA + DDRSS_PI_227_DATA + DDRSS_PI_228_DATA + DDRSS_PI_229_DATA + DDRSS_PI_230_DATA + DDRSS_PI_231_DATA + DDRSS_PI_232_DATA + DDRSS_PI_233_DATA + DDRSS_PI_234_DATA + DDRSS_PI_235_DATA + DDRSS_PI_236_DATA + DDRSS_PI_237_DATA + DDRSS_PI_238_DATA + DDRSS_PI_239_DATA + DDRSS_PI_240_DATA + DDRSS_PI_241_DATA + DDRSS_PI_242_DATA + DDRSS_PI_243_DATA + DDRSS_PI_244_DATA + DDRSS_PI_245_DATA + DDRSS_PI_246_DATA + DDRSS_PI_247_DATA + DDRSS_PI_248_DATA + DDRSS_PI_249_DATA + DDRSS_PI_250_DATA + DDRSS_PI_251_DATA + DDRSS_PI_252_DATA + DDRSS_PI_253_DATA + DDRSS_PI_254_DATA + DDRSS_PI_255_DATA + DDRSS_PI_256_DATA + DDRSS_PI_257_DATA + DDRSS_PI_258_DATA + DDRSS_PI_259_DATA + DDRSS_PI_260_DATA + DDRSS_PI_261_DATA + DDRSS_PI_262_DATA + DDRSS_PI_263_DATA + DDRSS_PI_264_DATA + DDRSS_PI_265_DATA + DDRSS_PI_266_DATA + DDRSS_PI_267_DATA + DDRSS_PI_268_DATA + DDRSS_PI_269_DATA + DDRSS_PI_270_DATA + DDRSS_PI_271_DATA + DDRSS_PI_272_DATA + DDRSS_PI_273_DATA + DDRSS_PI_274_DATA + DDRSS_PI_275_DATA + DDRSS_PI_276_DATA + DDRSS_PI_277_DATA + DDRSS_PI_278_DATA + DDRSS_PI_279_DATA + DDRSS_PI_280_DATA + DDRSS_PI_281_DATA + DDRSS_PI_282_DATA + DDRSS_PI_283_DATA + DDRSS_PI_284_DATA + DDRSS_PI_285_DATA + DDRSS_PI_286_DATA + DDRSS_PI_287_DATA + DDRSS_PI_288_DATA + DDRSS_PI_289_DATA + DDRSS_PI_290_DATA + DDRSS_PI_291_DATA + DDRSS_PI_292_DATA + DDRSS_PI_293_DATA + DDRSS_PI_294_DATA + DDRSS_PI_295_DATA + DDRSS_PI_296_DATA + DDRSS_PI_297_DATA + DDRSS_PI_298_DATA + DDRSS_PI_299_DATA + DDRSS_PI_300_DATA + DDRSS_PI_301_DATA + DDRSS_PI_302_DATA + DDRSS_PI_303_DATA + DDRSS_PI_304_DATA + DDRSS_PI_305_DATA + DDRSS_PI_306_DATA + DDRSS_PI_307_DATA + DDRSS_PI_308_DATA + DDRSS_PI_309_DATA + DDRSS_PI_310_DATA + DDRSS_PI_311_DATA + DDRSS_PI_312_DATA + DDRSS_PI_313_DATA + DDRSS_PI_314_DATA + DDRSS_PI_315_DATA + DDRSS_PI_316_DATA + DDRSS_PI_317_DATA + DDRSS_PI_318_DATA + DDRSS_PI_319_DATA + DDRSS_PI_320_DATA + DDRSS_PI_321_DATA + DDRSS_PI_322_DATA + DDRSS_PI_323_DATA + DDRSS_PI_324_DATA + DDRSS_PI_325_DATA + DDRSS_PI_326_DATA + DDRSS_PI_327_DATA + DDRSS_PI_328_DATA + DDRSS_PI_329_DATA + DDRSS_PI_330_DATA + DDRSS_PI_331_DATA + DDRSS_PI_332_DATA + DDRSS_PI_333_DATA + DDRSS_PI_334_DATA + DDRSS_PI_335_DATA + DDRSS_PI_336_DATA + DDRSS_PI_337_DATA + DDRSS_PI_338_DATA + DDRSS_PI_339_DATA + DDRSS_PI_340_DATA + DDRSS_PI_341_DATA + DDRSS_PI_342_DATA + DDRSS_PI_343_DATA + DDRSS_PI_344_DATA + DDRSS_PI_345_DATA + DDRSS_PI_346_DATA + DDRSS_PI_347_DATA + DDRSS_PI_348_DATA + DDRSS_PI_349_DATA + DDRSS_PI_350_DATA + DDRSS_PI_351_DATA + DDRSS_PI_352_DATA + DDRSS_PI_353_DATA + DDRSS_PI_354_DATA + DDRSS_PI_355_DATA + DDRSS_PI_356_DATA + DDRSS_PI_357_DATA + DDRSS_PI_358_DATA + DDRSS_PI_359_DATA + DDRSS_PI_360_DATA + DDRSS_PI_361_DATA + DDRSS_PI_362_DATA + DDRSS_PI_363_DATA + DDRSS_PI_364_DATA + DDRSS_PI_365_DATA + DDRSS_PI_366_DATA + DDRSS_PI_367_DATA + DDRSS_PI_368_DATA + DDRSS_PI_369_DATA + DDRSS_PI_370_DATA + DDRSS_PI_371_DATA + DDRSS_PI_372_DATA + DDRSS_PI_373_DATA + DDRSS_PI_374_DATA + DDRSS_PI_375_DATA + DDRSS_PI_376_DATA + DDRSS_PI_377_DATA + DDRSS_PI_378_DATA + DDRSS_PI_379_DATA + DDRSS_PI_380_DATA + DDRSS_PI_381_DATA + DDRSS_PI_382_DATA + DDRSS_PI_383_DATA + DDRSS_PI_384_DATA + DDRSS_PI_385_DATA + DDRSS_PI_386_DATA + DDRSS_PI_387_DATA + DDRSS_PI_388_DATA + DDRSS_PI_389_DATA + DDRSS_PI_390_DATA + DDRSS_PI_391_DATA + DDRSS_PI_392_DATA + DDRSS_PI_393_DATA + DDRSS_PI_394_DATA + DDRSS_PI_395_DATA + DDRSS_PI_396_DATA + DDRSS_PI_397_DATA + DDRSS_PI_398_DATA + DDRSS_PI_399_DATA + DDRSS_PI_400_DATA + DDRSS_PI_401_DATA + DDRSS_PI_402_DATA + DDRSS_PI_403_DATA + DDRSS_PI_404_DATA + DDRSS_PI_405_DATA + DDRSS_PI_406_DATA + DDRSS_PI_407_DATA + DDRSS_PI_408_DATA + DDRSS_PI_409_DATA + DDRSS_PI_410_DATA + DDRSS_PI_411_DATA + DDRSS_PI_412_DATA + DDRSS_PI_413_DATA + DDRSS_PI_414_DATA + DDRSS_PI_415_DATA + DDRSS_PI_416_DATA + DDRSS_PI_417_DATA + DDRSS_PI_418_DATA + DDRSS_PI_419_DATA + DDRSS_PI_420_DATA + DDRSS_PI_421_DATA + DDRSS_PI_422_DATA + DDRSS_PI_423_DATA + >; + + ti,phy-data = < + DDRSS_PHY_0_DATA + DDRSS_PHY_1_DATA + DDRSS_PHY_2_DATA + DDRSS_PHY_3_DATA + DDRSS_PHY_4_DATA + DDRSS_PHY_5_DATA + DDRSS_PHY_6_DATA + DDRSS_PHY_7_DATA + DDRSS_PHY_8_DATA + DDRSS_PHY_9_DATA + DDRSS_PHY_10_DATA + DDRSS_PHY_11_DATA + DDRSS_PHY_12_DATA + DDRSS_PHY_13_DATA + DDRSS_PHY_14_DATA + DDRSS_PHY_15_DATA + DDRSS_PHY_16_DATA + DDRSS_PHY_17_DATA + DDRSS_PHY_18_DATA + DDRSS_PHY_19_DATA + DDRSS_PHY_20_DATA + DDRSS_PHY_21_DATA + DDRSS_PHY_22_DATA + DDRSS_PHY_23_DATA + DDRSS_PHY_24_DATA + DDRSS_PHY_25_DATA + DDRSS_PHY_26_DATA + DDRSS_PHY_27_DATA + DDRSS_PHY_28_DATA + DDRSS_PHY_29_DATA + DDRSS_PHY_30_DATA + DDRSS_PHY_31_DATA + DDRSS_PHY_32_DATA + DDRSS_PHY_33_DATA + DDRSS_PHY_34_DATA + DDRSS_PHY_35_DATA + DDRSS_PHY_36_DATA + DDRSS_PHY_37_DATA + DDRSS_PHY_38_DATA + DDRSS_PHY_39_DATA + DDRSS_PHY_40_DATA + DDRSS_PHY_41_DATA + DDRSS_PHY_42_DATA + DDRSS_PHY_43_DATA + DDRSS_PHY_44_DATA + DDRSS_PHY_45_DATA + DDRSS_PHY_46_DATA + DDRSS_PHY_47_DATA + DDRSS_PHY_48_DATA + DDRSS_PHY_49_DATA + DDRSS_PHY_50_DATA + DDRSS_PHY_51_DATA + DDRSS_PHY_52_DATA + DDRSS_PHY_53_DATA + DDRSS_PHY_54_DATA + DDRSS_PHY_55_DATA + DDRSS_PHY_56_DATA + DDRSS_PHY_57_DATA + DDRSS_PHY_58_DATA + DDRSS_PHY_59_DATA + DDRSS_PHY_60_DATA + DDRSS_PHY_61_DATA + DDRSS_PHY_62_DATA + DDRSS_PHY_63_DATA + DDRSS_PHY_64_DATA + DDRSS_PHY_65_DATA + DDRSS_PHY_66_DATA + DDRSS_PHY_67_DATA + DDRSS_PHY_68_DATA + DDRSS_PHY_69_DATA + DDRSS_PHY_70_DATA + DDRSS_PHY_71_DATA + DDRSS_PHY_72_DATA + DDRSS_PHY_73_DATA + DDRSS_PHY_74_DATA + DDRSS_PHY_75_DATA + DDRSS_PHY_76_DATA + DDRSS_PHY_77_DATA + DDRSS_PHY_78_DATA + DDRSS_PHY_79_DATA + DDRSS_PHY_80_DATA + DDRSS_PHY_81_DATA + DDRSS_PHY_82_DATA + DDRSS_PHY_83_DATA + DDRSS_PHY_84_DATA + DDRSS_PHY_85_DATA + DDRSS_PHY_86_DATA + DDRSS_PHY_87_DATA + DDRSS_PHY_88_DATA + DDRSS_PHY_89_DATA + DDRSS_PHY_90_DATA + DDRSS_PHY_91_DATA + DDRSS_PHY_92_DATA + DDRSS_PHY_93_DATA + DDRSS_PHY_94_DATA + DDRSS_PHY_95_DATA + DDRSS_PHY_96_DATA + DDRSS_PHY_97_DATA + DDRSS_PHY_98_DATA + DDRSS_PHY_99_DATA + DDRSS_PHY_100_DATA + DDRSS_PHY_101_DATA + DDRSS_PHY_102_DATA + DDRSS_PHY_103_DATA + DDRSS_PHY_104_DATA + DDRSS_PHY_105_DATA + DDRSS_PHY_106_DATA + DDRSS_PHY_107_DATA + DDRSS_PHY_108_DATA + DDRSS_PHY_109_DATA + DDRSS_PHY_110_DATA + DDRSS_PHY_111_DATA + DDRSS_PHY_112_DATA + DDRSS_PHY_113_DATA + DDRSS_PHY_114_DATA + DDRSS_PHY_115_DATA + DDRSS_PHY_116_DATA + DDRSS_PHY_117_DATA + DDRSS_PHY_118_DATA + DDRSS_PHY_119_DATA + DDRSS_PHY_120_DATA + DDRSS_PHY_121_DATA + DDRSS_PHY_122_DATA + DDRSS_PHY_123_DATA + DDRSS_PHY_124_DATA + DDRSS_PHY_125_DATA + DDRSS_PHY_126_DATA + DDRSS_PHY_127_DATA + DDRSS_PHY_128_DATA + DDRSS_PHY_129_DATA + DDRSS_PHY_130_DATA + DDRSS_PHY_131_DATA + DDRSS_PHY_132_DATA + DDRSS_PHY_133_DATA + DDRSS_PHY_134_DATA + DDRSS_PHY_135_DATA + DDRSS_PHY_136_DATA + DDRSS_PHY_137_DATA + DDRSS_PHY_138_DATA + DDRSS_PHY_139_DATA + DDRSS_PHY_140_DATA + DDRSS_PHY_141_DATA + DDRSS_PHY_142_DATA + DDRSS_PHY_143_DATA + DDRSS_PHY_144_DATA + DDRSS_PHY_145_DATA + DDRSS_PHY_146_DATA + DDRSS_PHY_147_DATA + DDRSS_PHY_148_DATA + DDRSS_PHY_149_DATA + DDRSS_PHY_150_DATA + DDRSS_PHY_151_DATA + DDRSS_PHY_152_DATA + DDRSS_PHY_153_DATA + DDRSS_PHY_154_DATA + DDRSS_PHY_155_DATA + DDRSS_PHY_156_DATA + DDRSS_PHY_157_DATA + DDRSS_PHY_158_DATA + DDRSS_PHY_159_DATA + DDRSS_PHY_160_DATA + DDRSS_PHY_161_DATA + DDRSS_PHY_162_DATA + DDRSS_PHY_163_DATA + DDRSS_PHY_164_DATA + DDRSS_PHY_165_DATA + DDRSS_PHY_166_DATA + DDRSS_PHY_167_DATA + DDRSS_PHY_168_DATA + DDRSS_PHY_169_DATA + DDRSS_PHY_170_DATA + DDRSS_PHY_171_DATA + DDRSS_PHY_172_DATA + DDRSS_PHY_173_DATA + DDRSS_PHY_174_DATA + DDRSS_PHY_175_DATA + DDRSS_PHY_176_DATA + DDRSS_PHY_177_DATA + DDRSS_PHY_178_DATA + DDRSS_PHY_179_DATA + DDRSS_PHY_180_DATA + DDRSS_PHY_181_DATA + DDRSS_PHY_182_DATA + DDRSS_PHY_183_DATA + DDRSS_PHY_184_DATA + DDRSS_PHY_185_DATA + DDRSS_PHY_186_DATA + DDRSS_PHY_187_DATA + DDRSS_PHY_188_DATA + DDRSS_PHY_189_DATA + DDRSS_PHY_190_DATA + DDRSS_PHY_191_DATA + DDRSS_PHY_192_DATA + DDRSS_PHY_193_DATA + DDRSS_PHY_194_DATA + DDRSS_PHY_195_DATA + DDRSS_PHY_196_DATA + DDRSS_PHY_197_DATA + DDRSS_PHY_198_DATA + DDRSS_PHY_199_DATA + DDRSS_PHY_200_DATA + DDRSS_PHY_201_DATA + DDRSS_PHY_202_DATA + DDRSS_PHY_203_DATA + DDRSS_PHY_204_DATA + DDRSS_PHY_205_DATA + DDRSS_PHY_206_DATA + DDRSS_PHY_207_DATA + DDRSS_PHY_208_DATA + DDRSS_PHY_209_DATA + DDRSS_PHY_210_DATA + DDRSS_PHY_211_DATA + DDRSS_PHY_212_DATA + DDRSS_PHY_213_DATA + DDRSS_PHY_214_DATA + DDRSS_PHY_215_DATA + DDRSS_PHY_216_DATA + DDRSS_PHY_217_DATA + DDRSS_PHY_218_DATA + DDRSS_PHY_219_DATA + DDRSS_PHY_220_DATA + DDRSS_PHY_221_DATA + DDRSS_PHY_222_DATA + DDRSS_PHY_223_DATA + DDRSS_PHY_224_DATA + DDRSS_PHY_225_DATA + DDRSS_PHY_226_DATA + DDRSS_PHY_227_DATA + DDRSS_PHY_228_DATA + DDRSS_PHY_229_DATA + DDRSS_PHY_230_DATA + DDRSS_PHY_231_DATA + DDRSS_PHY_232_DATA + DDRSS_PHY_233_DATA + DDRSS_PHY_234_DATA + DDRSS_PHY_235_DATA + DDRSS_PHY_236_DATA + DDRSS_PHY_237_DATA + DDRSS_PHY_238_DATA + DDRSS_PHY_239_DATA + DDRSS_PHY_240_DATA + DDRSS_PHY_241_DATA + DDRSS_PHY_242_DATA + DDRSS_PHY_243_DATA + DDRSS_PHY_244_DATA + DDRSS_PHY_245_DATA + DDRSS_PHY_246_DATA + DDRSS_PHY_247_DATA + DDRSS_PHY_248_DATA + DDRSS_PHY_249_DATA + DDRSS_PHY_250_DATA + DDRSS_PHY_251_DATA + DDRSS_PHY_252_DATA + DDRSS_PHY_253_DATA + DDRSS_PHY_254_DATA + DDRSS_PHY_255_DATA + DDRSS_PHY_256_DATA + DDRSS_PHY_257_DATA + DDRSS_PHY_258_DATA + DDRSS_PHY_259_DATA + DDRSS_PHY_260_DATA + DDRSS_PHY_261_DATA + DDRSS_PHY_262_DATA + DDRSS_PHY_263_DATA + DDRSS_PHY_264_DATA + DDRSS_PHY_265_DATA + DDRSS_PHY_266_DATA + DDRSS_PHY_267_DATA + DDRSS_PHY_268_DATA + DDRSS_PHY_269_DATA + DDRSS_PHY_270_DATA + DDRSS_PHY_271_DATA + DDRSS_PHY_272_DATA + DDRSS_PHY_273_DATA + DDRSS_PHY_274_DATA + DDRSS_PHY_275_DATA + DDRSS_PHY_276_DATA + DDRSS_PHY_277_DATA + DDRSS_PHY_278_DATA + DDRSS_PHY_279_DATA + DDRSS_PHY_280_DATA + DDRSS_PHY_281_DATA + DDRSS_PHY_282_DATA + DDRSS_PHY_283_DATA + DDRSS_PHY_284_DATA + DDRSS_PHY_285_DATA + DDRSS_PHY_286_DATA + DDRSS_PHY_287_DATA + DDRSS_PHY_288_DATA + DDRSS_PHY_289_DATA + DDRSS_PHY_290_DATA + DDRSS_PHY_291_DATA + DDRSS_PHY_292_DATA + DDRSS_PHY_293_DATA + DDRSS_PHY_294_DATA + DDRSS_PHY_295_DATA + DDRSS_PHY_296_DATA + DDRSS_PHY_297_DATA + DDRSS_PHY_298_DATA + DDRSS_PHY_299_DATA + DDRSS_PHY_300_DATA + DDRSS_PHY_301_DATA + DDRSS_PHY_302_DATA + DDRSS_PHY_303_DATA + DDRSS_PHY_304_DATA + DDRSS_PHY_305_DATA + DDRSS_PHY_306_DATA + DDRSS_PHY_307_DATA + DDRSS_PHY_308_DATA + DDRSS_PHY_309_DATA + DDRSS_PHY_310_DATA + DDRSS_PHY_311_DATA + DDRSS_PHY_312_DATA + DDRSS_PHY_313_DATA + DDRSS_PHY_314_DATA + DDRSS_PHY_315_DATA + DDRSS_PHY_316_DATA + DDRSS_PHY_317_DATA + DDRSS_PHY_318_DATA + DDRSS_PHY_319_DATA + DDRSS_PHY_320_DATA + DDRSS_PHY_321_DATA + DDRSS_PHY_322_DATA + DDRSS_PHY_323_DATA + DDRSS_PHY_324_DATA + DDRSS_PHY_325_DATA + DDRSS_PHY_326_DATA + DDRSS_PHY_327_DATA + DDRSS_PHY_328_DATA + DDRSS_PHY_329_DATA + DDRSS_PHY_330_DATA + DDRSS_PHY_331_DATA + DDRSS_PHY_332_DATA + DDRSS_PHY_333_DATA + DDRSS_PHY_334_DATA + DDRSS_PHY_335_DATA + DDRSS_PHY_336_DATA + DDRSS_PHY_337_DATA + DDRSS_PHY_338_DATA + DDRSS_PHY_339_DATA + DDRSS_PHY_340_DATA + DDRSS_PHY_341_DATA + DDRSS_PHY_342_DATA + DDRSS_PHY_343_DATA + DDRSS_PHY_344_DATA + DDRSS_PHY_345_DATA + DDRSS_PHY_346_DATA + DDRSS_PHY_347_DATA + DDRSS_PHY_348_DATA + DDRSS_PHY_349_DATA + DDRSS_PHY_350_DATA + DDRSS_PHY_351_DATA + DDRSS_PHY_352_DATA + DDRSS_PHY_353_DATA + DDRSS_PHY_354_DATA + DDRSS_PHY_355_DATA + DDRSS_PHY_356_DATA + DDRSS_PHY_357_DATA + DDRSS_PHY_358_DATA + DDRSS_PHY_359_DATA + DDRSS_PHY_360_DATA + DDRSS_PHY_361_DATA + DDRSS_PHY_362_DATA + DDRSS_PHY_363_DATA + DDRSS_PHY_364_DATA + DDRSS_PHY_365_DATA + DDRSS_PHY_366_DATA + DDRSS_PHY_367_DATA + DDRSS_PHY_368_DATA + DDRSS_PHY_369_DATA + DDRSS_PHY_370_DATA + DDRSS_PHY_371_DATA + DDRSS_PHY_372_DATA + DDRSS_PHY_373_DATA + DDRSS_PHY_374_DATA + DDRSS_PHY_375_DATA + DDRSS_PHY_376_DATA + DDRSS_PHY_377_DATA + DDRSS_PHY_378_DATA + DDRSS_PHY_379_DATA + DDRSS_PHY_380_DATA + DDRSS_PHY_381_DATA + DDRSS_PHY_382_DATA + DDRSS_PHY_383_DATA + DDRSS_PHY_384_DATA + DDRSS_PHY_385_DATA + DDRSS_PHY_386_DATA + DDRSS_PHY_387_DATA + DDRSS_PHY_388_DATA + DDRSS_PHY_389_DATA + DDRSS_PHY_390_DATA + DDRSS_PHY_391_DATA + DDRSS_PHY_392_DATA + DDRSS_PHY_393_DATA + DDRSS_PHY_394_DATA + DDRSS_PHY_395_DATA + DDRSS_PHY_396_DATA + DDRSS_PHY_397_DATA + DDRSS_PHY_398_DATA + DDRSS_PHY_399_DATA + DDRSS_PHY_400_DATA + DDRSS_PHY_401_DATA + DDRSS_PHY_402_DATA + DDRSS_PHY_403_DATA + DDRSS_PHY_404_DATA + DDRSS_PHY_405_DATA + DDRSS_PHY_406_DATA + DDRSS_PHY_407_DATA + DDRSS_PHY_408_DATA + DDRSS_PHY_409_DATA + DDRSS_PHY_410_DATA + DDRSS_PHY_411_DATA + DDRSS_PHY_412_DATA + DDRSS_PHY_413_DATA + DDRSS_PHY_414_DATA + DDRSS_PHY_415_DATA + DDRSS_PHY_416_DATA + DDRSS_PHY_417_DATA + DDRSS_PHY_418_DATA + DDRSS_PHY_419_DATA + DDRSS_PHY_420_DATA + DDRSS_PHY_421_DATA + DDRSS_PHY_422_DATA + DDRSS_PHY_423_DATA + DDRSS_PHY_424_DATA + DDRSS_PHY_425_DATA + DDRSS_PHY_426_DATA + DDRSS_PHY_427_DATA + DDRSS_PHY_428_DATA + DDRSS_PHY_429_DATA + DDRSS_PHY_430_DATA + DDRSS_PHY_431_DATA + DDRSS_PHY_432_DATA + DDRSS_PHY_433_DATA + DDRSS_PHY_434_DATA + DDRSS_PHY_435_DATA + DDRSS_PHY_436_DATA + DDRSS_PHY_437_DATA + DDRSS_PHY_438_DATA + DDRSS_PHY_439_DATA + DDRSS_PHY_440_DATA + DDRSS_PHY_441_DATA + DDRSS_PHY_442_DATA + DDRSS_PHY_443_DATA + DDRSS_PHY_444_DATA + DDRSS_PHY_445_DATA + DDRSS_PHY_446_DATA + DDRSS_PHY_447_DATA + DDRSS_PHY_448_DATA + DDRSS_PHY_449_DATA + DDRSS_PHY_450_DATA + DDRSS_PHY_451_DATA + DDRSS_PHY_452_DATA + DDRSS_PHY_453_DATA + DDRSS_PHY_454_DATA + DDRSS_PHY_455_DATA + DDRSS_PHY_456_DATA + DDRSS_PHY_457_DATA + DDRSS_PHY_458_DATA + DDRSS_PHY_459_DATA + DDRSS_PHY_460_DATA + DDRSS_PHY_461_DATA + DDRSS_PHY_462_DATA + DDRSS_PHY_463_DATA + DDRSS_PHY_464_DATA + DDRSS_PHY_465_DATA + DDRSS_PHY_466_DATA + DDRSS_PHY_467_DATA + DDRSS_PHY_468_DATA + DDRSS_PHY_469_DATA + DDRSS_PHY_470_DATA + DDRSS_PHY_471_DATA + DDRSS_PHY_472_DATA + DDRSS_PHY_473_DATA + DDRSS_PHY_474_DATA + DDRSS_PHY_475_DATA + DDRSS_PHY_476_DATA + DDRSS_PHY_477_DATA + DDRSS_PHY_478_DATA + DDRSS_PHY_479_DATA + DDRSS_PHY_480_DATA + DDRSS_PHY_481_DATA + DDRSS_PHY_482_DATA + DDRSS_PHY_483_DATA + DDRSS_PHY_484_DATA + DDRSS_PHY_485_DATA + DDRSS_PHY_486_DATA + DDRSS_PHY_487_DATA + DDRSS_PHY_488_DATA + DDRSS_PHY_489_DATA + DDRSS_PHY_490_DATA + DDRSS_PHY_491_DATA + DDRSS_PHY_492_DATA + DDRSS_PHY_493_DATA + DDRSS_PHY_494_DATA + DDRSS_PHY_495_DATA + DDRSS_PHY_496_DATA + DDRSS_PHY_497_DATA + DDRSS_PHY_498_DATA + DDRSS_PHY_499_DATA + DDRSS_PHY_500_DATA + DDRSS_PHY_501_DATA + DDRSS_PHY_502_DATA + DDRSS_PHY_503_DATA + DDRSS_PHY_504_DATA + DDRSS_PHY_505_DATA + DDRSS_PHY_506_DATA + DDRSS_PHY_507_DATA + DDRSS_PHY_508_DATA + DDRSS_PHY_509_DATA + DDRSS_PHY_510_DATA + DDRSS_PHY_511_DATA + DDRSS_PHY_512_DATA + DDRSS_PHY_513_DATA + DDRSS_PHY_514_DATA + DDRSS_PHY_515_DATA + DDRSS_PHY_516_DATA + DDRSS_PHY_517_DATA + DDRSS_PHY_518_DATA + DDRSS_PHY_519_DATA + DDRSS_PHY_520_DATA + DDRSS_PHY_521_DATA + DDRSS_PHY_522_DATA + DDRSS_PHY_523_DATA + DDRSS_PHY_524_DATA + DDRSS_PHY_525_DATA + DDRSS_PHY_526_DATA + DDRSS_PHY_527_DATA + DDRSS_PHY_528_DATA + DDRSS_PHY_529_DATA + DDRSS_PHY_530_DATA + DDRSS_PHY_531_DATA + DDRSS_PHY_532_DATA + DDRSS_PHY_533_DATA + DDRSS_PHY_534_DATA + DDRSS_PHY_535_DATA + DDRSS_PHY_536_DATA + DDRSS_PHY_537_DATA + DDRSS_PHY_538_DATA + DDRSS_PHY_539_DATA + DDRSS_PHY_540_DATA + DDRSS_PHY_541_DATA + DDRSS_PHY_542_DATA + DDRSS_PHY_543_DATA + DDRSS_PHY_544_DATA + DDRSS_PHY_545_DATA + DDRSS_PHY_546_DATA + DDRSS_PHY_547_DATA + DDRSS_PHY_548_DATA + DDRSS_PHY_549_DATA + DDRSS_PHY_550_DATA + DDRSS_PHY_551_DATA + DDRSS_PHY_552_DATA + DDRSS_PHY_553_DATA + DDRSS_PHY_554_DATA + DDRSS_PHY_555_DATA + DDRSS_PHY_556_DATA + DDRSS_PHY_557_DATA + DDRSS_PHY_558_DATA + DDRSS_PHY_559_DATA + DDRSS_PHY_560_DATA + DDRSS_PHY_561_DATA + DDRSS_PHY_562_DATA + DDRSS_PHY_563_DATA + DDRSS_PHY_564_DATA + DDRSS_PHY_565_DATA + DDRSS_PHY_566_DATA + DDRSS_PHY_567_DATA + DDRSS_PHY_568_DATA + DDRSS_PHY_569_DATA + DDRSS_PHY_570_DATA + DDRSS_PHY_571_DATA + DDRSS_PHY_572_DATA + DDRSS_PHY_573_DATA + DDRSS_PHY_574_DATA + DDRSS_PHY_575_DATA + DDRSS_PHY_576_DATA + DDRSS_PHY_577_DATA + DDRSS_PHY_578_DATA + DDRSS_PHY_579_DATA + DDRSS_PHY_580_DATA + DDRSS_PHY_581_DATA + DDRSS_PHY_582_DATA + DDRSS_PHY_583_DATA + DDRSS_PHY_584_DATA + DDRSS_PHY_585_DATA + DDRSS_PHY_586_DATA + DDRSS_PHY_587_DATA + DDRSS_PHY_588_DATA + DDRSS_PHY_589_DATA + DDRSS_PHY_590_DATA + DDRSS_PHY_591_DATA + DDRSS_PHY_592_DATA + DDRSS_PHY_593_DATA + DDRSS_PHY_594_DATA + DDRSS_PHY_595_DATA + DDRSS_PHY_596_DATA + DDRSS_PHY_597_DATA + DDRSS_PHY_598_DATA + DDRSS_PHY_599_DATA + DDRSS_PHY_600_DATA + DDRSS_PHY_601_DATA + DDRSS_PHY_602_DATA + DDRSS_PHY_603_DATA + DDRSS_PHY_604_DATA + DDRSS_PHY_605_DATA + DDRSS_PHY_606_DATA + DDRSS_PHY_607_DATA + DDRSS_PHY_608_DATA + DDRSS_PHY_609_DATA + DDRSS_PHY_610_DATA + DDRSS_PHY_611_DATA + DDRSS_PHY_612_DATA + DDRSS_PHY_613_DATA + DDRSS_PHY_614_DATA + DDRSS_PHY_615_DATA + DDRSS_PHY_616_DATA + DDRSS_PHY_617_DATA + DDRSS_PHY_618_DATA + DDRSS_PHY_619_DATA + DDRSS_PHY_620_DATA + DDRSS_PHY_621_DATA + DDRSS_PHY_622_DATA + DDRSS_PHY_623_DATA + DDRSS_PHY_624_DATA + DDRSS_PHY_625_DATA + DDRSS_PHY_626_DATA + DDRSS_PHY_627_DATA + DDRSS_PHY_628_DATA + DDRSS_PHY_629_DATA + DDRSS_PHY_630_DATA + DDRSS_PHY_631_DATA + DDRSS_PHY_632_DATA + DDRSS_PHY_633_DATA + DDRSS_PHY_634_DATA + DDRSS_PHY_635_DATA + DDRSS_PHY_636_DATA + DDRSS_PHY_637_DATA + DDRSS_PHY_638_DATA + DDRSS_PHY_639_DATA + DDRSS_PHY_640_DATA + DDRSS_PHY_641_DATA + DDRSS_PHY_642_DATA + DDRSS_PHY_643_DATA + DDRSS_PHY_644_DATA + DDRSS_PHY_645_DATA + DDRSS_PHY_646_DATA + DDRSS_PHY_647_DATA + DDRSS_PHY_648_DATA + DDRSS_PHY_649_DATA + DDRSS_PHY_650_DATA + DDRSS_PHY_651_DATA + DDRSS_PHY_652_DATA + DDRSS_PHY_653_DATA + DDRSS_PHY_654_DATA + DDRSS_PHY_655_DATA + DDRSS_PHY_656_DATA + DDRSS_PHY_657_DATA + DDRSS_PHY_658_DATA + DDRSS_PHY_659_DATA + DDRSS_PHY_660_DATA + DDRSS_PHY_661_DATA + DDRSS_PHY_662_DATA + DDRSS_PHY_663_DATA + DDRSS_PHY_664_DATA + DDRSS_PHY_665_DATA + DDRSS_PHY_666_DATA + DDRSS_PHY_667_DATA + DDRSS_PHY_668_DATA + DDRSS_PHY_669_DATA + DDRSS_PHY_670_DATA + DDRSS_PHY_671_DATA + DDRSS_PHY_672_DATA + DDRSS_PHY_673_DATA + DDRSS_PHY_674_DATA + DDRSS_PHY_675_DATA + DDRSS_PHY_676_DATA + DDRSS_PHY_677_DATA + DDRSS_PHY_678_DATA + DDRSS_PHY_679_DATA + DDRSS_PHY_680_DATA + DDRSS_PHY_681_DATA + DDRSS_PHY_682_DATA + DDRSS_PHY_683_DATA + DDRSS_PHY_684_DATA + DDRSS_PHY_685_DATA + DDRSS_PHY_686_DATA + DDRSS_PHY_687_DATA + DDRSS_PHY_688_DATA + DDRSS_PHY_689_DATA + DDRSS_PHY_690_DATA + DDRSS_PHY_691_DATA + DDRSS_PHY_692_DATA + DDRSS_PHY_693_DATA + DDRSS_PHY_694_DATA + DDRSS_PHY_695_DATA + DDRSS_PHY_696_DATA + DDRSS_PHY_697_DATA + DDRSS_PHY_698_DATA + DDRSS_PHY_699_DATA + DDRSS_PHY_700_DATA + DDRSS_PHY_701_DATA + DDRSS_PHY_702_DATA + DDRSS_PHY_703_DATA + DDRSS_PHY_704_DATA + DDRSS_PHY_705_DATA + DDRSS_PHY_706_DATA + DDRSS_PHY_707_DATA + DDRSS_PHY_708_DATA + DDRSS_PHY_709_DATA + DDRSS_PHY_710_DATA + DDRSS_PHY_711_DATA + DDRSS_PHY_712_DATA + DDRSS_PHY_713_DATA + DDRSS_PHY_714_DATA + DDRSS_PHY_715_DATA + DDRSS_PHY_716_DATA + DDRSS_PHY_717_DATA + DDRSS_PHY_718_DATA + DDRSS_PHY_719_DATA + DDRSS_PHY_720_DATA + DDRSS_PHY_721_DATA + DDRSS_PHY_722_DATA + DDRSS_PHY_723_DATA + DDRSS_PHY_724_DATA + DDRSS_PHY_725_DATA + DDRSS_PHY_726_DATA + DDRSS_PHY_727_DATA + DDRSS_PHY_728_DATA + DDRSS_PHY_729_DATA + DDRSS_PHY_730_DATA + DDRSS_PHY_731_DATA + DDRSS_PHY_732_DATA + DDRSS_PHY_733_DATA + DDRSS_PHY_734_DATA + DDRSS_PHY_735_DATA + DDRSS_PHY_736_DATA + DDRSS_PHY_737_DATA + DDRSS_PHY_738_DATA + DDRSS_PHY_739_DATA + DDRSS_PHY_740_DATA + DDRSS_PHY_741_DATA + DDRSS_PHY_742_DATA + DDRSS_PHY_743_DATA + DDRSS_PHY_744_DATA + DDRSS_PHY_745_DATA + DDRSS_PHY_746_DATA + DDRSS_PHY_747_DATA + DDRSS_PHY_748_DATA + DDRSS_PHY_749_DATA + DDRSS_PHY_750_DATA + DDRSS_PHY_751_DATA + DDRSS_PHY_752_DATA + DDRSS_PHY_753_DATA + DDRSS_PHY_754_DATA + DDRSS_PHY_755_DATA + DDRSS_PHY_756_DATA + DDRSS_PHY_757_DATA + DDRSS_PHY_758_DATA + DDRSS_PHY_759_DATA + DDRSS_PHY_760_DATA + DDRSS_PHY_761_DATA + DDRSS_PHY_762_DATA + DDRSS_PHY_763_DATA + DDRSS_PHY_764_DATA + DDRSS_PHY_765_DATA + DDRSS_PHY_766_DATA + DDRSS_PHY_767_DATA + DDRSS_PHY_768_DATA + DDRSS_PHY_769_DATA + DDRSS_PHY_770_DATA + DDRSS_PHY_771_DATA + DDRSS_PHY_772_DATA + DDRSS_PHY_773_DATA + DDRSS_PHY_774_DATA + DDRSS_PHY_775_DATA + DDRSS_PHY_776_DATA + DDRSS_PHY_777_DATA + DDRSS_PHY_778_DATA + DDRSS_PHY_779_DATA + DDRSS_PHY_780_DATA + DDRSS_PHY_781_DATA + DDRSS_PHY_782_DATA + DDRSS_PHY_783_DATA + DDRSS_PHY_784_DATA + DDRSS_PHY_785_DATA + DDRSS_PHY_786_DATA + DDRSS_PHY_787_DATA + DDRSS_PHY_788_DATA + DDRSS_PHY_789_DATA + DDRSS_PHY_790_DATA + DDRSS_PHY_791_DATA + DDRSS_PHY_792_DATA + DDRSS_PHY_793_DATA + DDRSS_PHY_794_DATA + DDRSS_PHY_795_DATA + DDRSS_PHY_796_DATA + DDRSS_PHY_797_DATA + DDRSS_PHY_798_DATA + DDRSS_PHY_799_DATA + DDRSS_PHY_800_DATA + DDRSS_PHY_801_DATA + DDRSS_PHY_802_DATA + DDRSS_PHY_803_DATA + DDRSS_PHY_804_DATA + DDRSS_PHY_805_DATA + DDRSS_PHY_806_DATA + DDRSS_PHY_807_DATA + DDRSS_PHY_808_DATA + DDRSS_PHY_809_DATA + DDRSS_PHY_810_DATA + DDRSS_PHY_811_DATA + DDRSS_PHY_812_DATA + DDRSS_PHY_813_DATA + DDRSS_PHY_814_DATA + DDRSS_PHY_815_DATA + DDRSS_PHY_816_DATA + DDRSS_PHY_817_DATA + DDRSS_PHY_818_DATA + DDRSS_PHY_819_DATA + DDRSS_PHY_820_DATA + DDRSS_PHY_821_DATA + DDRSS_PHY_822_DATA + DDRSS_PHY_823_DATA + DDRSS_PHY_824_DATA + DDRSS_PHY_825_DATA + DDRSS_PHY_826_DATA + DDRSS_PHY_827_DATA + DDRSS_PHY_828_DATA + DDRSS_PHY_829_DATA + DDRSS_PHY_830_DATA + DDRSS_PHY_831_DATA + DDRSS_PHY_832_DATA + DDRSS_PHY_833_DATA + DDRSS_PHY_834_DATA + DDRSS_PHY_835_DATA + DDRSS_PHY_836_DATA + DDRSS_PHY_837_DATA + DDRSS_PHY_838_DATA + DDRSS_PHY_839_DATA + DDRSS_PHY_840_DATA + DDRSS_PHY_841_DATA + DDRSS_PHY_842_DATA + DDRSS_PHY_843_DATA + DDRSS_PHY_844_DATA + DDRSS_PHY_845_DATA + DDRSS_PHY_846_DATA + DDRSS_PHY_847_DATA + DDRSS_PHY_848_DATA + DDRSS_PHY_849_DATA + DDRSS_PHY_850_DATA + DDRSS_PHY_851_DATA + DDRSS_PHY_852_DATA + DDRSS_PHY_853_DATA + DDRSS_PHY_854_DATA + DDRSS_PHY_855_DATA + DDRSS_PHY_856_DATA + DDRSS_PHY_857_DATA + DDRSS_PHY_858_DATA + DDRSS_PHY_859_DATA + DDRSS_PHY_860_DATA + DDRSS_PHY_861_DATA + DDRSS_PHY_862_DATA + DDRSS_PHY_863_DATA + DDRSS_PHY_864_DATA + DDRSS_PHY_865_DATA + DDRSS_PHY_866_DATA + DDRSS_PHY_867_DATA + DDRSS_PHY_868_DATA + DDRSS_PHY_869_DATA + DDRSS_PHY_870_DATA + DDRSS_PHY_871_DATA + DDRSS_PHY_872_DATA + DDRSS_PHY_873_DATA + DDRSS_PHY_874_DATA + DDRSS_PHY_875_DATA + DDRSS_PHY_876_DATA + DDRSS_PHY_877_DATA + DDRSS_PHY_878_DATA + DDRSS_PHY_879_DATA + DDRSS_PHY_880_DATA + DDRSS_PHY_881_DATA + DDRSS_PHY_882_DATA + DDRSS_PHY_883_DATA + DDRSS_PHY_884_DATA + DDRSS_PHY_885_DATA + DDRSS_PHY_886_DATA + DDRSS_PHY_887_DATA + DDRSS_PHY_888_DATA + DDRSS_PHY_889_DATA + DDRSS_PHY_890_DATA + DDRSS_PHY_891_DATA + DDRSS_PHY_892_DATA + DDRSS_PHY_893_DATA + DDRSS_PHY_894_DATA + DDRSS_PHY_895_DATA + DDRSS_PHY_896_DATA + DDRSS_PHY_897_DATA + DDRSS_PHY_898_DATA + DDRSS_PHY_899_DATA + DDRSS_PHY_900_DATA + DDRSS_PHY_901_DATA + DDRSS_PHY_902_DATA + DDRSS_PHY_903_DATA + DDRSS_PHY_904_DATA + DDRSS_PHY_905_DATA + DDRSS_PHY_906_DATA + DDRSS_PHY_907_DATA + DDRSS_PHY_908_DATA + DDRSS_PHY_909_DATA + DDRSS_PHY_910_DATA + DDRSS_PHY_911_DATA + DDRSS_PHY_912_DATA + DDRSS_PHY_913_DATA + DDRSS_PHY_914_DATA + DDRSS_PHY_915_DATA + DDRSS_PHY_916_DATA + DDRSS_PHY_917_DATA + DDRSS_PHY_918_DATA + DDRSS_PHY_919_DATA + DDRSS_PHY_920_DATA + DDRSS_PHY_921_DATA + DDRSS_PHY_922_DATA + DDRSS_PHY_923_DATA + DDRSS_PHY_924_DATA + DDRSS_PHY_925_DATA + DDRSS_PHY_926_DATA + DDRSS_PHY_927_DATA + DDRSS_PHY_928_DATA + DDRSS_PHY_929_DATA + DDRSS_PHY_930_DATA + DDRSS_PHY_931_DATA + DDRSS_PHY_932_DATA + DDRSS_PHY_933_DATA + DDRSS_PHY_934_DATA + DDRSS_PHY_935_DATA + DDRSS_PHY_936_DATA + DDRSS_PHY_937_DATA + DDRSS_PHY_938_DATA + DDRSS_PHY_939_DATA + DDRSS_PHY_940_DATA + DDRSS_PHY_941_DATA + DDRSS_PHY_942_DATA + DDRSS_PHY_943_DATA + DDRSS_PHY_944_DATA + DDRSS_PHY_945_DATA + DDRSS_PHY_946_DATA + DDRSS_PHY_947_DATA + DDRSS_PHY_948_DATA + DDRSS_PHY_949_DATA + DDRSS_PHY_950_DATA + DDRSS_PHY_951_DATA + DDRSS_PHY_952_DATA + DDRSS_PHY_953_DATA + DDRSS_PHY_954_DATA + DDRSS_PHY_955_DATA + DDRSS_PHY_956_DATA + DDRSS_PHY_957_DATA + DDRSS_PHY_958_DATA + DDRSS_PHY_959_DATA + DDRSS_PHY_960_DATA + DDRSS_PHY_961_DATA + DDRSS_PHY_962_DATA + DDRSS_PHY_963_DATA + DDRSS_PHY_964_DATA + DDRSS_PHY_965_DATA + DDRSS_PHY_966_DATA + DDRSS_PHY_967_DATA + DDRSS_PHY_968_DATA + DDRSS_PHY_969_DATA + DDRSS_PHY_970_DATA + DDRSS_PHY_971_DATA + DDRSS_PHY_972_DATA + DDRSS_PHY_973_DATA + DDRSS_PHY_974_DATA + DDRSS_PHY_975_DATA + DDRSS_PHY_976_DATA + DDRSS_PHY_977_DATA + DDRSS_PHY_978_DATA + DDRSS_PHY_979_DATA + DDRSS_PHY_980_DATA + DDRSS_PHY_981_DATA + DDRSS_PHY_982_DATA + DDRSS_PHY_983_DATA + DDRSS_PHY_984_DATA + DDRSS_PHY_985_DATA + DDRSS_PHY_986_DATA + DDRSS_PHY_987_DATA + DDRSS_PHY_988_DATA + DDRSS_PHY_989_DATA + DDRSS_PHY_990_DATA + DDRSS_PHY_991_DATA + DDRSS_PHY_992_DATA + DDRSS_PHY_993_DATA + DDRSS_PHY_994_DATA + DDRSS_PHY_995_DATA + DDRSS_PHY_996_DATA + DDRSS_PHY_997_DATA + DDRSS_PHY_998_DATA + DDRSS_PHY_999_DATA + DDRSS_PHY_1000_DATA + DDRSS_PHY_1001_DATA + DDRSS_PHY_1002_DATA + DDRSS_PHY_1003_DATA + DDRSS_PHY_1004_DATA + DDRSS_PHY_1005_DATA + DDRSS_PHY_1006_DATA + DDRSS_PHY_1007_DATA + DDRSS_PHY_1008_DATA + DDRSS_PHY_1009_DATA + DDRSS_PHY_1010_DATA + DDRSS_PHY_1011_DATA + DDRSS_PHY_1012_DATA + DDRSS_PHY_1013_DATA + DDRSS_PHY_1014_DATA + DDRSS_PHY_1015_DATA + DDRSS_PHY_1016_DATA + DDRSS_PHY_1017_DATA + DDRSS_PHY_1018_DATA + DDRSS_PHY_1019_DATA + DDRSS_PHY_1020_DATA + DDRSS_PHY_1021_DATA + DDRSS_PHY_1022_DATA + DDRSS_PHY_1023_DATA + DDRSS_PHY_1024_DATA + DDRSS_PHY_1025_DATA + DDRSS_PHY_1026_DATA + DDRSS_PHY_1027_DATA + DDRSS_PHY_1028_DATA + DDRSS_PHY_1029_DATA + DDRSS_PHY_1030_DATA + DDRSS_PHY_1031_DATA + DDRSS_PHY_1032_DATA + DDRSS_PHY_1033_DATA + DDRSS_PHY_1034_DATA + DDRSS_PHY_1035_DATA + DDRSS_PHY_1036_DATA + DDRSS_PHY_1037_DATA + DDRSS_PHY_1038_DATA + DDRSS_PHY_1039_DATA + DDRSS_PHY_1040_DATA + DDRSS_PHY_1041_DATA + DDRSS_PHY_1042_DATA + DDRSS_PHY_1043_DATA + DDRSS_PHY_1044_DATA + DDRSS_PHY_1045_DATA + DDRSS_PHY_1046_DATA + DDRSS_PHY_1047_DATA + DDRSS_PHY_1048_DATA + DDRSS_PHY_1049_DATA + DDRSS_PHY_1050_DATA + DDRSS_PHY_1051_DATA + DDRSS_PHY_1052_DATA + DDRSS_PHY_1053_DATA + DDRSS_PHY_1054_DATA + DDRSS_PHY_1055_DATA + DDRSS_PHY_1056_DATA + DDRSS_PHY_1057_DATA + DDRSS_PHY_1058_DATA + DDRSS_PHY_1059_DATA + DDRSS_PHY_1060_DATA + DDRSS_PHY_1061_DATA + DDRSS_PHY_1062_DATA + DDRSS_PHY_1063_DATA + DDRSS_PHY_1064_DATA + DDRSS_PHY_1065_DATA + DDRSS_PHY_1066_DATA + DDRSS_PHY_1067_DATA + DDRSS_PHY_1068_DATA + DDRSS_PHY_1069_DATA + DDRSS_PHY_1070_DATA + DDRSS_PHY_1071_DATA + DDRSS_PHY_1072_DATA + DDRSS_PHY_1073_DATA + DDRSS_PHY_1074_DATA + DDRSS_PHY_1075_DATA + DDRSS_PHY_1076_DATA + DDRSS_PHY_1077_DATA + DDRSS_PHY_1078_DATA + DDRSS_PHY_1079_DATA + DDRSS_PHY_1080_DATA + DDRSS_PHY_1081_DATA + DDRSS_PHY_1082_DATA + DDRSS_PHY_1083_DATA + DDRSS_PHY_1084_DATA + DDRSS_PHY_1085_DATA + DDRSS_PHY_1086_DATA + DDRSS_PHY_1087_DATA + DDRSS_PHY_1088_DATA + DDRSS_PHY_1089_DATA + DDRSS_PHY_1090_DATA + DDRSS_PHY_1091_DATA + DDRSS_PHY_1092_DATA + DDRSS_PHY_1093_DATA + DDRSS_PHY_1094_DATA + DDRSS_PHY_1095_DATA + DDRSS_PHY_1096_DATA + DDRSS_PHY_1097_DATA + DDRSS_PHY_1098_DATA + DDRSS_PHY_1099_DATA + DDRSS_PHY_1100_DATA + DDRSS_PHY_1101_DATA + DDRSS_PHY_1102_DATA + DDRSS_PHY_1103_DATA + DDRSS_PHY_1104_DATA + DDRSS_PHY_1105_DATA + DDRSS_PHY_1106_DATA + DDRSS_PHY_1107_DATA + DDRSS_PHY_1108_DATA + DDRSS_PHY_1109_DATA + DDRSS_PHY_1110_DATA + DDRSS_PHY_1111_DATA + DDRSS_PHY_1112_DATA + DDRSS_PHY_1113_DATA + DDRSS_PHY_1114_DATA + DDRSS_PHY_1115_DATA + DDRSS_PHY_1116_DATA + DDRSS_PHY_1117_DATA + DDRSS_PHY_1118_DATA + DDRSS_PHY_1119_DATA + DDRSS_PHY_1120_DATA + DDRSS_PHY_1121_DATA + DDRSS_PHY_1122_DATA + DDRSS_PHY_1123_DATA + DDRSS_PHY_1124_DATA + DDRSS_PHY_1125_DATA + DDRSS_PHY_1126_DATA + DDRSS_PHY_1127_DATA + DDRSS_PHY_1128_DATA + DDRSS_PHY_1129_DATA + DDRSS_PHY_1130_DATA + DDRSS_PHY_1131_DATA + DDRSS_PHY_1132_DATA + DDRSS_PHY_1133_DATA + DDRSS_PHY_1134_DATA + DDRSS_PHY_1135_DATA + DDRSS_PHY_1136_DATA + DDRSS_PHY_1137_DATA + DDRSS_PHY_1138_DATA + DDRSS_PHY_1139_DATA + DDRSS_PHY_1140_DATA + DDRSS_PHY_1141_DATA + DDRSS_PHY_1142_DATA + DDRSS_PHY_1143_DATA + DDRSS_PHY_1144_DATA + DDRSS_PHY_1145_DATA + DDRSS_PHY_1146_DATA + DDRSS_PHY_1147_DATA + DDRSS_PHY_1148_DATA + DDRSS_PHY_1149_DATA + DDRSS_PHY_1150_DATA + DDRSS_PHY_1151_DATA + DDRSS_PHY_1152_DATA + DDRSS_PHY_1153_DATA + DDRSS_PHY_1154_DATA + DDRSS_PHY_1155_DATA + DDRSS_PHY_1156_DATA + DDRSS_PHY_1157_DATA + DDRSS_PHY_1158_DATA + DDRSS_PHY_1159_DATA + DDRSS_PHY_1160_DATA + DDRSS_PHY_1161_DATA + DDRSS_PHY_1162_DATA + DDRSS_PHY_1163_DATA + DDRSS_PHY_1164_DATA + DDRSS_PHY_1165_DATA + DDRSS_PHY_1166_DATA + DDRSS_PHY_1167_DATA + DDRSS_PHY_1168_DATA + DDRSS_PHY_1169_DATA + DDRSS_PHY_1170_DATA + DDRSS_PHY_1171_DATA + DDRSS_PHY_1172_DATA + DDRSS_PHY_1173_DATA + DDRSS_PHY_1174_DATA + DDRSS_PHY_1175_DATA + DDRSS_PHY_1176_DATA + DDRSS_PHY_1177_DATA + DDRSS_PHY_1178_DATA + DDRSS_PHY_1179_DATA + DDRSS_PHY_1180_DATA + DDRSS_PHY_1181_DATA + DDRSS_PHY_1182_DATA + DDRSS_PHY_1183_DATA + DDRSS_PHY_1184_DATA + DDRSS_PHY_1185_DATA + DDRSS_PHY_1186_DATA + DDRSS_PHY_1187_DATA + DDRSS_PHY_1188_DATA + DDRSS_PHY_1189_DATA + DDRSS_PHY_1190_DATA + DDRSS_PHY_1191_DATA + DDRSS_PHY_1192_DATA + DDRSS_PHY_1193_DATA + DDRSS_PHY_1194_DATA + DDRSS_PHY_1195_DATA + DDRSS_PHY_1196_DATA + DDRSS_PHY_1197_DATA + DDRSS_PHY_1198_DATA + DDRSS_PHY_1199_DATA + DDRSS_PHY_1200_DATA + DDRSS_PHY_1201_DATA + DDRSS_PHY_1202_DATA + DDRSS_PHY_1203_DATA + DDRSS_PHY_1204_DATA + DDRSS_PHY_1205_DATA + DDRSS_PHY_1206_DATA + DDRSS_PHY_1207_DATA + DDRSS_PHY_1208_DATA + DDRSS_PHY_1209_DATA + DDRSS_PHY_1210_DATA + DDRSS_PHY_1211_DATA + DDRSS_PHY_1212_DATA + DDRSS_PHY_1213_DATA + DDRSS_PHY_1214_DATA + DDRSS_PHY_1215_DATA + DDRSS_PHY_1216_DATA + DDRSS_PHY_1217_DATA + DDRSS_PHY_1218_DATA + DDRSS_PHY_1219_DATA + DDRSS_PHY_1220_DATA + DDRSS_PHY_1221_DATA + DDRSS_PHY_1222_DATA + DDRSS_PHY_1223_DATA + DDRSS_PHY_1224_DATA + DDRSS_PHY_1225_DATA + DDRSS_PHY_1226_DATA + DDRSS_PHY_1227_DATA + DDRSS_PHY_1228_DATA + DDRSS_PHY_1229_DATA + DDRSS_PHY_1230_DATA + DDRSS_PHY_1231_DATA + DDRSS_PHY_1232_DATA + DDRSS_PHY_1233_DATA + DDRSS_PHY_1234_DATA + DDRSS_PHY_1235_DATA + DDRSS_PHY_1236_DATA + DDRSS_PHY_1237_DATA + DDRSS_PHY_1238_DATA + DDRSS_PHY_1239_DATA + DDRSS_PHY_1240_DATA + DDRSS_PHY_1241_DATA + DDRSS_PHY_1242_DATA + DDRSS_PHY_1243_DATA + DDRSS_PHY_1244_DATA + DDRSS_PHY_1245_DATA + DDRSS_PHY_1246_DATA + DDRSS_PHY_1247_DATA + DDRSS_PHY_1248_DATA + DDRSS_PHY_1249_DATA + DDRSS_PHY_1250_DATA + DDRSS_PHY_1251_DATA + DDRSS_PHY_1252_DATA + DDRSS_PHY_1253_DATA + DDRSS_PHY_1254_DATA + DDRSS_PHY_1255_DATA + DDRSS_PHY_1256_DATA + DDRSS_PHY_1257_DATA + DDRSS_PHY_1258_DATA + DDRSS_PHY_1259_DATA + DDRSS_PHY_1260_DATA + DDRSS_PHY_1261_DATA + DDRSS_PHY_1262_DATA + DDRSS_PHY_1263_DATA + DDRSS_PHY_1264_DATA + DDRSS_PHY_1265_DATA + DDRSS_PHY_1266_DATA + DDRSS_PHY_1267_DATA + DDRSS_PHY_1268_DATA + DDRSS_PHY_1269_DATA + DDRSS_PHY_1270_DATA + DDRSS_PHY_1271_DATA + DDRSS_PHY_1272_DATA + DDRSS_PHY_1273_DATA + DDRSS_PHY_1274_DATA + DDRSS_PHY_1275_DATA + DDRSS_PHY_1276_DATA + DDRSS_PHY_1277_DATA + DDRSS_PHY_1278_DATA + DDRSS_PHY_1279_DATA + DDRSS_PHY_1280_DATA + DDRSS_PHY_1281_DATA + DDRSS_PHY_1282_DATA + DDRSS_PHY_1283_DATA + DDRSS_PHY_1284_DATA + DDRSS_PHY_1285_DATA + DDRSS_PHY_1286_DATA + DDRSS_PHY_1287_DATA + DDRSS_PHY_1288_DATA + DDRSS_PHY_1289_DATA + DDRSS_PHY_1290_DATA + DDRSS_PHY_1291_DATA + DDRSS_PHY_1292_DATA + DDRSS_PHY_1293_DATA + DDRSS_PHY_1294_DATA + DDRSS_PHY_1295_DATA + DDRSS_PHY_1296_DATA + DDRSS_PHY_1297_DATA + DDRSS_PHY_1298_DATA + DDRSS_PHY_1299_DATA + DDRSS_PHY_1300_DATA + DDRSS_PHY_1301_DATA + DDRSS_PHY_1302_DATA + DDRSS_PHY_1303_DATA + DDRSS_PHY_1304_DATA + DDRSS_PHY_1305_DATA + DDRSS_PHY_1306_DATA + DDRSS_PHY_1307_DATA + DDRSS_PHY_1308_DATA + DDRSS_PHY_1309_DATA + DDRSS_PHY_1310_DATA + DDRSS_PHY_1311_DATA + DDRSS_PHY_1312_DATA + DDRSS_PHY_1313_DATA + DDRSS_PHY_1314_DATA + DDRSS_PHY_1315_DATA + DDRSS_PHY_1316_DATA + DDRSS_PHY_1317_DATA + DDRSS_PHY_1318_DATA + DDRSS_PHY_1319_DATA + DDRSS_PHY_1320_DATA + DDRSS_PHY_1321_DATA + DDRSS_PHY_1322_DATA + DDRSS_PHY_1323_DATA + DDRSS_PHY_1324_DATA + DDRSS_PHY_1325_DATA + DDRSS_PHY_1326_DATA + DDRSS_PHY_1327_DATA + DDRSS_PHY_1328_DATA + DDRSS_PHY_1329_DATA + DDRSS_PHY_1330_DATA + DDRSS_PHY_1331_DATA + DDRSS_PHY_1332_DATA + DDRSS_PHY_1333_DATA + DDRSS_PHY_1334_DATA + DDRSS_PHY_1335_DATA + DDRSS_PHY_1336_DATA + DDRSS_PHY_1337_DATA + DDRSS_PHY_1338_DATA + DDRSS_PHY_1339_DATA + DDRSS_PHY_1340_DATA + DDRSS_PHY_1341_DATA + DDRSS_PHY_1342_DATA + DDRSS_PHY_1343_DATA + DDRSS_PHY_1344_DATA + DDRSS_PHY_1345_DATA + DDRSS_PHY_1346_DATA + DDRSS_PHY_1347_DATA + DDRSS_PHY_1348_DATA + DDRSS_PHY_1349_DATA + DDRSS_PHY_1350_DATA + DDRSS_PHY_1351_DATA + DDRSS_PHY_1352_DATA + DDRSS_PHY_1353_DATA + DDRSS_PHY_1354_DATA + DDRSS_PHY_1355_DATA + DDRSS_PHY_1356_DATA + DDRSS_PHY_1357_DATA + DDRSS_PHY_1358_DATA + DDRSS_PHY_1359_DATA + DDRSS_PHY_1360_DATA + DDRSS_PHY_1361_DATA + DDRSS_PHY_1362_DATA + DDRSS_PHY_1363_DATA + DDRSS_PHY_1364_DATA + DDRSS_PHY_1365_DATA + DDRSS_PHY_1366_DATA + DDRSS_PHY_1367_DATA + DDRSS_PHY_1368_DATA + DDRSS_PHY_1369_DATA + DDRSS_PHY_1370_DATA + DDRSS_PHY_1371_DATA + DDRSS_PHY_1372_DATA + DDRSS_PHY_1373_DATA + DDRSS_PHY_1374_DATA + DDRSS_PHY_1375_DATA + DDRSS_PHY_1376_DATA + DDRSS_PHY_1377_DATA + DDRSS_PHY_1378_DATA + DDRSS_PHY_1379_DATA + DDRSS_PHY_1380_DATA + DDRSS_PHY_1381_DATA + DDRSS_PHY_1382_DATA + DDRSS_PHY_1383_DATA + DDRSS_PHY_1384_DATA + DDRSS_PHY_1385_DATA + DDRSS_PHY_1386_DATA + DDRSS_PHY_1387_DATA + DDRSS_PHY_1388_DATA + DDRSS_PHY_1389_DATA + DDRSS_PHY_1390_DATA + DDRSS_PHY_1391_DATA + DDRSS_PHY_1392_DATA + DDRSS_PHY_1393_DATA + DDRSS_PHY_1394_DATA + DDRSS_PHY_1395_DATA + DDRSS_PHY_1396_DATA + DDRSS_PHY_1397_DATA + DDRSS_PHY_1398_DATA + DDRSS_PHY_1399_DATA + DDRSS_PHY_1400_DATA + DDRSS_PHY_1401_DATA + DDRSS_PHY_1402_DATA + DDRSS_PHY_1403_DATA + DDRSS_PHY_1404_DATA + DDRSS_PHY_1405_DATA + DDRSS_PHY_1406_DATA + DDRSS_PHY_1407_DATA + DDRSS_PHY_1408_DATA + DDRSS_PHY_1409_DATA + DDRSS_PHY_1410_DATA + DDRSS_PHY_1411_DATA + DDRSS_PHY_1412_DATA + DDRSS_PHY_1413_DATA + DDRSS_PHY_1414_DATA + DDRSS_PHY_1415_DATA + DDRSS_PHY_1416_DATA + DDRSS_PHY_1417_DATA + DDRSS_PHY_1418_DATA + DDRSS_PHY_1419_DATA + DDRSS_PHY_1420_DATA + DDRSS_PHY_1421_DATA + DDRSS_PHY_1422_DATA + DDRSS_PHY_1423_DATA + DDRSS_PHY_1424_DATA + DDRSS_PHY_1425_DATA + DDRSS_PHY_1426_DATA + DDRSS_PHY_1427_DATA + DDRSS_PHY_1428_DATA + DDRSS_PHY_1429_DATA + DDRSS_PHY_1430_DATA + DDRSS_PHY_1431_DATA + DDRSS_PHY_1432_DATA + DDRSS_PHY_1433_DATA + DDRSS_PHY_1434_DATA + DDRSS_PHY_1435_DATA + DDRSS_PHY_1436_DATA + DDRSS_PHY_1437_DATA + DDRSS_PHY_1438_DATA + DDRSS_PHY_1439_DATA + DDRSS_PHY_1440_DATA + DDRSS_PHY_1441_DATA + DDRSS_PHY_1442_DATA + DDRSS_PHY_1443_DATA + DDRSS_PHY_1444_DATA + DDRSS_PHY_1445_DATA + DDRSS_PHY_1446_DATA + DDRSS_PHY_1447_DATA + DDRSS_PHY_1448_DATA + DDRSS_PHY_1449_DATA + DDRSS_PHY_1450_DATA + DDRSS_PHY_1451_DATA + DDRSS_PHY_1452_DATA + DDRSS_PHY_1453_DATA + DDRSS_PHY_1454_DATA + DDRSS_PHY_1455_DATA + DDRSS_PHY_1456_DATA + DDRSS_PHY_1457_DATA + DDRSS_PHY_1458_DATA + DDRSS_PHY_1459_DATA + DDRSS_PHY_1460_DATA + DDRSS_PHY_1461_DATA + DDRSS_PHY_1462_DATA + DDRSS_PHY_1463_DATA + DDRSS_PHY_1464_DATA + DDRSS_PHY_1465_DATA + DDRSS_PHY_1466_DATA + DDRSS_PHY_1467_DATA + DDRSS_PHY_1468_DATA + DDRSS_PHY_1469_DATA + DDRSS_PHY_1470_DATA + DDRSS_PHY_1471_DATA + DDRSS_PHY_1472_DATA + DDRSS_PHY_1473_DATA + DDRSS_PHY_1474_DATA + DDRSS_PHY_1475_DATA + DDRSS_PHY_1476_DATA + DDRSS_PHY_1477_DATA + DDRSS_PHY_1478_DATA + DDRSS_PHY_1479_DATA + DDRSS_PHY_1480_DATA + DDRSS_PHY_1481_DATA + DDRSS_PHY_1482_DATA + DDRSS_PHY_1483_DATA + DDRSS_PHY_1484_DATA + DDRSS_PHY_1485_DATA + DDRSS_PHY_1486_DATA + DDRSS_PHY_1487_DATA + DDRSS_PHY_1488_DATA + DDRSS_PHY_1489_DATA + DDRSS_PHY_1490_DATA + DDRSS_PHY_1491_DATA + DDRSS_PHY_1492_DATA + DDRSS_PHY_1493_DATA + DDRSS_PHY_1494_DATA + DDRSS_PHY_1495_DATA + DDRSS_PHY_1496_DATA + DDRSS_PHY_1497_DATA + DDRSS_PHY_1498_DATA + DDRSS_PHY_1499_DATA + DDRSS_PHY_1500_DATA + DDRSS_PHY_1501_DATA + DDRSS_PHY_1502_DATA + DDRSS_PHY_1503_DATA + DDRSS_PHY_1504_DATA + DDRSS_PHY_1505_DATA + DDRSS_PHY_1506_DATA + DDRSS_PHY_1507_DATA + DDRSS_PHY_1508_DATA + DDRSS_PHY_1509_DATA + DDRSS_PHY_1510_DATA + DDRSS_PHY_1511_DATA + DDRSS_PHY_1512_DATA + DDRSS_PHY_1513_DATA + DDRSS_PHY_1514_DATA + DDRSS_PHY_1515_DATA + DDRSS_PHY_1516_DATA + DDRSS_PHY_1517_DATA + DDRSS_PHY_1518_DATA + DDRSS_PHY_1519_DATA + DDRSS_PHY_1520_DATA + DDRSS_PHY_1521_DATA + DDRSS_PHY_1522_DATA + DDRSS_PHY_1523_DATA + DDRSS_PHY_1524_DATA + DDRSS_PHY_1525_DATA + DDRSS_PHY_1526_DATA + DDRSS_PHY_1527_DATA + DDRSS_PHY_1528_DATA + DDRSS_PHY_1529_DATA + DDRSS_PHY_1530_DATA + DDRSS_PHY_1531_DATA + DDRSS_PHY_1532_DATA + DDRSS_PHY_1533_DATA + DDRSS_PHY_1534_DATA + DDRSS_PHY_1535_DATA + DDRSS_PHY_1536_DATA + DDRSS_PHY_1537_DATA + DDRSS_PHY_1538_DATA + DDRSS_PHY_1539_DATA + DDRSS_PHY_1540_DATA + DDRSS_PHY_1541_DATA + DDRSS_PHY_1542_DATA + DDRSS_PHY_1543_DATA + DDRSS_PHY_1544_DATA + DDRSS_PHY_1545_DATA + DDRSS_PHY_1546_DATA + DDRSS_PHY_1547_DATA + DDRSS_PHY_1548_DATA + DDRSS_PHY_1549_DATA + DDRSS_PHY_1550_DATA + DDRSS_PHY_1551_DATA + DDRSS_PHY_1552_DATA + DDRSS_PHY_1553_DATA + DDRSS_PHY_1554_DATA + DDRSS_PHY_1555_DATA + DDRSS_PHY_1556_DATA + DDRSS_PHY_1557_DATA + DDRSS_PHY_1558_DATA + DDRSS_PHY_1559_DATA + DDRSS_PHY_1560_DATA + DDRSS_PHY_1561_DATA + DDRSS_PHY_1562_DATA + DDRSS_PHY_1563_DATA + DDRSS_PHY_1564_DATA + DDRSS_PHY_1565_DATA + DDRSS_PHY_1566_DATA + DDRSS_PHY_1567_DATA + DDRSS_PHY_1568_DATA + DDRSS_PHY_1569_DATA + DDRSS_PHY_1570_DATA + DDRSS_PHY_1571_DATA + DDRSS_PHY_1572_DATA + DDRSS_PHY_1573_DATA + DDRSS_PHY_1574_DATA + DDRSS_PHY_1575_DATA + DDRSS_PHY_1576_DATA + DDRSS_PHY_1577_DATA + DDRSS_PHY_1578_DATA + DDRSS_PHY_1579_DATA + DDRSS_PHY_1580_DATA + DDRSS_PHY_1581_DATA + DDRSS_PHY_1582_DATA + DDRSS_PHY_1583_DATA + DDRSS_PHY_1584_DATA + DDRSS_PHY_1585_DATA + DDRSS_PHY_1586_DATA + DDRSS_PHY_1587_DATA + DDRSS_PHY_1588_DATA + DDRSS_PHY_1589_DATA + DDRSS_PHY_1590_DATA + DDRSS_PHY_1591_DATA + DDRSS_PHY_1592_DATA + DDRSS_PHY_1593_DATA + DDRSS_PHY_1594_DATA + DDRSS_PHY_1595_DATA + DDRSS_PHY_1596_DATA + DDRSS_PHY_1597_DATA + DDRSS_PHY_1598_DATA + DDRSS_PHY_1599_DATA + DDRSS_PHY_1600_DATA + DDRSS_PHY_1601_DATA + DDRSS_PHY_1602_DATA + DDRSS_PHY_1603_DATA + DDRSS_PHY_1604_DATA + DDRSS_PHY_1605_DATA + DDRSS_PHY_1606_DATA + DDRSS_PHY_1607_DATA + DDRSS_PHY_1608_DATA + DDRSS_PHY_1609_DATA + DDRSS_PHY_1610_DATA + DDRSS_PHY_1611_DATA + DDRSS_PHY_1612_DATA + DDRSS_PHY_1613_DATA + DDRSS_PHY_1614_DATA + DDRSS_PHY_1615_DATA + DDRSS_PHY_1616_DATA + DDRSS_PHY_1617_DATA + DDRSS_PHY_1618_DATA + DDRSS_PHY_1619_DATA + DDRSS_PHY_1620_DATA + DDRSS_PHY_1621_DATA + DDRSS_PHY_1622_DATA + DDRSS_PHY_1623_DATA + DDRSS_PHY_1624_DATA + DDRSS_PHY_1625_DATA + DDRSS_PHY_1626_DATA + DDRSS_PHY_1627_DATA + DDRSS_PHY_1628_DATA + DDRSS_PHY_1629_DATA + DDRSS_PHY_1630_DATA + DDRSS_PHY_1631_DATA + DDRSS_PHY_1632_DATA + DDRSS_PHY_1633_DATA + DDRSS_PHY_1634_DATA + DDRSS_PHY_1635_DATA + DDRSS_PHY_1636_DATA + DDRSS_PHY_1637_DATA + DDRSS_PHY_1638_DATA + DDRSS_PHY_1639_DATA + DDRSS_PHY_1640_DATA + DDRSS_PHY_1641_DATA + DDRSS_PHY_1642_DATA + DDRSS_PHY_1643_DATA + DDRSS_PHY_1644_DATA + DDRSS_PHY_1645_DATA + DDRSS_PHY_1646_DATA + DDRSS_PHY_1647_DATA + DDRSS_PHY_1648_DATA + DDRSS_PHY_1649_DATA + DDRSS_PHY_1650_DATA + DDRSS_PHY_1651_DATA + DDRSS_PHY_1652_DATA + DDRSS_PHY_1653_DATA + DDRSS_PHY_1654_DATA + DDRSS_PHY_1655_DATA + DDRSS_PHY_1656_DATA + DDRSS_PHY_1657_DATA + DDRSS_PHY_1658_DATA + DDRSS_PHY_1659_DATA + DDRSS_PHY_1660_DATA + DDRSS_PHY_1661_DATA + DDRSS_PHY_1662_DATA + DDRSS_PHY_1663_DATA + DDRSS_PHY_1664_DATA + DDRSS_PHY_1665_DATA + DDRSS_PHY_1666_DATA + DDRSS_PHY_1667_DATA + DDRSS_PHY_1668_DATA + DDRSS_PHY_1669_DATA + DDRSS_PHY_1670_DATA + DDRSS_PHY_1671_DATA + DDRSS_PHY_1672_DATA + DDRSS_PHY_1673_DATA + DDRSS_PHY_1674_DATA + DDRSS_PHY_1675_DATA + DDRSS_PHY_1676_DATA + DDRSS_PHY_1677_DATA + DDRSS_PHY_1678_DATA + DDRSS_PHY_1679_DATA + DDRSS_PHY_1680_DATA + DDRSS_PHY_1681_DATA + DDRSS_PHY_1682_DATA + DDRSS_PHY_1683_DATA + DDRSS_PHY_1684_DATA + DDRSS_PHY_1685_DATA + DDRSS_PHY_1686_DATA + DDRSS_PHY_1687_DATA + DDRSS_PHY_1688_DATA + DDRSS_PHY_1689_DATA + DDRSS_PHY_1690_DATA + DDRSS_PHY_1691_DATA + DDRSS_PHY_1692_DATA + DDRSS_PHY_1693_DATA + DDRSS_PHY_1694_DATA + DDRSS_PHY_1695_DATA + DDRSS_PHY_1696_DATA + DDRSS_PHY_1697_DATA + DDRSS_PHY_1698_DATA + DDRSS_PHY_1699_DATA + DDRSS_PHY_1700_DATA + DDRSS_PHY_1701_DATA + DDRSS_PHY_1702_DATA + DDRSS_PHY_1703_DATA + DDRSS_PHY_1704_DATA + DDRSS_PHY_1705_DATA + DDRSS_PHY_1706_DATA + DDRSS_PHY_1707_DATA + DDRSS_PHY_1708_DATA + DDRSS_PHY_1709_DATA + DDRSS_PHY_1710_DATA + DDRSS_PHY_1711_DATA + DDRSS_PHY_1712_DATA + DDRSS_PHY_1713_DATA + DDRSS_PHY_1714_DATA + DDRSS_PHY_1715_DATA + DDRSS_PHY_1716_DATA + DDRSS_PHY_1717_DATA + DDRSS_PHY_1718_DATA + DDRSS_PHY_1719_DATA + DDRSS_PHY_1720_DATA + DDRSS_PHY_1721_DATA + DDRSS_PHY_1722_DATA + DDRSS_PHY_1723_DATA + DDRSS_PHY_1724_DATA + DDRSS_PHY_1725_DATA + DDRSS_PHY_1726_DATA + DDRSS_PHY_1727_DATA + DDRSS_PHY_1728_DATA + DDRSS_PHY_1729_DATA + DDRSS_PHY_1730_DATA + DDRSS_PHY_1731_DATA + DDRSS_PHY_1732_DATA + DDRSS_PHY_1733_DATA + DDRSS_PHY_1734_DATA + DDRSS_PHY_1735_DATA + DDRSS_PHY_1736_DATA + DDRSS_PHY_1737_DATA + DDRSS_PHY_1738_DATA + DDRSS_PHY_1739_DATA + DDRSS_PHY_1740_DATA + DDRSS_PHY_1741_DATA + DDRSS_PHY_1742_DATA + DDRSS_PHY_1743_DATA + DDRSS_PHY_1744_DATA + DDRSS_PHY_1745_DATA + DDRSS_PHY_1746_DATA + DDRSS_PHY_1747_DATA + DDRSS_PHY_1748_DATA + DDRSS_PHY_1749_DATA + DDRSS_PHY_1750_DATA + DDRSS_PHY_1751_DATA + DDRSS_PHY_1752_DATA + DDRSS_PHY_1753_DATA + DDRSS_PHY_1754_DATA + DDRSS_PHY_1755_DATA + DDRSS_PHY_1756_DATA + DDRSS_PHY_1757_DATA + DDRSS_PHY_1758_DATA + DDRSS_PHY_1759_DATA + DDRSS_PHY_1760_DATA + DDRSS_PHY_1761_DATA + DDRSS_PHY_1762_DATA + DDRSS_PHY_1763_DATA + DDRSS_PHY_1764_DATA + DDRSS_PHY_1765_DATA + DDRSS_PHY_1766_DATA + DDRSS_PHY_1767_DATA + DDRSS_PHY_1768_DATA + DDRSS_PHY_1769_DATA + DDRSS_PHY_1770_DATA + DDRSS_PHY_1771_DATA + DDRSS_PHY_1772_DATA + DDRSS_PHY_1773_DATA + DDRSS_PHY_1774_DATA + DDRSS_PHY_1775_DATA + DDRSS_PHY_1776_DATA + DDRSS_PHY_1777_DATA + DDRSS_PHY_1778_DATA + DDRSS_PHY_1779_DATA + DDRSS_PHY_1780_DATA + DDRSS_PHY_1781_DATA + DDRSS_PHY_1782_DATA + DDRSS_PHY_1783_DATA + DDRSS_PHY_1784_DATA + DDRSS_PHY_1785_DATA + DDRSS_PHY_1786_DATA + DDRSS_PHY_1787_DATA + DDRSS_PHY_1788_DATA + DDRSS_PHY_1789_DATA + DDRSS_PHY_1790_DATA + DDRSS_PHY_1791_DATA + DDRSS_PHY_1792_DATA + DDRSS_PHY_1793_DATA + DDRSS_PHY_1794_DATA + DDRSS_PHY_1795_DATA + DDRSS_PHY_1796_DATA + DDRSS_PHY_1797_DATA + DDRSS_PHY_1798_DATA + DDRSS_PHY_1799_DATA + DDRSS_PHY_1800_DATA + DDRSS_PHY_1801_DATA + DDRSS_PHY_1802_DATA + DDRSS_PHY_1803_DATA + DDRSS_PHY_1804_DATA + DDRSS_PHY_1805_DATA + DDRSS_PHY_1806_DATA + DDRSS_PHY_1807_DATA + DDRSS_PHY_1808_DATA + DDRSS_PHY_1809_DATA + DDRSS_PHY_1810_DATA + DDRSS_PHY_1811_DATA + DDRSS_PHY_1812_DATA + DDRSS_PHY_1813_DATA + DDRSS_PHY_1814_DATA + DDRSS_PHY_1815_DATA + DDRSS_PHY_1816_DATA + DDRSS_PHY_1817_DATA + DDRSS_PHY_1818_DATA + DDRSS_PHY_1819_DATA + DDRSS_PHY_1820_DATA + DDRSS_PHY_1821_DATA + DDRSS_PHY_1822_DATA + DDRSS_PHY_1823_DATA + DDRSS_PHY_1824_DATA + DDRSS_PHY_1825_DATA + DDRSS_PHY_1826_DATA + DDRSS_PHY_1827_DATA + DDRSS_PHY_1828_DATA + DDRSS_PHY_1829_DATA + DDRSS_PHY_1830_DATA + DDRSS_PHY_1831_DATA + DDRSS_PHY_1832_DATA + DDRSS_PHY_1833_DATA + DDRSS_PHY_1834_DATA + DDRSS_PHY_1835_DATA + DDRSS_PHY_1836_DATA + DDRSS_PHY_1837_DATA + DDRSS_PHY_1838_DATA + DDRSS_PHY_1839_DATA + DDRSS_PHY_1840_DATA + DDRSS_PHY_1841_DATA + DDRSS_PHY_1842_DATA + DDRSS_PHY_1843_DATA + DDRSS_PHY_1844_DATA + DDRSS_PHY_1845_DATA + DDRSS_PHY_1846_DATA + DDRSS_PHY_1847_DATA + DDRSS_PHY_1848_DATA + DDRSS_PHY_1849_DATA + DDRSS_PHY_1850_DATA + DDRSS_PHY_1851_DATA + DDRSS_PHY_1852_DATA + DDRSS_PHY_1853_DATA + DDRSS_PHY_1854_DATA + DDRSS_PHY_1855_DATA + DDRSS_PHY_1856_DATA + DDRSS_PHY_1857_DATA + DDRSS_PHY_1858_DATA + DDRSS_PHY_1859_DATA + DDRSS_PHY_1860_DATA + DDRSS_PHY_1861_DATA + DDRSS_PHY_1862_DATA + DDRSS_PHY_1863_DATA + DDRSS_PHY_1864_DATA + DDRSS_PHY_1865_DATA + DDRSS_PHY_1866_DATA + DDRSS_PHY_1867_DATA + DDRSS_PHY_1868_DATA + DDRSS_PHY_1869_DATA + DDRSS_PHY_1870_DATA + DDRSS_PHY_1871_DATA + DDRSS_PHY_1872_DATA + DDRSS_PHY_1873_DATA + DDRSS_PHY_1874_DATA + DDRSS_PHY_1875_DATA + DDRSS_PHY_1876_DATA + DDRSS_PHY_1877_DATA + DDRSS_PHY_1878_DATA + DDRSS_PHY_1879_DATA + DDRSS_PHY_1880_DATA + DDRSS_PHY_1881_DATA + DDRSS_PHY_1882_DATA + DDRSS_PHY_1883_DATA + DDRSS_PHY_1884_DATA + DDRSS_PHY_1885_DATA + DDRSS_PHY_1886_DATA + DDRSS_PHY_1887_DATA + DDRSS_PHY_1888_DATA + DDRSS_PHY_1889_DATA + DDRSS_PHY_1890_DATA + DDRSS_PHY_1891_DATA + DDRSS_PHY_1892_DATA + DDRSS_PHY_1893_DATA + DDRSS_PHY_1894_DATA + DDRSS_PHY_1895_DATA + DDRSS_PHY_1896_DATA + DDRSS_PHY_1897_DATA + DDRSS_PHY_1898_DATA + DDRSS_PHY_1899_DATA + DDRSS_PHY_1900_DATA + DDRSS_PHY_1901_DATA + DDRSS_PHY_1902_DATA + DDRSS_PHY_1903_DATA + DDRSS_PHY_1904_DATA + DDRSS_PHY_1905_DATA + DDRSS_PHY_1906_DATA + DDRSS_PHY_1907_DATA + DDRSS_PHY_1908_DATA + DDRSS_PHY_1909_DATA + DDRSS_PHY_1910_DATA + DDRSS_PHY_1911_DATA + DDRSS_PHY_1912_DATA + DDRSS_PHY_1913_DATA + DDRSS_PHY_1914_DATA + DDRSS_PHY_1915_DATA + DDRSS_PHY_1916_DATA + DDRSS_PHY_1917_DATA + DDRSS_PHY_1918_DATA + DDRSS_PHY_1919_DATA + DDRSS_PHY_1920_DATA + DDRSS_PHY_1921_DATA + DDRSS_PHY_1922_DATA + DDRSS_PHY_1923_DATA + >; + }; +}; diff --git a/arch/arm/dts/k3-am62a-main.dtsi b/arch/arm/dts/k3-am62a-main.dtsi new file mode 100644 index 0000000000..bc4b50bcd1 --- /dev/null +++ b/arch/arm/dts/k3-am62a-main.dtsi @@ -0,0 +1,298 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for AM62A SoC Family Main Domain peripherals + * + * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ + */ + +&cbass_main { + oc_sram: sram@70000000 { + compatible = "mmio-sram"; + reg = <0x00 0x70000000 0x00 0x10000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x00 0x70000000 0x10000>; + }; + + gic500: interrupt-controller@1800000 { + compatible = "arm,gic-v3"; + reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */ + <0x00 0x01880000 0x00 0xc0000>, /* GICR */ + <0x00 0x01880000 0x00 0xc0000>, /* GICR */ + <0x01 0x00000000 0x00 0x2000>, /* GICC */ + <0x01 0x00010000 0x00 0x1000>, /* GICH */ + <0x01 0x00020000 0x00 0x2000>; /* GICV */ + #address-cells = <2>; + #size-cells = <2>; + ranges; + #interrupt-cells = <3>; + interrupt-controller; + /* + * vcpumntirq: + * virtual CPU interface maintenance interrupt + */ + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; + + gic_its: msi-controller@1820000 { + compatible = "arm,gic-v3-its"; + reg = <0x00 0x01820000 0x00 0x10000>; + socionext,synquacer-pre-its = <0x1000000 0x400000>; + msi-controller; + #msi-cells = <1>; + }; + }; + + main_conf: syscon@100000 { + compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; + reg = <0x00 0x00100000 0x00 0x20000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00 0x00 0x00100000 0x20000>; + }; + + dmss: bus@48000000 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + dma-ranges; + ranges = <0x00 0x48000000 0x00 0x48000000 0x00 0x06000000>; + + ti,sci-dev-id = <25>; + + secure_proxy_main: mailbox@4d000000 { + compatible = "ti,am654-secure-proxy"; + reg = <0x00 0x4d000000 0x00 0x80000>, + <0x00 0x4a600000 0x00 0x80000>, + <0x00 0x4a400000 0x00 0x80000>; + reg-names = "target_data", "rt", "scfg"; + #mbox-cells = <1>; + interrupt-names = "rx_012"; + interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + + dmsc: system-controller@44043000 { + compatible = "ti,k2g-sci"; + reg = <0x00 0x44043000 0x00 0xfe0>; + reg-names = "debug_messages"; + ti,host-id = <12>; + mbox-names = "rx", "tx"; + mboxes= <&secure_proxy_main 12>, + <&secure_proxy_main 13>; + + k3_pds: power-controller { + compatible = "ti,sci-pm-domain"; + #power-domain-cells = <2>; + }; + + k3_clks: clock-controller { + compatible = "ti,k2g-sci-clk"; + #clock-cells = <2>; + }; + + k3_reset: reset-controller { + compatible = "ti,sci-reset"; + #reset-cells = <2>; + }; + }; + + main_pmx0: pinctrl@f4000 { + compatible = "pinctrl-single"; + reg = <0x00 0xf4000 0x00 0x2ac>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0xffffffff>; + }; + + main_uart0: serial@2800000 { + compatible = "ti,am64-uart", "ti,am654-uart"; + reg = <0x00 0x02800000 0x00 0x100>; + interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 146 0>; + clock-names = "fclk"; + status = "disabled"; + }; + + main_uart1: serial@2810000 { + compatible = "ti,am64-uart", "ti,am654-uart"; + reg = <0x00 0x02810000 0x00 0x100>; + interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 152 0>; + clock-names = "fclk"; + status = "disabled"; + }; + + main_uart2: serial@2820000 { + compatible = "ti,am64-uart", "ti,am654-uart"; + reg = <0x00 0x02820000 0x00 0x100>; + interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 153 0>; + clock-names = "fclk"; + status = "disabled"; + }; + + main_uart3: serial@2830000 { + compatible = "ti,am64-uart", "ti,am654-uart"; + reg = <0x00 0x02830000 0x00 0x100>; + interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 154 0>; + clock-names = "fclk"; + status = "disabled"; + }; + + main_uart4: serial@2840000 { + compatible = "ti,am64-uart", "ti,am654-uart"; + reg = <0x00 0x02840000 0x00 0x100>; + interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&k3_pds 155 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 155 0>; + clock-names = "fclk"; + status = "disabled"; + }; + + main_uart5: serial@2850000 { + compatible = "ti,am64-uart", "ti,am654-uart"; + reg = <0x00 0x02850000 0x00 0x100>; + interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&k3_pds 156 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 156 0>; + clock-names = "fclk"; + status = "disabled"; + }; + + main_uart6: serial@2860000 { + compatible = "ti,am64-uart", "ti,am654-uart"; + reg = <0x00 0x02860000 0x00 0x100>; + interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 158 0>; + clock-names = "fclk"; + status = "disabled"; + }; + + main_i2c0: i2c@20000000 { + compatible = "ti,am64-i2c", "ti,omap4-i2c"; + reg = <0x00 0x20000000 0x00 0x100>; + interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 102 2>; + clock-names = "fck"; + status = "disabled"; + }; + + main_i2c1: i2c@20010000 { + compatible = "ti,am64-i2c", "ti,omap4-i2c"; + reg = <0x00 0x20010000 0x00 0x100>; + interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 103 2>; + clock-names = "fck"; + status = "disabled"; + }; + + main_i2c2: i2c@20020000 { + compatible = "ti,am64-i2c", "ti,omap4-i2c"; + reg = <0x00 0x20020000 0x00 0x100>; + interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 104 2>; + clock-names = "fck"; + status = "disabled"; + }; + + main_i2c3: i2c@20030000 { + compatible = "ti,am64-i2c", "ti,omap4-i2c"; + reg = <0x00 0x20030000 0x00 0x100>; + interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 105 2>; + clock-names = "fck"; + status = "disabled"; + }; + + main_gpio_intr: interrupt-controller@a00000 { + compatible = "ti,sci-intr"; + reg = <0x00 0x00a00000 0x00 0x800>; + ti,intr-trigger-type = <1>; + interrupt-controller; + interrupt-parent = <&gic500>; + #interrupt-cells = <1>; + ti,sci = <&dmsc>; + ti,sci-dev-id = <3>; + ti,interrupt-ranges = <0 32 16>; + status = "disabled"; + }; + + main_gpio0: gpio@600000 { + compatible = "ti,am64-gpio", "ti,keystone-gpio"; + reg = <0x00 0x00600000 0x0 0x100>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&main_gpio_intr>; + interrupts = <190>, <191>, <192>, + <193>, <194>, <195>; + interrupt-controller; + #interrupt-cells = <2>; + ti,ngpio = <87>; + ti,davinci-gpio-unbanked = <0>; + power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 77 0>; + clock-names = "gpio"; + status = "disabled"; + }; + + main_gpio1: gpio@601000 { + compatible = "ti,am64-gpio", "ti,keystone-gpio"; + reg = <0x00 0x00601000 0x0 0x100>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&main_gpio_intr>; + interrupts = <180>, <181>, <182>, + <183>, <184>, <185>; + interrupt-controller; + #interrupt-cells = <2>; + ti,ngpio = <88>; + ti,davinci-gpio-unbanked = <0>; + power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 78 0>; + clock-names = "gpio"; + status = "disabled"; + }; + + sdhci1: mmc@fa00000 { + compatible = "ti,am62-sdhci"; + reg = <0x00 0xfa00000 0x00 0x260>, <0x00 0xfa08000 0x00 0x134>; + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 58 5>, <&k3_clks 58 6>; + clock-names = "clk_ahb", "clk_xin"; + ti,trm-icp = <0x2>; + ti,otap-del-sel-legacy = <0x0>; + ti,otap-del-sel-sd-hs = <0x0>; + ti,otap-del-sel-sdr12 = <0xf>; + ti,otap-del-sel-sdr25 = <0xf>; + ti,otap-del-sel-sdr50 = <0xc>; + ti,otap-del-sel-sdr104 = <0x6>; + ti,otap-del-sel-ddr50 = <0x9>; + ti,itap-del-sel-legacy = <0x0>; + ti,itap-del-sel-sd-hs = <0x0>; + ti,itap-del-sel-sdr12 = <0x0>; + ti,itap-del-sel-sdr25 = <0x0>; + ti,clkbuf-sel = <0x7>; + bus-width = <4>; + no-1-8-v; + status = "disabled"; + }; +}; diff --git a/arch/arm/dts/k3-am62a-mcu.dtsi b/arch/arm/dts/k3-am62a-mcu.dtsi new file mode 100644 index 0000000000..6d1e501b94 --- /dev/null +++ b/arch/arm/dts/k3-am62a-mcu.dtsi @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for AM625 SoC Family MCU Domain peripherals + * + * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/ + */ + +&cbass_mcu { + mcu_pmx0: pinctrl@4084000 { + compatible = "pinctrl-single"; + reg = <0x00 0x04084000 0x00 0x88>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0xffffffff>; + status = "disabled"; + }; + + mcu_uart0: serial@4a00000 { + compatible = "ti,am64-uart", "ti,am654-uart"; + reg = <0x00 0x04a00000 0x00 0x100>; + interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 149 0>; + clock-names = "fclk"; + status = "disabled"; + }; + + mcu_i2c0: i2c@4900000 { + compatible = "ti,am64-i2c", "ti,omap4-i2c"; + reg = <0x00 0x04900000 0x00 0x100>; + interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 106 2>; + clock-names = "fck"; + status = "disabled"; + }; +}; diff --git a/arch/arm/dts/k3-am62a-wakeup.dtsi b/arch/arm/dts/k3-am62a-wakeup.dtsi new file mode 100644 index 0000000000..99afac40e8 --- /dev/null +++ b/arch/arm/dts/k3-am62a-wakeup.dtsi @@ -0,0 +1,54 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for AM62A SoC Family Wakeup Domain peripherals + * + * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ + */ + +&cbass_wakeup { + wkup_conf: syscon@43000000 { + compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; + reg = <0x00 0x43000000 0x00 0x20000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00 0x00 0x43000000 0x20000>; + + chipid: chipid@14 { + compatible = "ti,am654-chipid"; + reg = <0x14 0x4>; + }; + }; + + wkup_uart0: serial@2b300000 { + compatible = "ti,am64-uart", "ti,am654-uart"; + reg = <0x00 0x2b300000 0x00 0x100>; + interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 114 0>; + clock-names = "fclk"; + status = "disabled"; + }; + + wkup_i2c0: i2c@2b200000 { + compatible = "ti,am64-i2c", "ti,omap4-i2c"; + reg = <0x00 0x02b200000 0x00 0x100>; + interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 107 4>; + clock-names = "fck"; + status = "disabled"; + }; + + wkup_rtc0: rtc@2b1f0000 { + compatible = "ti,am62-rtc"; + reg = <0x00 0x2b1f0000 0x00 0x100>; + interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&k3_clks 117 6> , <&k3_clks 117 0>; + clock-names = "vbus", "osc32k"; + power-domains = <&k3_pds 117 TI_SCI_PD_EXCLUSIVE>; + wakeup-source; + status = "disabled"; + }; +}; diff --git a/arch/arm/dts/k3-am62a.dtsi b/arch/arm/dts/k3-am62a.dtsi new file mode 100644 index 0000000000..6eb87c3f9f --- /dev/null +++ b/arch/arm/dts/k3-am62a.dtsi @@ -0,0 +1,122 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for AM62A SoC Family + * + * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/pinctrl/k3.h> +#include <dt-bindings/soc/ti,sci_pm_domain.h> + +/ { + model = "Texas Instruments K3 AM62A SoC"; + compatible = "ti,am62a7"; + interrupt-parent = <&gic500>; + #address-cells = <2>; + #size-cells = <2>; + + chosen { }; + + firmware { + optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + + psci: psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + }; + + a53_timer0: timer-cl0-cpu0 { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* cntpsirq */ + <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* cntpnsirq */ + <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* cntvirq */ + <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* cnthpirq */ + }; + + pmu: pmu { + compatible = "arm,cortex-a53-pmu"; + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; + }; + + cbass_main: bus@f0000 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + + ranges = <0x00 0x000f0000 0x00 0x000f0000 0x00 0x00030000>, /* Main MMRs */ + <0x00 0x00420000 0x00 0x00420000 0x00 0x00001000>, /* ESM0 */ + <0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */ + <0x00 0x00703000 0x00 0x00703000 0x00 0x00000200>, /* USB0 debug trace */ + <0x00 0x0070c000 0x00 0x0070c000 0x00 0x00000200>, /* USB1 debug trace */ + <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* Timesync router */ + <0x00 0x01000000 0x00 0x01000000 0x00 0x01b28400>, /* First peripheral window */ + <0x00 0x08000000 0x00 0x08000000 0x00 0x00200000>, /* Main CPSW */ + <0x00 0x0e000000 0x00 0x0e000000 0x00 0x01d20000>, /* Second peripheral window */ + <0x00 0x0fd00000 0x00 0x0fd00000 0x00 0x00020000>, /* GPU */ + <0x00 0x20000000 0x00 0x20000000 0x00 0x0a008000>, /* Third peripheral window */ + <0x00 0x30040000 0x00 0x30040000 0x00 0x00080000>, /* PRUSS-M */ + <0x00 0x30101000 0x00 0x30101000 0x00 0x00010100>, /* CSI window */ + <0x00 0x30200000 0x00 0x30200000 0x00 0x00010000>, /* DSS */ + <0x00 0x30210000 0x00 0x30210000 0x00 0x00010000>, /* VPU */ + <0x00 0x31000000 0x00 0x31000000 0x00 0x00050000>, /* USB0 DWC3 Core window */ + <0x00 0x31100000 0x00 0x31100000 0x00 0x00050000>, /* USB1 DWC3 Core window */ + <0x00 0x40900000 0x00 0x40900000 0x00 0x00030000>, /* SA3UL */ + <0x00 0x43600000 0x00 0x43600000 0x00 0x00010000>, /* SA3 sproxy data */ + <0x00 0x44043000 0x00 0x44043000 0x00 0x00000fe0>, /* TI SCI DEBUG */ + <0x00 0x44860000 0x00 0x44860000 0x00 0x00040000>, /* SA3 sproxy config */ + <0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>, /* DMSS */ + <0x00 0x60000000 0x00 0x60000000 0x00 0x08000000>, /* FSS0 DAT1 */ + <0x00 0x70000000 0x00 0x70000000 0x00 0x00010000>, /* OCSRAM */ + <0x00 0x7e000000 0x00 0x7e000000 0x00 0x00100000>, /* C7x_0 */ + <0x01 0x00000000 0x01 0x00000000 0x00 0x00310000>, /* A53 PERIPHBASE */ + <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS0 DAT3 */ + + /* MCU Domain Range */ + <0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>, + <0x00 0x79000000 0x00 0x79000000 0x00 0x00008000>, /* MCU R5 ATCM */ + <0x00 0x79020000 0x00 0x79020000 0x00 0x00008000>, /* MCU R5 BTCM */ + <0x00 0x79100000 0x00 0x79100000 0x00 0x00040000>, /* MCU R5 IRAM0 */ + <0x00 0x79140000 0x00 0x79140000 0x00 0x00040000>, /* MCU R5 IRAM1 */ + + /* Wakeup Domain Range */ + <0x00 0x00b00000 0x00 0x00b00000 0x00 0x00002400>, + <0x00 0x2b000000 0x00 0x2b000000 0x00 0x00300400>, + <0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>, + <0x00 0x78000000 0x00 0x78000000 0x00 0x00008000>, /* DM R5 ATCM */ + <0x00 0x78100000 0x00 0x78100000 0x00 0x00008000>; /* DM R5 BTCM */ + + cbass_mcu: bus@4000000 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>, /* Peripheral window */ + <0x00 0x79000000 0x00 0x79000000 0x00 0x00008000>, /* MCU R5 ATCM */ + <0x00 0x79020000 0x00 0x79020000 0x00 0x00008000>, /* MCU R5 BTCM */ + <0x00 0x79100000 0x00 0x79100000 0x00 0x00040000>, /* MCU IRAM0 */ + <0x00 0x79140000 0x00 0x79140000 0x00 0x00040000>; /* MCU IRAM1 */ + }; + + cbass_wakeup: bus@b00000 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x00 0x00b00000 0x00 0x00b00000 0x00 0x00002400>, /* VTM */ + <0x00 0x2b000000 0x00 0x2b000000 0x00 0x00300400>, /* Peripheral Window */ + <0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>, /* WKUP CTRL MMR */ + <0x00 0x78000000 0x00 0x78000000 0x00 0x00008000>, /* DM R5 ATCM*/ + <0x00 0x78100000 0x00 0x78100000 0x00 0x00008000>; /* DM R5 BTCM*/ + }; + }; +}; + +/* Now include the peripherals for each bus segments */ +#include "k3-am62a-main.dtsi" +#include "k3-am62a-mcu.dtsi" +#include "k3-am62a-wakeup.dtsi" diff --git a/arch/arm/dts/k3-am62a7-r5-sk.dts b/arch/arm/dts/k3-am62a7-r5-sk.dts new file mode 100644 index 0000000000..58b7c8ad05 --- /dev/null +++ b/arch/arm/dts/k3-am62a7-r5-sk.dts @@ -0,0 +1,143 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * AM62A7 SK dts file for R5 SPL + * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#include "k3-am62a7-sk.dts" +#include "k3-am62a-ddr-1866mhz-32bit.dtsi" +#include "k3-am62a-ddr.dtsi" + +#include "k3-am62a7-sk-u-boot.dtsi" + +/ { + aliases { + remoteproc0 = &sysctrler; + remoteproc1 = &a53_0; + serial0 = &wkup_uart0; + serial3 = &main_uart1; + }; + + chosen { + stdout-path = "serial2:115200n8"; + tick-timer = &timer1; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x00000000 0x80000000 0x00000000 0x80000000>; /* 2G RAM */ + u-boot,dm-spl; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + secure_ddr: optee@9e800000 { + reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */ + alignment = <0x1000>; + no-map; + }; + }; + + a53_0: a53@0 { + compatible = "ti,am654-rproc"; + reg = <0x00 0x00a90000 0x00 0x10>; + power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>, + <&k3_pds 135 TI_SCI_PD_EXCLUSIVE>; + resets = <&k3_reset 135 0>; + clocks = <&k3_clks 61 0>; + assigned-clocks = <&k3_clks 61 0>, <&k3_clks 135 0>; + assigned-clock-parents = <&k3_clks 61 2>; + assigned-clock-rates = <200000000>, <1200000000>; + ti,sci = <&dmsc>; + ti,sci-proc-id = <32>; + ti,sci-host-id = <10>; + u-boot,dm-spl; + }; + + dm_tifs: dm-tifs { + compatible = "ti,j721e-dm-sci"; + ti,host-id = <36>; + ti,secure-host; + mbox-names = "rx", "tx"; + mboxes= <&secure_proxy_main 22>, + <&secure_proxy_main 23>; + u-boot,dm-spl; + }; +}; + +&dmsc { + mboxes= <&secure_proxy_main 0>, + <&secure_proxy_main 1>, + <&secure_proxy_main 0>; + mbox-names = "rx", "tx", "notify"; + ti,host-id = <35>; + ti,secure-host; +}; + +&cbass_main { + sa3_secproxy: secproxy@44880000 { + compatible = "ti,am654-secure-proxy"; + #mbox-cells = <1>; + reg = <0x00 0x44880000 0x00 0x20000>, + <0x0 0x44860000 0x0 0x20000>, + <0x0 0x43600000 0x0 0x10000>; + reg-names = "rt", "scfg", "target_data"; + u-boot,dm-spl; + }; + + sysctrler: sysctrler { + compatible = "ti,am654-system-controller"; + mboxes= <&secure_proxy_main 1>, + <&secure_proxy_main 0>, + <&sa3_secproxy 0>; + mbox-names = "tx", "rx", "boot_notify"; + u-boot,dm-spl; + }; +}; + +&mcu_pmx0 { + status = "okay"; + u-boot,dm-spl; + + wkup_uart0_pins_default: wkup-uart0-pins-default { + pinctrl-single,pins = < + AM62X_MCU_IOPAD(0x02c, PIN_INPUT, 0) /* (C6) WKUP_UART0_CTSn */ + AM62X_MCU_IOPAD(0x030, PIN_OUTPUT, 0) /* (A4) WKUP_UART0_RTSn */ + AM62X_MCU_IOPAD(0x024, PIN_INPUT, 0) /* (B4) WKUP_UART0_RXD */ + AM62X_MCU_IOPAD(0x028, PIN_OUTPUT, 0) /* (C5) WKUP_UART0_TXD */ + >; + u-boot,dm-spl; + }; +}; + +&main_pmx0 { + u-boot,dm-spl; + main_uart1_pins_default: main-uart1-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x194, PIN_INPUT, 2) /* (B19) MCASP0_AXR3.UART1_CTSn */ + AM62X_IOPAD(0x198, PIN_OUTPUT, 2) /* (A19) MCASP0_AXR2.UART1_RTSn */ + AM62X_IOPAD(0x1ac, PIN_INPUT, 2) /* (E19) MCASP0_AFSR.UART1_RXD */ + AM62X_IOPAD(0x1b0, PIN_OUTPUT, 2) /* (A20) MCASP0_ACLKR.UART1_TXD */ + >; + u-boot,dm-spl; + }; +}; + +/* WKUP UART0 is used for DM firmware logs */ +&wkup_uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&wkup_uart0_pins_default>; + status = "okay"; + u-boot,dm-spl; +}; + +/* Main UART1 is used for TIFS firmware logs */ +&main_uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&main_uart1_pins_default>; + status = "okay"; + u-boot,dm-spl; +}; diff --git a/arch/arm/dts/k3-am62a7-sk-u-boot.dtsi b/arch/arm/dts/k3-am62a7-sk-u-boot.dtsi new file mode 100644 index 0000000000..7fc749ed70 --- /dev/null +++ b/arch/arm/dts/k3-am62a7-sk-u-boot.dtsi @@ -0,0 +1,140 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Common AM62A EVM dts file for SPLs + * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/ { + chosen { + stdout-path = "serial2:115200n8"; + tick-timer = &timer1; + }; + + memory@80000000 { + u-boot,dm-spl; + }; +}; + +&cbass_main{ + u-boot,dm-spl; + + timer1: timer@2400000 { + compatible = "ti,omap5430-timer"; + reg = <0x00 0x2400000 0x00 0x80>; + ti,timer-alwon; + clock-frequency = <25000000>; + u-boot,dm-spl; + }; +}; + +&dmss { + u-boot,dm-spl; +}; + +&secure_proxy_main { + u-boot,dm-spl; +}; + +&dmsc { + u-boot,dm-spl; +}; + +&k3_pds { + u-boot,dm-spl; +}; + +&k3_clks { + u-boot,dm-spl; +}; + +&k3_reset { + u-boot,dm-spl; +}; + +&wkup_conf { + u-boot,dm-spl; +}; + +&chipid { + u-boot,dm-spl; +}; + +&main_pmx0 { + u-boot,dm-spl; +}; + +&main_uart0 { + u-boot,dm-spl; +}; + +&main_uart0_pins_default { + u-boot,dm-spl; +}; + +&main_uart1 { + u-boot,dm-spl; +}; + +&cbass_mcu { + u-boot,dm-spl; +}; + +&cbass_wakeup { + u-boot,dm-spl; +}; + +&mcu_pmx0 { + u-boot,dm-spl; +}; + +&wkup_uart0 { + u-boot,dm-spl; +}; + +&main_gpio0 { + u-boot,dm-spl; +}; + +&main_i2c0 { + u-boot,dm-spl; +}; + +&main_i2c0_pins_default { + u-boot,dm-spl; +}; + +&main_i2c1 { + u-boot,dm-spl; +}; + +&main_i2c1_pins_default { + u-boot,dm-spl; +}; + +&exp1 { + u-boot,dm-spl; +}; + +&sdhci1 { + u-boot,dm-spl; +}; + +&main_mmc1_pins_default { + u-boot,dm-spl; +}; + +&k3_reset { + u-boot,dm-spl; +}; + +&dmsc { + u-boot,dm-spl; + k3_sysreset: sysreset-controller { + compatible = "ti,sci-sysreset"; + u-boot,dm-spl; + }; +}; + +&vdd_mmc1 { + u-boot,dm-spl; +}; diff --git a/arch/arm/dts/k3-am62a7-sk.dts b/arch/arm/dts/k3-am62a7-sk.dts new file mode 100644 index 0000000000..576dbce80a --- /dev/null +++ b/arch/arm/dts/k3-am62a7-sk.dts @@ -0,0 +1,223 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * AM62A SK: https://www.ti.com/lit/zip/sprr459 + * + * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; + +#include <dt-bindings/leds/common.h> +#include <dt-bindings/gpio/gpio.h> +#include "k3-am62a7.dtsi" + +/ { + compatible = "ti,am62a7-sk", "ti,am62a7"; + model = "Texas Instruments AM62A7 SK"; + + aliases { + serial2 = &main_uart0; + mmc1 = &sdhci1; + }; + + chosen { + stdout-path = "serial2:115200n8"; + }; + + memory@80000000 { + device_type = "memory"; + /* 2G RAM */ + reg = <0x00000000 0x80000000 0x00000000 0x80000000>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + secure_tfa_ddr: tfa@9e780000 { + reg = <0x00 0x9e780000 0x00 0x80000>; + alignment = <0x1000>; + no-map; + }; + + secure_ddr: optee@9e800000 { + reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */ + alignment = <0x1000>; + no-map; + }; + + wkup_r5fss0_core0_memory_region: r5f-dma-memory@9c900000 { + compatible = "shared-dma-pool"; + reg = <0x00 0x9c900000 0x00 0x01e00000>; + no-map; + }; + }; + + vmain_pd: regulator-0 { + /* TPS25750 PD CONTROLLER OUTPUT */ + compatible = "regulator-fixed"; + regulator-name = "vmain_pd"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; + + vcc_5v0: regulator-1 { + /* Output of TPS63070 */ + compatible = "regulator-fixed"; + regulator-name = "vcc_5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vmain_pd>; + regulator-always-on; + regulator-boot-on; + }; + + vcc_3v3_sys: regulator-2 { + /* output of LM5141-Q1 */ + compatible = "regulator-fixed"; + regulator-name = "vcc_3v3_sys"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vmain_pd>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_mmc1: regulator-3 { + /* TPS22918DBVR */ + compatible = "regulator-fixed"; + regulator-name = "vdd_mmc1"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + enable-active-high; + gpio = <&exp1 3 GPIO_ACTIVE_HIGH>; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&usr_led_pins_default>; + + led-0 { + label = "am62a-sk:green:heartbeat"; + gpios = <&main_gpio1 49 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + function = LED_FUNCTION_HEARTBEAT; + default-state = "off"; + }; + }; +}; + +&main_pmx0 { + main_uart0_pins_default: main-uart0-pins-default { + pinctrl-single,pins = < + AM62AX_IOPAD(0x1c8, PIN_INPUT, 0) /* (D14) UART0_RXD */ + AM62AX_IOPAD(0x1cc, PIN_OUTPUT, 0) /* (E14) UART0_TXD */ + >; + }; + + main_i2c0_pins_default: main-i2c0-pins-default { + pinctrl-single,pins = < + AM62AX_IOPAD(0x1e0, PIN_INPUT_PULLUP, 0) /* (B16) I2C0_SCL */ + AM62AX_IOPAD(0x1e4, PIN_INPUT_PULLUP, 0) /* (A16) I2C0_SDA */ + >; + }; + + main_i2c1_pins_default: main-i2c1-pins-default { + pinctrl-single,pins = < + AM62AX_IOPAD(0x1e8, PIN_INPUT_PULLUP, 0) /* (B17) I2C1_SCL */ + AM62AX_IOPAD(0x1ec, PIN_INPUT_PULLUP, 0) /* (A17) I2C1_SDA */ + >; + }; + + main_i2c2_pins_default: main-i2c2-pins-default { + pinctrl-single,pins = < + AM62AX_IOPAD(0x0b0, PIN_INPUT_PULLUP, 1) /* (K22) GPMC0_CSn2.I2C2_SCL */ + AM62AX_IOPAD(0x0b4, PIN_INPUT_PULLUP, 1) /* (K24) GPMC0_CSn3.I2C2_SDA */ + >; + }; + + main_mmc1_pins_default: main-mmc1-pins-default { + pinctrl-single,pins = < + AM62AX_IOPAD(0x23c, PIN_INPUT, 0) /* (A21) MMC1_CMD */ + AM62AX_IOPAD(0x234, PIN_INPUT, 0) /* (B22) MMC1_CLK */ + AM62AX_IOPAD(0x230, PIN_INPUT, 0) /* (A22) MMC1_DAT0 */ + AM62AX_IOPAD(0x22c, PIN_INPUT, 0) /* (B21) MMC1_DAT1 */ + AM62AX_IOPAD(0x228, PIN_INPUT, 0) /* (C21) MMC1_DAT2 */ + AM62AX_IOPAD(0x224, PIN_INPUT, 0) /* (D22) MMC1_DAT3 */ + AM62AX_IOPAD(0x240, PIN_INPUT, 0) /* (D17) MMC1_SDCD */ + >; + }; + + usr_led_pins_default: usr-led-pins-default { + pinctrl-single,pins = < + AM62AX_IOPAD(0x244, PIN_OUTPUT, 7) /* (D18) MMC1_SDWP.GPIO1_49 */ + >; + }; +}; + +&main_i2c0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c0_pins_default>; + clock-frequency = <400000>; +}; + +&main_i2c1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c1_pins_default>; + clock-frequency = <400000>; + + exp1: gpio@22 { + compatible = "ti,tca6424"; + reg = <0x22>; + gpio-controller; + #gpio-cells = <2>; + + gpio-line-names = "GPIO_CPSW2_RST", "GPIO_CPSW1_RST", + "BT_EN_SOC", "MMC1_SD_EN", + "VPP_EN", "EXP_PS_3V3_En", + "EXP_PS_5V0_En", "EXP_HAT_DETECT", + "GPIO_AUD_RSTn", "GPIO_eMMC_RSTn", + "UART1_FET_BUF_EN", "BT_UART_WAKE_SOC", + "GPIO_HDMI_RSTn", "CSI_GPIO0", + "CSI_GPIO1", "WLAN_ALERTn", + "HDMI_INTn", "TEST_GPIO2", + "MCASP1_FET_EN", "MCASP1_BUF_BT_EN", + "MCASP1_FET_SEL", "UART1_FET_SEL", + "PD_I2C_IRQ", "IO_EXP_TEST_LED"; + }; +}; + +&sdhci1 { + /* SD/MMC */ + status = "okay"; + vmmc-supply = <&vdd_mmc1>; + pinctrl-names = "default"; + pinctrl-0 = <&main_mmc1_pins_default>; + ti,driver-strength-ohm = <50>; + disable-wp; +}; + +&main_gpio0 { + status = "okay"; +}; + +&main_gpio1 { + status = "okay"; +}; + +&main_gpio_intr { + status = "okay"; +}; + +&main_uart0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_uart0_pins_default>; +}; diff --git a/arch/arm/dts/k3-am62a7.dtsi b/arch/arm/dts/k3-am62a7.dtsi new file mode 100644 index 0000000000..331d89fda2 --- /dev/null +++ b/arch/arm/dts/k3-am62a7.dtsi @@ -0,0 +1,103 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for AM62A7 SoC family in Quad core configuration + * + * TRM: https://www.ti.com/lit/zip/spruj16 + * + * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; + +#include "k3-am62a.dtsi" + +/ { + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu-map { + cluster0: cluster0 { + core0 { + cpu = <&cpu0>; + }; + + core1 { + cpu = <&cpu1>; + }; + + core2 { + cpu = <&cpu2>; + }; + + core3 { + cpu = <&cpu3>; + }; + }; + }; + + cpu0: cpu@0 { + compatible = "arm,cortex-a53"; + reg = <0x000>; + device_type = "cpu"; + enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&L2_0>; + }; + + cpu1: cpu@1 { + compatible = "arm,cortex-a53"; + reg = <0x001>; + device_type = "cpu"; + enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&L2_0>; + }; + + cpu2: cpu@2 { + compatible = "arm,cortex-a53"; + reg = <0x002>; + device_type = "cpu"; + enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&L2_0>; + }; + + cpu3: cpu@3 { + compatible = "arm,cortex-a53"; + reg = <0x003>; + device_type = "cpu"; + enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&L2_0>; + }; + }; + + L2_0: l2-cache0 { + compatible = "cache"; + cache-level = <2>; + cache-size = <0x40000>; + cache-line-size = <64>; + cache-sets = <512>; + }; +}; diff --git a/arch/arm/dts/k3-am64-mcu.dtsi b/arch/arm/dts/k3-am64-mcu.dtsi index 59cc58f7d0..2bb5c9ff17 100644 --- a/arch/arm/dts/k3-am64-mcu.dtsi +++ b/arch/arm/dts/k3-am64-mcu.dtsi @@ -97,4 +97,12 @@ clocks = <&k3_clks 79 0>; clock-names = "gpio"; }; + + mcu_pmx0: pinctrl@4084000 { + compatible = "pinctrl-single"; + reg = <0x00 0x4084000 0x00 0x84>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0xffffffff>; + }; }; diff --git a/arch/arm/dts/nuvoton-common-npcm8xx.dtsi b/arch/arm/dts/nuvoton-common-npcm8xx.dtsi index aa7aac8c37..4538345dda 100644 --- a/arch/arm/dts/nuvoton-common-npcm8xx.dtsi +++ b/arch/arm/dts/nuvoton-common-npcm8xx.dtsi @@ -4,6 +4,7 @@ #include <dt-bindings/clock/nuvoton,npcm845-clk.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/gpio/gpio.h> / { #address-cells = <2>; @@ -60,6 +61,70 @@ reg = <0x0 0xf0801000 0x0 0x1000>; }; + sdhci0: sdhci@f0842000 { + compatible = "nuvoton,npcm845-sdhci"; + reg = <0x0 0xf0842000 0x0 0x100>; + interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk NPCM8XX_CLK_AHB>; + clock-names = "clk_mmc"; + pinctrl-names = "default"; + pinctrl-0 = <&mmc8_pins + &mmc_pins>; + status = "disabled"; + }; + + fiu0: spi@fb000000 { + compatible = "nuvoton,npcm845-fiu"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0xfb000000 0x0 0x1000>, + <0x0 0x80000000 0x0 0x10000000>; + reg-names = "control", "memory"; + clocks = <&clk NPCM8XX_CLK_SPI0>; + clock-names = "clk_ahb"; + status = "disabled"; + }; + + fiu1: spi@fb002000 { + compatible = "nuvoton,npcm845-fiu"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0xfb002000 0x0 0x1000>, + <0x0 0x90000000 0x0 0x4000000>; + reg-names = "control", "memory"; + clocks = <&clk NPCM8XX_CLK_SPI1>; + clock-names = "clk_spi1"; + pinctrl-names = "default"; + pinctrl-0 = <&spi1_pins>; + status = "disabled"; + }; + + fiu3: spi@c0000000 { + compatible = "nuvoton,npcm845-fiu"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0xc0000000 0x0 0x1000>, + <0x0 0xA0000000 0x0 0x20000000>; + reg-names = "control", "memory"; + clocks = <&clk NPCM8XX_CLK_SPI3>; + clock-names = "clk_spi3"; + pinctrl-names = "default"; + pinctrl-0 = <&spi3_pins>; + status = "disabled"; + }; + + fiux: spi@fb001000 { + compatible = "nuvoton,npcm845-fiu"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0xfb001000 0x0 0x1000>, + <0x0 0xf8000000 0x0 0x2000000>; + reg-names = "control", "memory"; + clocks = <&clk NPCM8XX_CLK_SPIX>; + clock-names = "clk_ahb"; + status = "disabled"; + }; + apb { #address-cells = <1>; #size-cells = <1>; @@ -68,6 +133,19 @@ ranges = <0x0 0x0 0xf0000000 0x00300000>, <0xfff00000 0x0 0xfff00000 0x00016000>; + spi1: spi@201000 { + compatible = "nuvoton,npcm845-pspi"; + reg = <0x201000 0x1000>; + pinctrl-names = "default"; + pinctrl-0 = <&pspi_pins>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk NPCM8XX_CLK_APB5>; + clock-names = "clk_apb5"; + status = "disabled"; + }; + timer0: timer@8000 { compatible = "nuvoton,npcm845-timer"; interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; @@ -165,6 +243,20 @@ clocks = <&clk NPCM8XX_CLK_REFCLK>; syscon = <&gcr>; }; + + i2c0: i2c@80000 { + compatible = "nuvoton,npcm845-i2c"; + reg = <0x80000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clk NPCM8XX_CLK_APB2>; + clock-frequency = <100000>; + interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&smb0_pins>; + syscon = <&gcr>; + status = "disabled"; + }; }; }; }; diff --git a/arch/arm/dts/nuvoton-npcm7xx-u-boot.dtsi b/arch/arm/dts/nuvoton-npcm7xx-u-boot.dtsi index c547e433e7..d54064091e 100644 --- a/arch/arm/dts/nuvoton-npcm7xx-u-boot.dtsi +++ b/arch/arm/dts/nuvoton-npcm7xx-u-boot.dtsi @@ -220,7 +220,7 @@ clocks = <&clk NPCM7XX_CLK_APB1>; }; gpio_0: gpio0@10000 { - compatible = "nuvoton,npcm-gpio"; + compatible = "nuvoton,npcm-gpio", "nuvoton,npcm750-gpio"; reg = <0x10000 0xB0>; #gpio-cells = <2>; gpio-controller; @@ -228,7 +228,7 @@ }; gpio_1: gpio1@11000 { - compatible = "nuvoton,npcm-gpio"; + compatible = "nuvoton,npcm-gpio", "nuvoton,npcm750-gpio"; reg = <0x11000 0xB0>; #gpio-cells = <2>; gpio-controller; @@ -236,14 +236,14 @@ }; gpio_2: gpio2@12000 { - compatible = "nuvoton,npcm-gpio"; + compatible = "nuvoton,npcm-gpio", "nuvoton,npcm750-gpio"; reg = <0x12000 0xB0>; #gpio-cells = <2>; gpio-controller; gpio-bank-name = "gpio2"; }; gpio_3: gpio3@13000 { - compatible = "nuvoton,npcm-gpio"; + compatible = "nuvoton,npcm-gpio", "nuvoton,npcm750-gpio"; reg = <0x13000 0xB0>; #gpio-cells = <2>; gpio-controller; @@ -251,7 +251,7 @@ }; gpio_4: gpio4@14000 { - compatible = "nuvoton,npcm-gpio"; + compatible = "nuvoton,npcm-gpio", "nuvoton,npcm750-gpio"; reg = <0x14000 0xB0>; #gpio-cells = <2>; gpio-controller; @@ -259,7 +259,7 @@ }; gpio_5: gpio5@15000 { - compatible = "nuvoton,npcm-gpio"; + compatible = "nuvoton,npcm-gpio", "nuvoton,npcm750-gpio"; reg = <0x15000 0xB0>; #gpio-cells = <2>; gpio-controller; @@ -267,14 +267,14 @@ }; gpio_6: gpio6@16000 { - compatible = "nuvoton,npcm-gpio"; + compatible = "nuvoton,npcm-gpio", "nuvoton,npcm750-gpio"; reg = <0x16000 0xB0>; #gpio-cells = <2>; gpio-controller; gpio-bank-name = "gpio6"; }; gpio_7: gpio7@17000 { - compatible = "nuvoton,npcm-gpio"; + compatible = "nuvoton,npcm-gpio", "nuvoton,npcm750-gpio"; reg = <0x17000 0xB0>; #gpio-cells = <2>; gpio-controller; diff --git a/arch/arm/dts/nuvoton-npcm845-evb.dts b/arch/arm/dts/nuvoton-npcm845-evb.dts index a5ab2bc0f8..53f4c6aeca 100644 --- a/arch/arm/dts/nuvoton-npcm845-evb.dts +++ b/arch/arm/dts/nuvoton-npcm845-evb.dts @@ -3,6 +3,7 @@ /dts-v1/; #include "nuvoton-npcm845.dtsi" +#include "nuvoton-npcm845-pincfg.dtsi" / { model = "Nuvoton npcm845 Development Board (Device Tree)"; @@ -10,6 +11,15 @@ aliases { serial0 = &serial0; + i2c0 = &i2c0; + spi0 = &fiu0; + spi1 = &fiu1; + spi3 = &fiu3; + spi4 = &fiux; + spi5 = &spi1; + usb0 = &udc0; + usb1 = &ehci1; + usb2 = &ehci2; }; chosen { @@ -19,6 +29,31 @@ memory { reg = <0x0 0x0 0x0 0x40000000>; }; + + vsbr2: vsbr2 { + compatible = "regulator-npcm845"; + regulator-name = "vr2"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vsbv8: vsbv8 { + compatible = "regulator-npcm845"; + regulator-name = "v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vsbv5: vsbv5 { + compatible = "regulator-npcm845"; + regulator-name = "v5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; &serial0 { @@ -28,3 +63,97 @@ &watchdog1 { status = "okay"; }; + +&fiu0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&spi0cs1_pins>; + spi-nor@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <25000000>; + }; + spi_flash@1 { + compatible = "jedec,spi-nor"; + reg = <1>; + spi-max-frequency = <25000000>; + }; +}; + +&fiu1 { + status = "okay"; + spi-nor@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <25000000>; + }; +}; + +&fiu3 { + pinctrl-0 = <&spi3_pins>, <&spi3quad_pins>; + status = "okay"; + vqspi-supply = <&vsbv5>; + vqspi-microvolt = <3300000>; + spi-nor@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <25000000>; + }; +}; + +&fiux { + nuvoton,spix-mode; + status = "okay"; +}; + +&spi1 { + status = "okay"; +}; + +&usbphy1 { + status = "okay"; +}; + +&usbphy2 { + status = "okay"; +}; + +&usbphy3 { + status = "okay"; +}; + +&udc0 { + status = "okay"; + phys = <&usbphy1 0>; +}; + +&sdhci0 { + bus-width = <0x8>; + status = "okay"; +}; + +&ehci1 { + status = "okay"; + phys = <&usbphy2 3>; +}; + +&ehci2 { + status = "okay"; + phys = <&usbphy3 4>; +}; + +&i2c0 { + status = "okay"; +}; + +&pinctrl { + pinctrl-names = "default"; + pinctrl-0 = < + &gspi_pins + &vgadig_pins + &spix_pins + &r1_pins + &r1en_pins + &r1oen_pins + >; +};
\ No newline at end of file diff --git a/arch/arm/dts/nuvoton-npcm845-pincfg.dtsi b/arch/arm/dts/nuvoton-npcm845-pincfg.dtsi new file mode 100644 index 0000000000..65de96b1f5 --- /dev/null +++ b/arch/arm/dts/nuvoton-npcm845-pincfg.dtsi @@ -0,0 +1,2007 @@ +// SPDX-License-Identifier: GPL-2.0+ +// Copyright (c) 2021 Nuvoton Technology tomer.maimon@nuvoton.com + +/ { + pinctrl: pinctrl@f0800000 { + gpio0o_pins: gpio0o-pins { + pins = "GPIO0/IOX1_DI/SMB6C_SDA/SMB18_SDA"; + bias-disable; + output-high; + }; + gpio1_pins: gpio1-pins { + pins = "GPIO1/IOX1_LD/SMB6C_SCL/SMB18_SCL"; + bias-disable; + input-enable; + }; + gpio2_pins: gpio2-pins { + pins = "GPIO2/IOX1_CK/SMB6B_SDA/SMB17_SDA"; + bias-disable; + input-enable; + }; + gpio2o_pins: gpio2o-pins { + pins = "GPIO2/IOX1_CK/SMB6B_SDA/SMB17_SDA"; + bias-disable; + output_high; + }; + gpio3_pins: gpio3-pins { + pins = "GPIO3/IOX1_DO/SMB6B_SCL/SMB17_SCL"; + bias-disable; + input-enable; + }; + gpio3o_pins: gpio3o-pins { + pins = "GPIO3/IOX1_DO/SMB6B_SCL/SMB17_SCL"; + bias-disable; + output-high; + }; + gpio4_pins: gpio4-pins { + pins = "GPIO4/IOX2_DI/SMB1D_SDA"; + bias-disable; + input-enable; + }; + gpio5_pins: gpio5-pins { + pins = "GPIO5/IOX2_LD/SMB1D_SCL"; + bias-disable; + input-enable; + }; + gpio6_pins: gpio6-pins { + pins = "GPIO6/IOX2_CK/SMB2D_SDA"; + bias-disable; + input-enable; + }; + gpio6o_pins: gpio6o-pins { + pins = "GPIO6/IOX2_CK/SMB2D_SDA"; + bias-disable; + output-high; + }; + gpio6ol_pins: gpio6ol-pins { + pins = "GPIO6/IOX2_CK/SMB2D_SDA"; + bias-disable; + output-low; + }; + gpio7_pins: gpio7-pins { + pins = "GPIO7/IOX2_D0/SMB2D_SCL"; + bias-disable; + input-enable; + }; + gpio7o_pins: gpio7o-pins { + pins = "GPIO7/IOX2_D0/SMB2D_SCL"; + bias-disable; + output-high; + }; + gpio7ol_pins: gpio7ol-pins { + pins = "GPIO7/IOX2_D0/SMB2D_SCL"; + bias-disable; + output-low; + }; + gpio8_pins: gpio8-pins { + pins = "GPIO8/LKGPO1/TP_GPIO0"; + bias-disable; + input-enable; + }; + gpio8ol_pins: gpio8ol-pins { + pins = "GPIO8/LKGPO1/TP_GPIO0"; + bias-disable; + output-low; + }; + gpio9_pins: gpio9-pins { + pins = "GPIO9/LKGPO2/TP_GPIO1"; + bias-disable; + input-enable; + }; + gpio9o_pins: gpio9o-pins { + pins = "GPIO9/LKGPO2/TP_GPIO1"; + bias-disable; + output-high; + }; + gpio9ol_pins: gpio9ol-pins { + pins = "GPIO9/LKGPO2/TP_GPIO1"; + bias-disable; + output-low; + }; + gpio10_pins: gpio10-pins { + pins = "GPIO10/IOXH_LD/SMB6D_SCL/SMB16_SCL"; + bias-disable; + input-enable; + }; + gpio10ol_pins: gpio10ol-pins { + pins = "GPIO10/IOXH_LD/SMB6D_SCL/SMB16_SCL"; + bias-disable; + output-low; + }; + gpio11_pins: gpio11-pins { + pins = "GPIO11/IOXH_CK/SMB6D_SDA/SMB16_SDA"; + bias-disable; + input-enable; + }; + gpio11o_pins: gpio11o-pins { + pins = "GPIO11/IOXH_CK/SMB6D_SDA/SMB16_SDA"; + bias-disable; + output-high; + }; + gpio11ol_pins: gpio11ol-pins { + pins = "GPIO11/IOXH_CK/SMB6D_SDA/SMB16_SDA"; + bias-disable; + output-low; + }; + gpio12_pins: gpio12-pins { + pins = "GPIO12/GSPI_CK/SMB5B_SCL"; + bias-disable; + input-enable; + }; + gpio12o_pins: gpio12o-pins { + pins = "GPIO12/GSPI_CK/SMB5B_SCL"; + bias-disable; + output-high; + }; + gpio12ol_pins: gpio12ol-pins { + pins = "GPIO12/GSPI_CK/SMB5B_SCL"; + bias-disable; + output-low; + }; + gpio13_pins: gpio13-pins { + pins = "GPIO13/GSPI_DO/SMB5B_SDA"; + bias-disable; + input-enable; + }; + gpio13ol_pins: gpio13ol-pins { + pins = "GPIO13/GSPI_DO/SMB5B_SDA"; + bias-disable; + output-low; + }; + gpio14_pins: gpio14-pins { + pins = "GPIO14/GSPI_DI/SMB5C_SCL"; + bias-disable; + input-enable; + }; + gpio14ol_pins: gpio14ol-pins { + pins = "GPIO14/GSPI_DI/SMB5C_SCL"; + bias-disable; + output-low; + }; + gpio15_pins: gpio15-pins { + pins = "GPIO15/GSPI_CS/SMB5C_SDA"; + bias-disable; + input-enable; + }; + gpio15o_pins: gpio15o-pins { + pins = "GPIO15/GSPI_CS/SMB5C_SDA"; + bias-disable; + output-high; + }; + gpio16_pins: gpio16-pins { + pins = "GPIO16/SMB7B_SDA/LKGPO0/TP_GPIO2"; + bias-disable; + input-enable; + }; + gpio16o_pins: gpio16o-pins { + pins = "GPIO16/SMB7B_SDA/LKGPO0/TP_GPIO2"; + bias-disable; + output-high; + }; + gpio16ol_pins: gpio16ol-pins { + pins = "GPIO16/SMB7B_SDA/LKGPO0/TP_GPIO2"; + bias-disable; + output-low; + }; + gpio17_pins: gpio17-pins { + pins = "GPIO17/PSPI_DI/CP1_GPIO5"; + bias-disable; + input-enable; + }; + gpio17o_pins: gpio17o-pins { + pins = "GPIO17/PSPI_DI/CP1_GPIO5"; + bias-disable; + output-high; + }; + gpio17ol_pins: gpio17ol-pins { + pins = "GPIO17/PSPI_DI/CP1_GPIO5"; + bias-disable; + output-low; + }; + gpio18_pins: gpio18-pins { + pins = "GPIO18/PSPI_D0/SMB4B_SDA"; + bias-disable; + input-enable; + }; + gpio18ol_pins: gpio18ol-pins { + pins = "GPIO18/PSPI_D0/SMB4B_SDA"; + bias-disable; + output-low; + }; + gpio19_pins: gpio19-pins { + pins = "GPIO19/PSPI_CK/SMB4B_SCL"; + bias-disable; + input-enable; + }; + gpio19ol_pins: gpio19ol-pins { + pins = "GPIO19/PSPI_CK/SMB4B_SCL"; + bias-disable; + output-low; + }; + gpio20_pins: gpio20-pins { + pins = "GPIO20/H_GPIO0/SMB4C_SDA/SMB15_SDA"; + bias-disable; + input-enable; + }; + gpio20o_pins: gpio20o-pins { + pins = "GPIO20/H_GPIO0/SMB4C_SDA/SMB15_SDA"; + bias-disable; + output-high; + }; + gpio20ol_pins: gpio20ol-pins { + pins = "GPIO20/H_GPIO0/SMB4C_SDA/SMB15_SDA"; + bias-disable; + output-low; + }; + gpio21_pins: gpio21-pins { + pins = "GPIO21/H_GPIO1/SMB4C_SCL/SMB15_SCL"; + bias-disable; + input-enable; + }; + gpio21ol_pins: gpio21ol-pins { + pins = "GPIO21/H_GPIO1/SMB4C_SCL/SMB15_SCL"; + bias-disable; + output-low; + }; + gpio22_pins: gpio22-pins { + pins = "GPIO22/H_GPIO2/SMB4D_SDA/SMB14_SDA"; + bias-disable; + input-enable; + }; + gpio22ol_pins: gpio22ol-pins { + pins = "GPIO22/H_GPIO2/SMB4D_SDA/SMB14_SDA"; + bias-disable; + output-low; + }; + gpio23_pins: gpio23-pins { + pins = "GPIO23/H_GPIO3/SMB4D_SCL/SMB14_SCL"; + bias-disable; + input-enable; + }; + gpio23ol_pins: gpio23ol-pins { + pins = "GPIO23/H_GPIO3/SMB4D_SCL/SMB14_SCL"; + bias-disable; + output-low; + }; + gpio24_pins: gpio24-pins { + pins = "GPIO24/IOXH_DO/H_GPIO4/SMB7C_SCL/TP_SMB2_SCL"; + bias-disable; + input-enable; + }; + gpio24o_pins: gpio24o-pins { + pins = "GPIO24/IOXH_DO/H_GPIO4/SMB7C_SCL/TP_SMB2_SCL"; + bias-disable; + output-high; + }; + gpio24ol_pins: gpio24ol-pins { + pins = "GPIO24/IOXH_DO/H_GPIO4/SMB7C_SCL/TP_SMB2_SCL"; + bias-disable; + output-low; + }; + gpio25_pins: gpio25-pins { + pins = "GPIO25/IOXH_DI/H_GPIO4/SMB7C_SDA/TP_SMB2_SDA"; + bias-disable; + input-enable; + }; + gpio25o_pins: gpio25o-pins { + pins = "GPIO25/IOXH_DI/H_GPIO4/SMB7C_SDA/TP_SMB2_SDA"; + bias-disable; + output-high; + }; + gpio25ol_pins: gpio25ol-pins { + pins = "GPIO25/IOXH_DI/H_GPIO4/SMB7C_SDA/TP_SMB2_SDA"; + bias-disable; + output-low; + }; + gpio26_pins: gpio26-pins { + pins = "GPIO26/SMB5_SDA"; + bias-disable; + input-enable; + }; + gpio27_pins: gpio27-pins { + pins = "GPIO27/SMB5_SCL"; + bias-disable; + input-enable; + }; + gpio32_pins: gpio32-pins { + pins = "GPIO32/SMB14_SCL/SPI0_nCS1"; + bias-disable; + input-enable; + }; + gpio32o_pins: gpio32o-pins { + pins = "GPIO32/SMB14_SCL/SPI0_nCS1"; + bias-disable; + output-high; + }; + gpio32ol_pins: gpio32ol-pins { + pins = "GPIO32/SMB14_SCL/SPI0_nCS1"; + bias-disable; + output-low; + }; + gpio37_pins: gpio37-pins { + pins = "GPIO37/SMB3C_SDA/SMB23_SDA"; + bias-disable; + input-enable; + }; + gpio37o_pins: gpio37o-pins { + pins = "GPIO37/SMB3C_SDA/SMB23_SDA"; + bias-disable; + output-high; + }; + gpio37ol_pins: gpio37ol-pins { + pins = "GPIO37/SMB3C_SDA/SMB23_SDA"; + bias-disable; + output-low; + }; + gpio38_pins: gpio38-pins { + pins = "GPIO38/SMB3C_SCL/SMB23_SCL"; + bias-disable; + input-enable; + }; + gpio38o_pins: gpio38o-pins { + pins = "GPIO38/SMB3C_SCL/SMB23_SCL"; + bias-disable; + output-high; + }; + gpio38ol_pins: gpio38ol-pins { + pins = "GPIO38/SMB3C_SCL/SMB23_SCL"; + bias-disable; + output-low; + }; + gpio39_pins: gpio39-pins { + pins = "GPIO39/SMB3B_SDA/SMB22_SDA"; + bias-disable; + input-enable; + }; + gpio39o_pins: gpio39o-pins { + pins = "GPIO39/SMB3B_SDA/SMB22_SDA"; + bias-disable; + output-high; + }; + gpio39ol_pins: gpio39ol-pins { + pins = "GPIO39/SMB3B_SDA/SMB22_SDA"; + bias-disable; + output-low; + }; + gpio40_pins: gpio40-pins { + pins = "GPIO40/SMB3B_SCL/SMB22_SCL"; + bias-disable; + input-enable; + }; + gpio40o_pins: gpio40o-pins { + pins = "GPIO40/SMB3B_SCL/SMB22_SCL"; + bias-disable; + output-high; + }; + gpio40ol_pins: gpio40ol-pins { + pins = "GPIO40/SMB3B_SCL/SMB22_SCL"; + bias-disable; + output-low; + }; + gpio41_pins: gpio41-pins { + pins = "GPIO41/BU0_RXD/CP1U_RXD"; + input-enable; + }; + gpio42_pins: gpio42-pins { + pins = "GPIO42/BU0_TXD/CP1U_TXD"; + bias-disable; + input-enable; + }; + gpio43_pins: gpio43-pins { + pins = "GPIO43/SI1_RXD/BU1_RXD"; + bias-disable; + input-enable; + }; + gpio44_pins: gpio44-pins { + pins = "GPIO44/SI1_nCTS/BU1_nCTS/CP_TDI/TP_TDI/CP_TP_TDI"; + bias-disable; + input-enable; + }; + gpio45_pins: gpio45-pins { + pins = "GPIO45/SI1_nDCD/CP_TMS_SWIO/TP_TMS_SWIO/CP_TP_TMS_SWIO"; + bias-disable; + input-enable; + }; + gpio46_pins: gpio46-pins { + pins = "GPIO46/SI1_nDSR/CP_TCK_SWCLK/TP_TCK_SWCLK/CP_TP_TCK_SWCLK"; + bias-disable; + input-enable; + }; + gpio47_pins: gpio47-pins { + pins = "GPIO47/SI1n_RI1"; + bias-disable; + input-enable; + }; + gpio48_pins: gpio48-pins { + pins = "GPIO48/SI2_TXD/BU0_TXD/STRAP5"; + bias-disable; + input-enable; + }; + gpio49_pins: gpio49-pins { + pins = "GPIO49/SI2_RXD/BU0_RXD"; + bias-disable; + input-enable; + }; + gpio50_pins: gpio50-pins { + pins = "GPIO50/SI2_nCTS/BU6_TXD/TPU_TXD"; + bias-disable; + input-enable; + }; + gpio50ol_pins: gpio50ol-pins { + pins = "GPIO50/SI2_nCTS/BU6_TXD/TPU_TXD"; + bias-disable; + output-low; + }; + gpio51_pins: gpio51-pins { + pins = "GPIO51/SI2_nRTS/BU6_RXD/TPU_RXD"; + bias-disable; + input-enable; + }; + gpio51o_pins: gpio51o-pins { + pins = "GPIO51/SI2_nRTS/BU6_RXD/TPU_RXD"; + bias-disable; + output-high; + }; + gpio52_pins: gpio52-pins { + pins = "GPIO52/SI2_nDCD/BU5_RXD"; + bias-disable; + input-enable; + }; + gpio52ol_pins: gpio52ol-pins { + pins = "GPIO52/SI2_nDCD/BU5_RXD"; + bias-disable; + output-low; + }; + gpio53_pins: gpio53-pins { + pins = "GPIO53/SI2_nDTR_BOUT2/BU5_TXD"; + bias-disable; + input-enable; + }; + gpio53o_pins: gpio53o-pins { + pins = "GPIO53/SI2_nDTR_BOUT2/BU5_TXD"; + bias-disable; + output-high; + }; + gpio54_pins: gpio54-pins { + pins = "GPIO54/SI2_nDSR/BU4_TXD"; + bias-disable; + input-enable; + }; + gpio54ol_pins: gpio54ol-pins { + pins = "GPIO54/SI2_nDSR/BU4_TXD"; + bias-disable; + output-low; + }; + gpio55_pins: gpio55-pins { + pins = "GPIO55/SI2_RI2/BU4_RXD"; + bias-disable; + input-enable; + }; + gpio55ol_pins: gpio55ol-pins { + pins = "GPIO55/SI2_RI2/BU4_RXD"; + bias-disable; + output-low; + }; + gpio56_pins: gpio56-pins { + pins = "GPIO56/R1_RXERR/R1_OEN"; + bias-disable; + input-enable; + }; + gpio57_pins: gpio57-pins { + pins = "GPIO57/R1_MDC/TP_GPIO4"; + bias-disable; + input-enable; + }; + gpio57ol_pins: gpio57ol-pins { + pins = "GPIO57/R1_MDC/TP_GPIO4"; + bias-disable; + output-low; + }; + gpio58_pins: gpio58-pins { + pins = "GPIO58/R1_MDIO/TP_GPIO5"; + bias-disable; + input-enable; + }; + gpio58ol_pins: gpio58ol-pins { + pins = "GPIO58/R1_MDIO/TP_GPIO5"; + bias-disable; + output-low; + }; + gpio59_pins: gpio59-pins { + pins = "GPIO59/H_GPIO06/SMB3D_SDA/SMB19_SDA"; + bias-disable; + input-enable; + }; + gpio59o_pins: gpio59o-pins { + pins = "GPIO59/H_GPIO06/SMB3D_SDA/SMB19_SDA"; + bias-disable; + output-high; + }; + gpio59ol_pins: gpio59ol-pins { + pins = "GPIO59/H_GPIO06/SMB3D_SDA/SMB19_SDA"; + bias-disable; + output-low; + }; + gpio60_pins: gpio60-pins { + pins = "GPIO60/H_GPIO07/SMB3D_SCL/SMB19_SCL"; + bias-disable; + input-enable; + }; + gpio60o_pins: gpio60o-pins { + pins = "GPIO60/H_GPIO07/SMB3D_SCL/SMB19_SCL"; + bias-disable; + output-high; + }; + gpio60ol_pins: gpio60ol-pins { + pins = "GPIO60/H_GPIO07/SMB3D_SCL/SMB19_SCL"; + bias-disable; + output-low; + }; + gpio61_pins: gpio61-pins { + pins = "GPIO61/SI1_nDTR_BOUT"; + bias-disable; + input-enable; + }; + gpio61o_pins: gpio61o-pins { + pins = "GPIO61/SI1_nDTR_BOUT"; + bias-disable; + output-high; + }; + gpio62_pins: gpio62-pins { + pins = "GPIO62/SI1_nRTS/BU1_nRTS/CP_TDO_SWO/TP_TDO_SWO/CP_TP_TDO_SWO"; + bias-disable; + input-enable; + }; + gpio62o_pins: gpio62o-pins { + pins = "GPIO62/SI1_nRTS/BU1_nRTS/CP_TDO_SWO/TP_TDO_SWO/CP_TP_TDO_SWO"; + bias-disable; + output-high; + }; + gpio63_pins: gpio63-pins { + pins = "GPIO63/BU1_TXD1/SI1_TXD"; + bias-disable; + input-enable; + }; + gpio63o_pins: gpio63o-pins { + pins = "GPIO63/BU1_TXD1/SI1_TXD"; + bias-disable; + output-high; + }; + gpio64_pins: gpio64-pins { + pins = "GPIO64/FANIN0"; + bias-disable; + input-enable; + }; + gpio64o_pins: gpio64o-pins { + pins = "GPIO64/FANIN0"; + bias-disable; + output-high; + }; + gpio65_pins: gpio65-pins { + pins = "GPIO65/FANIN1"; + bias-disable; + input-enable; + }; + gpio66_pins: gpio66-pins { + pins = "GPIO66/FANIN2"; + bias-disable; + input-enable; + }; + gpio67_pins: gpio67-pins { + pins = "GPIO67/FANIN3"; + bias-disable; + input-enable; + }; + gpio68_pins: gpio68-pins { + pins = "GPIO68/FANIN4"; + bias-disable; + input-enable; + }; + gpio68o_pins: gpio68o-pins { + pins = "GPIO68/FANIN4"; + bias-disable; + output-high; + }; + gpio69_pins: gpio69-pins { + pins = "GPIO69/FANIN5"; + bias-disable; + input-enable; + }; + gpio69o_pins: gpio69o-pins { + pins = "GPIO69/FANIN5"; + bias-disable; + output-high; + }; + gpio69ol_pins: gpio69ol-pins { + pins = "GPIO69/FANIN5"; + bias-disable; + output-low; + }; + gpio70_pins: gpio70-pins { + pins = "GPIO70/FANIN6"; + bias-disable; + input-enable; + }; + gpio70o_pins: gpio70o-pins { + pins = "GPIO70/FANIN6"; + bias-disable; + output-high; + }; + gpio71_pins: gpio71-pins { + pins = "GPIO71/FANIN7"; + bias-disable; + input-enable; + }; + gpio72_pins: gpio72-pins { + pins = "GPIO72/FANIN8"; + bias-disable; + input-enable; + }; + gpio72ol_pins: gpio72ol-pins { + pins = "GPIO72/FANIN8"; + bias-disable; + output-low; + }; + gpio73_pins: gpio73-pins { + pins = "GPIO73/FANIN9"; + bias-disable; + input-enable; + }; + gpio73ol_pins: gpio73ol-pins { + pins = "GPIO73/FANIN9"; + bias-disable; + output-low; + }; + gpio74_pins: gpio74-pins { + pins = "GPIO74/FANIN10"; + bias-disable; + input-enable; + }; + gpio74ol_pins: gpio74ol-pins { + pins = "GPIO74/FANIN10"; + bias-disable; + output-low; + }; + gpio75_pins: gpio75-pins { + pins = "GPIO75/FANIN11"; + bias-disable; + input-enable; + }; + gpio75ol_pins: gpio75ol-pins { + pins = "GPIO75/FANIN11"; + bias-disable; + output-low; + }; + gpio76_pins: gpio76-pins { + pins = "GPIO76/FANIN12"; + bias-disable; + input-enable; + }; + gpio76ol_pins: gpio76ol-pins { + pins = "GPIO76/FANIN12"; + bias-disable; + output-low; + }; + gpio77_pins: gpio77-pins { + pins = "GPIO77/FANIN13"; + bias-disable; + input-enable; + }; + gpio77ol_pins: gpio77ol-pins { + pins = "GPIO77/FANIN13"; + bias-disable; + output-low; + }; + gpio78_pins: gpio78-pins { + pins = "GPIO78/FANIN14"; + bias-disable; + input-enable; + }; + gpio78ol_pins: gpio78ol-pins { + pins = "GPIO78/FANIN14"; + bias-disable; + output-low; + }; + gpio79_pins: gpio79-pins { + pins = "GPIO79/FANIN15"; + bias-disable; + input-enable; + }; + gpio79ol_pins: gpio79ol-pins { + pins = "GPIO79/FANIN15"; + bias-disable; + output-low; + }; + gpio80_pins: gpio80-pins { + pins = "GPIO80/PWM0"; + bias-disable; + input-enable; + }; + gpio81_pins: gpio81-pins { + pins = "GPIO81/PWM1"; + bias-disable; + input-enable; + }; + gpio82_pins: gpio82-pins { + pins = "GPIO82/PWM2"; + bias-disable; + input-enable; + }; + gpio83_pins: gpio83-pins { + pins = "GPIO83/PWM3"; + bias-disable; + input-enable; + }; + gpio84_pins: gpio84-pins { + pins = "GPIO84/R2_TXD0"; + bias-disable; + input-enable; + }; + gpio84o_pins: gpio84ol-pins { + pins = "GPIO84/R2_TXD0"; + bias-disable; + output-high; + }; + gpio85_pins: gpio85-pins { + pins = "GPIO85/R2_TXD1"; + bias-disable; + input-enable; + }; + gpio85o_pins: gpio85o-pins { + pins = "GPIO85/R2_TXD1"; + bias-disable; + output-high; + }; + gpio86_pins: gpio86-pins { + pins = "GPIO86/R2_TXEN"; + bias-disable; + input-enable; + }; + gpio86o_pins: gpio86o-pins { + pins = "GPIO86/R2_TXEN"; + bias-disable; + output-high; + }; + gpio87_pins: gpio87-pins { + pins = "GPIO87/R2_RXD0"; + bias-disable; + input-enable; + }; + gpio87o_pins: gpio87o-pins { + pins = "GPIO87/R2_RXD0"; + bias-disable; + output-high; + }; + gpio88_pins: gpio88-pins { + pins = "GPIO88/R2_RXD1"; + bias-disable; + input-enable; + }; + gpio88ol_pins: gpio88ol-pins { + pins = "GPIO88/R2_RXD1"; + bias-disable; + output-low; + }; + gpio89_pins: gpio89-pins { + pins = "GPIO89/R2_CRSDV"; + bias-disable; + input-enable; + }; + gpio89ol_pins: gpio89ol-pins { + pins = "GPIO89/R2_CRSDV"; + bias-disable; + output-low; + }; + gpio90_pins: gpio90-pins { + pins = "GPIO90/R2_RXERR/R2_OEN"; + bias-disable; + input-enable; + }; + gpio90o_pins: gpio90o0-pins { + pins = "GPIO90/R2_RXERR/R2_OEN"; + bias-disable; + output-high; + }; + gpio90ol_pins: gpio90ol-pins { + pins = "GPIO90/R2_RXERR/R2_OEN"; + bias-disable; + output-low; + }; + gpio91_pins: gpio91-pins { + pins = "GPIO91/R2_MDC/CP1_GPIO6/TP_GPIO0"; + bias-disable; + input-enable; + }; + gpio91o_pins: gpio91o-pins { + pins = "GPIO91/R2_MDC/CP1_GPIO6/TP_GPIO0"; + bias-disable; + output-high; + }; + gpio91ol_pins: gpio91ol-pins { + pins = "GPIO91/R2_MDC/CP1_GPIO6/TP_GPIO0"; + bias-disable; + output-low; + }; + gpio92_pins: gpio92-pins { + pins = "GPIO92/R2_MDIO/CP1_GPIO7/TP_GPIO1"; + bias-disable; + input-enable; + }; + gpio92o_pins: gpio92o-pins { + pins = "GPIO92/R2_MDIO/CP1_GPIO7/TP_GPIO1"; + bias-disable; + output-high; + }; + gpio92ol_pins: gpio92ol-pins { + pins = "GPIO92/R2_MDIO/CP1_GPIO7/TP_GPIO1"; + bias-disable; + output-low; + }; + gpio93_pins: gpio93-pins { + pins = "GPIO93/GA20/SMB5D_SCL"; + bias-disable; + input-enable; + }; + gpio93o_pins: gpio93o-pins { + pins = "GPIO93/GA20/SMB5D_SCL"; + bias-disable; + output-high; + }; + gpio93ol_pins: gpio93ol-pins { + pins = "GPIO93/GA20/SMB5D_SCL"; + bias-disable; + output-low; + }; + gpio94_pins: gpio94-pins { + pins = "GPIO94/nKBRST/SMB5D_SDA"; + bias-disable; + input-enable; + }; + gpio94o_pins: gpio94o-pins { + pins = "GPIO94/nKBRST/SMB5D_SDA"; + bias-disable; + output-high; + }; + gpio95_pins: gpio95-pins { + pins = "GPIO95/nESPIRST/LPC_nLRESET"; + bias-disable; + input-enable; + }; + gpio96_pins: gpio96-pins { + pins = "GPIO96/CP1_GPIO7/BU2_TXD/TP_GPIO7"; + bias-disable; + input-enable; + }; + gpio96ol_pins: gpio96ol-pins { + pins = "GPIO96/CP1_GPIO7/BU2_TXD/TP_GPIO7"; + bias-disable; + output-low; + }; + gpio97_pins: gpio97-pins { + pins = "GPIO97/CP1_GPIO6/BU2_RXD/TP_GPIO6"; + bias-disable; + input-enable; + }; + gpio97ol_pins: gpio97ol-pins { + pins = "GPIO97/CP1_GPIO6/BU2_RXD/TP_GPIO6"; + bias-disable; + output-low; + }; + gpio98_pins: gpio98-pins { + pins = "GPIO98/CP1_GPIO5/BU4_TXD/TP_GPIO5"; + bias-disable; + input-enable; + }; + gpio98o_pins: gpio98o-pins { + pins = "GPIO98/RG1TXD2"; + bias-disable; + output-high; + }; + gpio98ol_pins: gpio98ol-pins { + pins = "GPIO98/CP1_GPIO5/BU4_TXD/TP_GPIO5"; + bias-disable; + output-low; + }; + gpio99_pins: gpio99-pins { + pins = "GPIO99/CP1_GPIO4/BU4_RXD/TP_GPIO4"; + bias-disable; + input-enable; + }; + gpio99o_pins: gpio99o-pins { + pins = "GPIO99/RG1TXD3"; + bias-disable; + output-high; + }; + gpio99ol_pins: gpio99ol-pins { + pins = "GPIO99/CP1_GPIO4/BU4_RXD/TP_GPIO4"; + bias-disable; + output-low; + }; + gpio100_pins: gpio100-pins { + pins = "GPIO100/CP1_GPIO3/BU5_TXD/TP_GPIO3"; + bias-disable; + input-enable; + }; + gpio100ol_pins: gpio100ol-pins { + pins = "GPIO100/CP1_GPIO3/BU5_TXD/TP_GPIO3"; + bias-disable; + output-low; + }; + gpio101_pins: gpio101-pins { + pins = "GPIO101/CP1_GPIO2/BU5_RXD/TP_GPIO2"; + bias-disable; + input-enable; + }; + gpio101ol_pins: gpio101ol-pins { + pins = "GPIO101/CP1_GPIO2/BU5_RXD/TP_GPIO2"; + bias-disable; + output-low; + }; + gpio102_pins: gpio102-pins { + pins = "GPIO102/HSYNC"; + bias-disable; + input-enable; + }; + gpio102ol_pins: gpio102ol-pins { + pins = "GPIO102/HSYNC"; + bias-disable; + output-low; + }; + gpio103_pins: gpio103-pins { + pins = "GPIO103/VSYNC"; + bias-disable; + input-enable; + }; + gpio103ol_pins: gpio103ol-pins { + pins = "GPIO103/VSYNC"; + bias-disable; + output-low; + }; + gpio104_pins: gpio104-pins { + pins = "GPIO104/DDC_SCL"; + bias-disable; + input-enable; + }; + gpio104ol_pins: gpio104ol-pins { + pins = "GPIO104/DDC_SCL"; + bias-disable; + output-low; + }; + gpio105_pins: gpio105-pins { + pins = "GPIO105/DDC_SDA"; + bias-disable; + input-enable; + }; + gpio105ol_pins: gpio105ol-pins { + pins = "GPIO105/DDC_SDA"; + bias-disable; + output-low; + }; + gpio106_pins: gpio106-pins { + pins = "GPIO106/I3C5_SCL"; + bias-disable; + input-enable; + }; + gpio106ol_pins: gpio106ol-pins { + pins = "GPIO106/I3C5_SCL"; + bias-disable; + output-low; + }; + gpio107_pins: gpio107-pins { + pins = "GPIO107/I3C5_SDA"; + bias-disable; + input-enable; + }; + gpio107ol_pins: gpio107ol-pins { + pins = "GPIO107/I3C5_SDA"; + bias-disable; + output-low; + }; + gpio108_pins: gpio108-pins { + pins = "GPIO108/SG1_MDC"; + bias-disable; + input-enable; + }; + gpio108ol_pins: gpio108ol-pins { + pins = "GPIO108/SG1_MDC"; + bias-disable; + output-low; + }; + gpio109_pins: gpio109-pins { + pins = "GPIO109/SG1_MDIO"; + bias-disable; + input-enable; + }; + gpio109ol_pins: gpio109ol-pins { + pins = "GPIO109/SG1_MDIO"; + bias-disable; + output-low; + }; + gpio110_pins: gpio110-pins { + pins = "GPIO110/RG2_TXD0/DDRV0/R3_TXD0"; + bias-disable; + input-enable; + }; + gpio110ol_pins: gpio110ol-pins { + pins = "GPIO110/RG2_TXD0/DDRV0/R3_TXD0"; + bias-disable; + output-low; + }; + gpio111_pins: gpio111-pins { + pins = "GPIO111/RG2_TXD1/DDRV1/R3_TXD1"; + bias-disable; + input-enable; + }; + gpio111ol_pins: gpio111ol-pins { + pins = "GPIO111/RG2_TXD1/DDRV1/R3_TXD1"; + bias-disable; + output-low; + }; + gpio112_pins: gpio112-pins { + pins = "GPIO112/RG2_TXD2/DDRV2"; + bias-disable; + input-enable; + }; + gpio112ol_pins: gpio112ol-pins { + pins = "GPIO112/RG2_TXD2/DDRV2"; + bias-disable; + output-low; + }; + gpio113_pins: gpio113-pins { + pins = "GPIO113/RG2_TXD3/DDRV3"; + bias-disable; + input-enable; + }; + gpio113ol_pins: gpio113ol-pins { + pins = "GPIO113/RG2_TXD3/DDRV3"; + bias-disable; + output-low; + }; + gpio118_pins: gpio118-pins { + pins = "GPIO118/SMB2_SCL"; + bias-disable; + input-enable; + }; + gpio119_pins: gpio119-pins { + pins = "GPIO119/SMB2_SDA"; + bias-disable; + input-enable; + }; + gpio120_pins: gpio120-pins { + pins = "GPIO120/SMB2C_SDA"; + bias-disable; + input-enable; + }; + gpio120ol_pins: gpio120ol-pins { + pins = "GPIO120/SMB2C_SDA"; + bias-disable; + output-low; + }; + gpio121_pins: gpio121-pins { + pins = "GPIO121/SMB2C_SCL"; + bias-disable; + input-enable; + }; + gpio122_pins: gpio122-pins { + pins = "GPIO122/SMB2B_SDA"; + bias-disable; + input-enable; + }; + gpio123_pins: gpio123-pins { + pins = "GPIO123/SMB2B_SCL"; + bias-disable; + input-enable; + }; + gpio123_pins: gpio123-pins { + pins = "GPIO123/SMB2B_SCL"; + bias-disable; + input-enable; + }; + gpio124_pins: gpio124-pins { + pins = "GPIO124/SMB1C_SDA/CP1_GPIO3"; + bias-disable; + input-enable; + }; + gpio125_pins: gpio125-pins { + pins = "GPIO125/SMB1C_SCL/CP1_GPIO2"; + bias-disable; + input-enable; + }; + gpio126_pins: gpio126-pins { + pins = "GPIO126/SMB1B_SDA/CP1_GPIO1"; + bias-disable; + input-enable; + }; + gpio127_pins: gpio127-pins { + pins = "GPIO127/SMB1B_SCL/CP1_GPIO0"; + bias-disable; + input-enable; + }; + gpio128o_pins: gpio128o-pins { + pins = "GPIO128/SMB824_SCL"; + bias-disable; + output-high; + }; + gpio130_pins: gpio130-pins { + pins = "GPIO130/SMB925_SCL"; + bias-disable; + input-enable; + }; + gpio131_pins: gpio131-pins { + pins = "GPIO131/SMB925_SDA"; + bias-disable; + input-enable; + }; + gpio132_pins: gpio132-pins { + pins = "GPIO132/SMB1026_SCL"; + bias-disable; + input-enable; + }; + gpio133_pins: gpio133-pins { + pins = "GPIO133/SMB1026_SDA"; + bias-disable; + input-enable; + }; + gpio134_pins: gpio134-pins { + pins = "GPIO134/SMB11_SCL"; + bias-disable; + input-enable; + }; + gpio135_pins: gpio135-pins { + pins = "GPIO135/SMB11_SDA"; + bias-disable; + input-enable; + }; + gpio136_pins: gpio136-pins { + pins = "GPIO136/JM1_TCK"; + bias-disable; + input-enable; + }; + gpio136o_pins: gpio136o-pins { + pins = "GPIO136/JM1_TCK"; + bias-disable; + output-high; + }; + gpio137_pins: gpio137-pins { + pins = "GPIO137/JM1_TDO"; + bias-disable; + input-enable; + }; + gpio137o_pins: gpio137o-pins { + pins = "GPIO137/JM1_TDO"; + bias-disable; + output-high; + }; + gpio138_pins: gpio138-pins { + pins = "GPIO138/JM1_TMS"; + bias-disable; + input-enable; + }; + gpio138o_pins: gpio138o-pins { + pins = "GPIO138/JM1_TMS"; + bias-disable; + output-high; + }; + gpio139_pins: gpio139-pins { + pins = "GPIO139/JM1_TDI"; + bias-disable; + input-enable; + }; + gpio139o_pins: gpio139o-pins { + pins = "GPIO139/JM1_TDI"; + bias-disable; + output-high; + }; + gpio140_pins: gpio140-pins { + pins = "GPIO140/JM1_nTRST"; + bias-disable; + input-enable; + }; + gpio140o_pins: gpio140o-pins { + pins = "GPIO140/JM1_nTRST"; + bias-disable; + output-high; + }; + gpio141_pins: gpio141-pins { + pins = "GPIO141/SMB7B_SCL"; + bias-disable; + input-enable; + }; + gpio141o_pins: gpio141o-pins { + pins = "GPIO141/SMB7B_SCL"; + bias-disable; + output-high; + }; + gpio141ol_pins: gpio141ol-pins { + pins = "GPIO141/SMB7B_SCL"; + bias-disable; + output-low; + }; + gpio142_pins: gpio142-pins { + pins = "GPIO142/SMB7D_SCL/TPSMB1_SCL"; + bias-disable; + input-enable; + }; + gpio142o_pins: gpio142o-pins { + pins = "GPIO142/SMB7D_SCL/TPSMB1_SCL"; + bias-disable; + output-high; + }; + gpio143_pins: gpio143-pins { + pins = "GPIO143/SMB7D_SDA/TPSMB1_SDA"; + bias-disable; + input-enable; + }; + gpio143o_pins: gpio143o-pins { + pins = "GPIO143/SMB7D_SDA/TPSMB1_SDA"; + bias-disable; + output-high; + }; + gpio143ol_pins: gpio143ol-pins { + pins = "GPIO143/SMB7D_SDA/TPSMB1_SDA"; + bias-disable; + output-low; + }; + gpio144_pins: gpio144-pins { + pins = "GPIO144/PWM4"; + bias-disable; + input-enable; + }; + gpio145_pins: gpio145-pins { + pins = "GPIO145/PWM5"; + bias-disable; + input-enable; + }; + gpio146_pins: gpio146-pins { + pins = "GPIO146/PWM6"; + bias-disable; + input-enable; + }; + gpio147_pins: gpio147-pins { + pins = "GPIO147/PWM7"; + bias-disable; + input-enable; + }; + gpio148_pins: gpio148-pins { + pins = "GPIO148/MMC_DT4"; + bias-disable; + input-enable; + }; + gpio148o_pins: gpio148o-pins { + pins = "GPIO148/MMC_DT4"; + bias-disable; + output-high; + }; + gpio148ol_pins: gpio148ol_pins { + pins = "GPIO148/MMC_DT4"; + bias-disable; + output-low; + }; + gpio149_pins: gpio149-pins { + pins = "GPIO149/MMC_DT5"; + bias-disable; + input-enable; + }; + gpio149o_pins: gpio149o-pins { + pins = "GPIO149/MMC_DT5"; + bias-disable; + output-high; + }; + gpio149ol_pins: gpio149ol-pins { + pins = "GPIO149/MMC_DT5"; + bias-disable; + output-low; + }; + gpio150_pins: gpio150-pins { + pins = "GPIO150/MMC_DT6"; + bias-disable; + input-enable; + }; + gpio150o_pins: gpio150o-pins { + pins = "GPIO150/MMC_DT6"; + bias-disable; + output-high; + }; + gpio150ol_pins: gpio150ol-pins { + pins = "GPIO150/MMC_DT6"; + bias-disable; + output-low; + }; + gpio151_pins: gpio151-pins { + pins = "GPIO151/MMC_DT7"; + bias-disable; + input-enable; + }; + gpio151o_pins: gpio151o-pins { + pins = "GPIO151/MMC_DT7"; + bias-disable; + output-high; + }; + gpio151ol_pins: gpio151ol-pins { + pins = "GPIO151/MMC_DT7"; + bias-disable; + output-low; + }; + gpio152_pins: gpio152-pins { + pins = "GPIO152/MMC_CLK"; + bias-disable; + input-enable; + }; + gpio152o_pins: gpio152o-pins { + pins = "GPIO152/MMC_CLK"; + bias-disable; + output-high; + }; + gpio152ol_pins: gpio152ol-pins { + pins = "GPIO152/MMC_CLK"; + bias-disable; + output-low; + }; + gpio153_pins: gpio153-pins { + pins = "GPIO153/MMC_WP"; + bias-disable; + input-enable; + }; + gpio153ol_pins: gpio153ol-pins { + pins = "GPIO153/MMC_WP"; + bias-disable; + output-low; + }; + gpio154_pins: gpio154-pins { + pins = "GPIO154/MMC_CMD"; + bias-disable; + input-enable; + }; + gpio154ol_pins: gpio154ol-pins { + pins = "GPIO154/MMC_CMD"; + bias-disable; + output-low; + }; + gpio155_pins: gpio155-pins { + pins = "GPIO155/MMC_nCD/MMC_nRSTLK"; + bias-disable; + input-enable; + }; + gpio155ol_pins: gpio155ol-pins { + pins = "GPIO155/MMC_nCD/MMC_nRSTLK"; + bias-disable; + output-low; + }; + gpio156_pins: gpio156-pins { + pins = "GPIO156/MMC_DT0"; + bias-disable; + input-enable; + }; + gpio156ol_pins: gpio156ol-pins { + pins = "GPIO156/MMC_DT0"; + bias-disable; + output-low; + }; + gpio157_pins: gpio157-pins { + pins = "GPIO157/MMC_DT1"; + bias-disable; + input-enable; + }; + gpio157o_pins: gpio157o-pins { + pins = "GPIO157/MMC_DT1"; + bias-disable; + output-high; + }; + gpio157ol_pins: gpio157ol-pins { + pins = "GPIO157/MMC_DT1"; + bias-disable; + output-low; + }; + gpio158_pins: gpio158-pins { + pins = "GPIO158/MMC_DT2"; + bias-disable; + input-enable; + }; + gpio158o_pins: gpio158o-pins { + pins = "GPIO158/MMC_DT2"; + bias-disable; + output-high; + }; + gpio158ol_pins: gpio158ol-pins { + pins = "GPIO158/MMC_DT2"; + bias-disable; + output-low; + }; + gpio159_pins: gpio159-pins { + pins = "GPIO159/MMC_DT3"; + bias-disable; + input-enable; + }; + gpio159o_pins: gpio159o-pins { + pins = "GPIO159/MMC_DT3"; + bias-disable; + output-high; + }; + gpio159ol_pins: gpio159ol-pins { + pins = "GPIO159/MMC_DT3"; + bias-disable; + output-low; + }; + gpio160_pins: gpio160-pins { + pins = "GPIO160/CLKOUT/RNGOSCOUT/GFXBYPCK"; + bias-disable; + input-enable; + }; + gpio160o_pins: gpio160o-pins { + pins = "GPIO160/CLKOUT/RNGOSCOUT/GFXBYPCK"; + bias-disable; + output-high; + }; + gpio160ol_pins: gpio160ol-pins { + pins = "GPIO160/CLKOUT/RNGOSCOUT/GFXBYPCK"; + bias-disable; + output-low; + }; + gpio161_pins: gpio161-pins { + pins = "GPIO161/ESPI_nCS/LPC_nLFRAME"; + bias-disable; + input-enable; + }; + gpio162_pins: gpio162-pins { + pins = "GPIO162/LPC_nCLKRUN"; + bias-disable; + input-enable; + }; + gpio162o_pins: gpio162o-pins { + pins = "GPIO162/LPC_nCLKRUN"; + bias-disable; + output-high; + }; + gpio163_pins: gpio163-pins { + pins = "GPIO163/ESPI_CK/LPC_LCLK"; + bias-disable; + input-enable; + }; + gpio164_pins: gpio164-pins { + pins = "GPIO164/ESPI_IO0/LPC_LAD0"; + bias-disable; + input-enable; + }; + gpio165_pins: gpio165-pins { + pins = "GPIO165/ESPI_IO1/LPC_LAD1"; + bias-disable; + input-enable; + }; + gpio166_pins: gpio166-pins { + pins = "GPIO166/ESPI_IO2/LPC_LAD2"; + bias-disable; + input-enable; + }; + gpio167_pins: gpio167-pins { + pins = "GPIO167/ESPI_IO3/LPC_LAD3"; + bias-disable; + input-enable; + }; + gpio168_pins: gpio168-pins { + pins = "GPIO168/ESPI_nALERT/SERIRQ"; + bias-disable; + input-enable; + drive-open-drain; + }; + gpio168ol_pins: gpio168ol-pins { + pins = "GPIO168/ESPI_nALERT/SERIRQ"; + bias-disable; + output-low; + }; + gpio169_pins: gpio169-pins { + pins = "GPIO169/nSCIPME/SMB21_SCL"; + bias-disable; + input-enable; + }; + gpio169o_pins: gpio169o-pins { + pins = "GPIO169/nSCIPME/SMB21_SCL"; + bias-disable; + output-high; + }; + gpio169ol_pins: gpio169ol-pins { + pins = "GPIO169/nSCIPME/SMB21_SCL"; + bias-disable; + output-low; + }; + gpio170_pins: gpio170-pins { + pins = "GPIO170/nSMI/SMB21_SDA"; + bias-disable; + input-enable; + }; + gpio170ol_pins: gpio170ol-pins { + pins = "GPIO170/nSMI/SMB21_SDA"; + bias-disable; + output-low; + }; + gpio173o_pins: gpio173o-pins { + pins = "GPIO173/SMB7_SCL"; + bias-disable; + output-high; + }; + gpio173ol_pins: gpio173ol-pins { + pins = "GPIO173/SMB7_SCL"; + bias-disable; + output-low; + }; + gpio174_pins: gpio174-pins { + pins = "GPIO174/SMB7_SDA"; + bias-disable; + input-enable; + }; + gpio175_pins: gpio175-pins { + pins = "GPIO175/SPI1_CK/FANIN19/FM1_CK"; + bias-disable; + input-enable; + }; + gpio175o_pins: gpio175o-pins { + pins = "GPIO175/SPI1_CK/FANIN19/FM1_CK"; + bias-disable; + output-high; + }; + gpio175ol_pins: gpio175ol-pins { + pins = "GPIO175/SPI1_CK/FANIN19/FM1_CK"; + bias-disable; + output-low; + }; + gpio176_pins: gpio176-pins { + pins = "GPIO176/SPI1_DO/FANIN18/FM1_DO/STRAP9"; + bias-disable; + input-enable; + }; + gpio176o_pins: gpio176o-pins { + pins = "GPIO176/SPI1_DO/FANIN18/FM1_DO/STRAP9"; + bias-disable; + output-high; + }; + gpio176ol_pins: gpio176ol-pins { + pins = "GPIO176/SPI1_DO/FANIN18/FM1_DO/STRAP9"; + bias-disable; + output-low; + }; + gpio177_pins: gpio177-pins { + pins = "GPIO177/SPI1_DI/FANIN17/FM1_D1/STRAP10"; + bias-disable; + input-enable; + }; + gpio177o_pins: gpio177o-pins { + pins = "GPIO177/SPI1_DI/FANIN17/FM1_D1/STRAP10"; + bias-disable; + output-high; + }; + gpio177ol_pins: gpio177ol-pins { + pins = "GPIO177/SPI1_DI/FANIN17/FM1_D1/STRAP10"; + bias-disable; + output-low; + }; + gpio187_pins: gpio187-pins { + pins = "GPIO187/SPI3_nCS1_SMB14_SDA"; + bias-disable; + input-enable; + }; + gpio187o_pins: gpio187o-pins { + pins = "GPIO187/SPI3_nCS1_SMB14_SDA"; + bias-disable; + output-high; + }; + gpio187ol_pins: gpio187ol-pins { + pins = "GPIO187/SPI3_nCS1_SMB14_SDA"; + bias-disable; + output-low; + }; + gpio188_pins: gpio188-pins { + pins = "GPIO188/SPI3_D2/SPI3_nCS2"; + bias-disable; + input-enable; + }; + gpio188o_pins: gpio188o-pins { + pins = "GPIO188/SPI3_D2/SPI3_nCS2"; + bias-disable; + output-high; + }; + gpio189o_pins: gpio189o-pins { + pins = "GPIO189/SPI3_D3/SPI3_nCS3"; + bias-disable; + output-high; + }; + gpio190_pins: gpio190-pins { + pins = "GPIO190/nPRD_SMI"; + bias-disable; + input-enable; + }; + gpio190o_pins: gpio190o-pins { + pins = "GPIO190/nPRD_SMI"; + bias-disable; + output-high; + }; + gpio190ol_pins: gpio190ol-pins { + pins = "GPIO190/nPRD_SMI"; + bias-disable; + output-low; + }; + gpio191o_pins: gpio191o-pins { + pins = "GPIO191/SPI1_D1/FANIN17/FM1_D1/STRAP10"; + bias-disable; + output-high; + }; + gpio191ol_pins: gpio191ol-pins { + pins = "GPIO191/SPI1_D1/FANIN17/FM1_D1/STRAP10"; + bias-disable; + output-low; + }; + gpio192_pins: gpio192-pins { + pins = "GPIO192/SPI1_D3/SPI_nCS3/FM1_D3/SMB15_SCL"; + bias-disable; + input-enable; + }; + gpio192o_pins: gpio192o-pins { + pins = "GPIO192/SPI1_D3/SPI_nCS3/FM1_D3/SMB15_SCL"; + bias-disable; + output-high; + }; + gpio192ol_pins: gpio192ol-pins { + pins = "GPIO192/SPI1_D3/SPI_nCS3/FM1_D3/SMB15_SCL"; + bias-disable; + output-low; + }; + gpio194_pins: gpio194-pins { + pins = "GPIO194/SMB0B_SCL/FM0_CK"; + bias-disable; + input-enable; + }; + gpio194o_pins: gpio194o-pins { + pins = "GPIO194/SMB0B_SCL/FM0_CK"; + bias-disable; + output-high; + }; + gpio195_pins: gpio195-pins { + pins = "GPIO195/SMB0B_SDA/FM0_D0"; + bias-disable; + input-enable; + }; + gpio196_pins: gpio196-pins { + pins = "GPIO196/SMB0C_SCL/FM0_D1"; + bias-disable; + input-enable; + }; + gpio196o_pins: gpio196o-pins { + pins = "GPIO196/SMB0C_SCL/FM0_D1"; + bias-disable; + output-high; + }; + gpio197_pins: gpio197-pins { + pins = "GPIO197/SMB0DEN/FM0_D3"; + bias-disable; + input-enable; + }; + gpio197o_pins: gpio197o-pins { + pins = "GPIO197/SMB0DEN/FM0_D3"; + bias-disable; + output-high; + }; + gpio197ol_pins: gpio197ol-pins { + pins = "GPIO197/SMB0DEN/FM0_D3"; + bias-disable; + output-low; + }; + gpio198o_pins: gpio198o-pins { + pins = "GPIO198/SMB0D_SDA/FM0_D2"; + bias-disable; + output-high; + }; + gpio198ol_pins: gpio198ol-pins { + pins = "GPIO198/SMB0D_SDA/FM0_D2"; + bias-disable; + output-low; + }; + gpio199_pins: gpio199-pins { + pins = "GPIO199/SMB0D_SCL/FM0_CSO"; + bias-disable; + input-enable; + }; + gpio200_pins: gpio200-pins { + pins = "GPIO200/R2_CK"; + input-enable; + bias-disable; + }; + gpio200ol_pins: gpio200ol-pins { + pins = "GPIO200/R2_CK"; + bias-disable; + output-low; + }; + gpio201ol_pins: gpio201ol-pins { + pins = "GPIO201/R1_CK"; + bias-disable; + output-low; + }; + gpio202_pins: gpio202-pins { + pins = "GPIO202/SMB0C_SDA/FM0_CSI"; + bias-disable; + input-enable; + }; + gpio203_pins: gpio203-pins { + pins = "GPIO203/SPI1_nCS0/FANIN16/FM1_CSI"; + bias-disable; + input-enable; + }; + gpio203o_pins: gpio203o-pins { + pins = "GPIO203/SPI1_nCS0/FANIN16/FM1_CSI"; + bias-disable; + output-high; + }; + gpio203ol_pins: gpio203ol-pins { + pins = "GPIO203/SPI1_nCS0/FANIN16/FM1_CSI"; + bias-disable; + output-low; + }; + gpio208_pins: gpio208-pins { + pins = "GPIO208/RG2_TXC/DVCK"; + bias-disable; + input-enable; + }; + gpio208o_pins: gpio208o-pins { + pins = "GPIO208/RG2_TXC/DVCK"; + bias-disable; + output-high; + }; + gpio208ol_pins: gpio208ol-pins { + pins = "GPIO208/RG2_TXC/DVCK"; + bias-disable; + output-low; + }; + gpio209_pins: gpio209-pins { + pins = "GPIO209/RG2_TXCTL/DDRV4/R3_TXEN"; + bias-disable; + input-enable; + }; + gpio209ol_pins: gpio209ol-pins { + pins = "GPIO209/RG2_TXCTL/DDRV4/R3_TXEN"; + bias-disable; + output-low; + }; + gpio210_pins: gpio210-pins { + pins = "GPIO210/RG2_RXD0/DDRV5/R3_RXD0"; + bias-disable; + input-enable; + }; + gpio210o_pins: gpio210o-pins { + pins = "GPIO210/RG2_RXD0/DDRV5/R3_RXD0"; + bias-disable; + output-high; + }; + gpio210ol_pins: gpio210ol-pins { + pins = "GPIO210/RG2_RXD0/DDRV5/R3_RXD0"; + bias-disable; + output-low; + }; + gpio211_pins: gpio211-pins { + pins = "GPIO211/RG2_RXD1/DDRV6/R3_RXD1"; + bias-disable; + input-enable; + }; + gpio211o_pins: gpio211o-pins { + pins = "GPIO211/RG2_RXD1/DDRV6/R3_RXD1"; + bias-disable; + output-high; + }; + gpio211ol_pins: gpio211ol-pins { + pins = "GPIO211/RG2_RXD1/DDRV6/R3_RXD1"; + bias-disable; + output-low; + }; + gpio212_pins: gpio212-pins { + pins = "GPIO212/RG2_RXD2/DDRV7/R3_RXD2"; + bias-disable; + input-enable; + }; + gpio212o_pins: gpio212o-pins { + pins = "GPIO212/RG2_RXD2/DDRV7/R3_RXD2"; + bias-disable; + output-high; + }; + gpio212ol_pins: gpio212ol-pins { + pins = "GPIO212/RG2_RXD2/DDRV7/R3_RXD2"; + bias-disable; + output-low; + }; + gpio213_pins: gpio213-pins { + pins = "GPIO213/RG2_RXD3/DDRV8/R3_OEN"; + bias-disable; + input-enable; + }; + gpio213o_pins: gpio213o-pins { + pins = "GPIO213/RG2_RXD3/DDRV8/R3_OEN"; + bias-disable; + output-high; + }; + gpio213ol_pins: gpio213ol-pins { + pins = "GPIO213/RG2_RXD3/DDRV8/R3_OEN"; + bias-disable; + output-low; + }; + gpio214_pins: gpio214-pins { + pins = "GPIO214/RG2_RXC/DDRV9/R3_CK"; + bias-disable; + input-enable; + }; + gpio214ol_pins: gpio214ol-pins { + pins = "GPIO214/RG2_RXC/DDRV9/R3_CK"; + bias-disable; + output-low; + }; + gpio215_pins: gpio215-pins { + pins = "GPIO215/RG2_RXCTL/DDRV10/R3_CRSDV"; + bias-disable; + input-enable; + }; + gpio215ol_pins: gpio215ol-pins { + pins = "GPIO215/RG2_RXCTL/DDRV10/R3_CRSDV"; + bias-disable; + output-low; + }; + gpio216_pins: gpio216-pins { + pins = "GPIO216/RG2_MDC/DDRV11"; + bias-disable; + input-enable; + }; + gpio216ol_pins: gpio216ol-pins { + pins = "GPIO216/RG2_MDC/DDRV11"; + bias-disable; + output-low; + }; + gpio217_pins: gpio217-pins { + pins = "GPIO217/RG2_MDIO/DVHSYNC"; + bias-disable; + input-enable; + }; + gpio217ol_pins: gpio217ol-pins { + pins = "GPIO217/RG2_MDIO/DVHSYNC"; + bias-disable; + output-low; + }; + gpio218_pins: gpio218-pins { + pins = "GPIO218/nWDO1/SMB16_SCL"; + bias-disable; + input-enable; + }; + gpio218ol_pins: gpio218ol-pins { + pins = "GPIO218/nWDO1/SMB16_SCL"; + bias-disable; + output-low; + }; + gpio219_pins: gpio219-pins { + pins = "GPIO219/nWDO2/SMB16_SDA"; + bias-disable; + input-enable; + }; + gpio219ol_pins: gpio219ol-pins { + pins = "GPIO219/nWDO2/SMB16_SDA"; + bias-disable; + output-low; + }; + gpio220ol_pins: gpio220ol-pins { + pins = "GPIO220/SMB12_SCL/PWM8"; + bias-disable; + output-low; + }; + gpio221o_pins: gpio221o-pins { + pins = "GPIO221/SMB12_SDA/PWM9"; + bias-disable; + output-high; + }; + gpio222_pins: gpio222-pins { + pins = "GPIO222/SMB13_SCL"; + bias-disable; + input-enable; + }; + gpio222o_pins: gpio222o-pins { + pins = "GPIO222/SMB13_SCL"; + bias-disable; + output-high; + }; + gpio223_pins: gpio223-pins { + pins = "GPIO223/SMB13_SDA"; + bias-disable; + input-enable; + }; + gpio223ol_pins: gpio223ol-pins { + pins = "GPIO223/SMB13_SDA"; + bias-disable; + output-low; + }; + gpio224_pins: gpio224-pins { + pins = "GPIO224/SPIX_CK/FM2_CK"; + bias-disable; + input-enable; + }; + gpio224o_pins: gpio224o-pins { + pins = "GPIO224/SPIX_CK/FM2_CK"; + bias-disable; + output-high; + }; + gpio224ol_pins: gpio224ol-pins { + pins = "GPIO224/SPIX_CK/FM2_CK"; + bias-disable; + output-low; + }; + gpio225_pins: gpio225-pins { + pins = "GPO225/SPIX_D0/FM2_D0/STRAP1"; + bias-disable; + input-enable; + }; + gpio225o_pins: gpio225o-pins { + pins = "GPO225/SPIX_D0/FM2_D0/STRAP1"; + bias-disable; + output-high; + }; + gpio226_pins: gpio226-pins { + pins = "GPO226/SPIX_D1/FM2_D1/STRAP2"; + bias-disable; + input-enable; + }; + gpio226o_pins: gpio226o-pins { + pins = "GPO226/SPIX_D1/FM2_D1/STRAP2"; + bias-disable; + output-high; + }; + gpio227_pins: gpio227-pins { + pins = "GPIO227/SPIX_nCS0/FM2_CSI"; + bias-disable; + input-enable; + }; + gpio227o_pins: gpio227o-pins { + pins = "GPIO227/SPIX_nCS0/FM2_CSI"; + bias-disable; + output-high; + }; + gpio227ol_pins: gpio227ol-pins { + pins = "GPIO227/SPIX_nCS0/FM2_CSI"; + bias-disable; + output-low; + }; + gpio228_pins: gpio228-pins { + pins = "GPIO228/SPIX_nCS1/FM2_CSO"; + bias-disable; + input-enable; + }; + gpio228ol_pins: gpio228ol-pins { + pins = "GPIO228/SPIX_nCS1/FM2_CSO"; + bias-disable; + output-low; + }; + gpio229_pins: gpio229-pins { + pins = "GPO229/SPIX_D2/FM2_D2/STRAP3"; + bias-disable; + input-enable; + }; + gpio229o_pins: gpio229o-pins { + pins = "GPO229/SPIX_D2/FM2_D2/STRAP3"; + bias-disable; + output-high; + }; + gpio230_pins: gpio230-pins { + pins = "GPO230/SPIX_D3/FM2_D3/STRAP6"; + bias-disable; + input-enable; + }; + gpio230o_pins: gpio230o-pins { + pins = "GPO230/SPIX_D3/FM2_D3/STRAP6"; + bias-disable; + output-high; + }; + gpio230ol_pins: gpio230ol-pins { + pins = "GPO230/SPIX_D3/FM2_D3/STRAP6"; + bias-disable; + output-low; + }; + gpio231_pins: gpio231-pins { + pins = "GPIO231/EP_nCLKREQ"; + bias-disable; + input-enable; + }; + gpio231o_pins: gpio231o-pins { + pins = "GPIO231/EP_nCLKREQ"; + bias-disable; + output-high; + }; + }; +}; diff --git a/arch/arm/dts/nuvoton-npcm8xx-u-boot.dtsi b/arch/arm/dts/nuvoton-npcm8xx-u-boot.dtsi index f5f1ce669b..d21e5042a6 100644 --- a/arch/arm/dts/nuvoton-npcm8xx-u-boot.dtsi +++ b/arch/arm/dts/nuvoton-npcm8xx-u-boot.dtsi @@ -59,6 +59,174 @@ clocks = <&clk_refclk>; }; + ehci1: usb@f0828100 { + compatible = "nuvoton,npcm845-ehci"; + reg = <0x0 0xf0828100 0x0 0x1000>; + interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; + resets = <&rstc2 NPCM8XX_RESET_USBH1>; + status = "disabled"; + }; + + ehci2: usb@f082a100 { + compatible = "nuvoton,npcm845-ehci"; + reg = <0x0 0xf082a100 0x0 0x1000>; + interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; + resets = <&rstc4 NPCM8XX_RESET_USBH2>; + status = "disabled"; + }; + + ohci1: usb@f0829000 { + compatible = "nuvoton,npcm845-ohci"; + reg = <0x0 0xF0829000 0x0 0x1000>; + resets = <&rstc2 NPCM8XX_RESET_USBH1>; + status = "disabled"; + }; + + ohci2: usb@f082b000 { + compatible = "nuvoton,npcm845-ohci"; + reg = <0x0 0xF082B000 0x0 0x1000>; + resets = <&rstc4 NPCM8XX_RESET_USBH2>; + status = "disabled"; + }; + + usbphy { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + syscon = <&gcr>; + usbphy1: usbphy@1 { + compatible = "nuvoton,npcm845-usb-phy"; + #phy-cells = <1>; + reg = <1>; + resets = <&rstc3 NPCM8XX_RESET_USBPHY1>; + status = "disabled"; + }; + usbphy2: usbphy@2 { + compatible = "nuvoton,npcm845-usb-phy"; + #phy-cells = <1>; + reg = <2>; + resets = <&rstc3 NPCM8XX_RESET_USBPHY2>; + status = "disabled"; + }; + usbphy3: usbphy@3 { + compatible = "nuvoton,npcm845-usb-phy"; + #phy-cells = <1>; + reg = <3>; + resets = <&rstc3 NPCM8XX_RESET_USBPHY3>; + status = "disabled"; + }; + }; + + udc0:udc@f0830100 { + compatible = "nuvoton,npcm845-udc"; + reg = <0x0 0xf0830100 0x0 0x100 + 0x0 0xfffb0000 0x0 0x800>; + interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk NPCM8XX_CLK_SU>; + clock-names = "clk_usb_bridge"; + resets = <&rstc3 NPCM8XX_RESET_UDC0>; + status = "disable"; + }; + + udc1:udc@f0831100 { + compatible = "nuvoton,npcm845-udc"; + reg = <0x0 0xf0831100 0x0 0x100 + 0x0 0xfffb0800 0x0 0x800>; + interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk NPCM8XX_CLK_SU>; + clock-names = "clk_usb_bridge"; + resets = <&rstc1 NPCM8XX_RESET_UDC1>; + status = "disable"; + }; + + udc2:udc@f0832100 { + compatible = "nuvoton,npcm845-udc"; + reg = <0x0 0xf0832100 0x0 0x100 + 0x0 0xfffb1000 0x0 0x800>; + interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk NPCM8XX_CLK_SU>; + clock-names = "clk_usb_bridge"; + resets = <&rstc1 NPCM8XX_RESET_UDC2>; + status = "disable"; + }; + + udc3:udc@f0833100 { + compatible = "nuvoton,npcm845-udc"; + reg = <0x0 0xf0833100 0x0 0x100 + 0x0 0xfffb1800 0x0 0x800>; + interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk NPCM8XX_CLK_SU>; + clock-names = "clk_usb_bridge"; + resets = <&rstc1 NPCM8XX_RESET_UDC3>; + status = "disable"; + }; + + udc4:udc@f0834100 { + compatible = "nuvoton,npcm845-udc"; + reg = <0x0 0xf0834100 0x0 0x100 + 0x0 0xfffb2000 0x0 0x800>; + interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk NPCM8XX_CLK_SU>; + clock-names = "clk_usb_bridge"; + resets = <&rstc1 NPCM8XX_RESET_UDC4>; + status = "disable"; + }; + + udc5:udc@f0835100 { + compatible = "nuvoton,npcm845-udc"; + reg = <0x0 0xf0835100 0x0 0x100 + 0x0 0xfffb2800 0x0 0x800>; + interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk NPCM8XX_CLK_SU>; + clock-names = "clk_usb_bridge"; + resets = <&rstc1 NPCM8XX_RESET_UDC5>; + status = "disable"; + }; + + udc6:udc@f0836100 { + compatible = "nuvoton,npcm845-udc"; + reg = <0x0 0xf0836100 0x0 0x100 + 0x0 0xfffb3000 0x0 0x800>; + interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk NPCM8XX_CLK_SU>; + clock-names = "clk_usb_bridge"; + resets = <&rstc1 NPCM8XX_RESET_UDC6>; + status = "disable"; + }; + + udc7:udc@f0837100 { + compatible = "nuvoton,npcm845-udc"; + reg = <0x0 0xf0837100 0x0 0x100 + 0x0 0xfffb3800 0x0 0x800>; + interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk NPCM8XX_CLK_SU>; + clock-names = "clk_usb_bridge"; + resets = <&rstc3 NPCM8XX_RESET_UDC7>; + status = "disable"; + }; + + udc8:udc@f0838100 { + compatible = "nuvoton,npcm845-udc"; + reg = <0x0 0xf0838100 0x0 0x100 + 0x0 0xfffb4000 0x0 0x800>; + interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk NPCM8XX_CLK_SU>; + clock-names = "clk_usb_bridge"; + resets = <&rstc3 NPCM8XX_RESET_UDC8>; + status = "disable"; + }; + + udc9:udc@f0839100 { + compatible = "nuvoton,npcm845-udc"; + reg = <0x0 0xf0839100 0x0 0x100 + 0x0 0xfffb4800 0x0 0x800>; + interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk NPCM8XX_CLK_SU>; + clock-names = "clk_usb_bridge"; + resets = <&rstc3 NPCM8XX_RESET_UDC9>; + status = "disable"; + }; + apb { serial0: serial@0 { compatible = "nuvoton,npcm845-uart"; @@ -69,7 +237,7 @@ }; gpio0: gpio0@10000 { - compatible = "nuvoton,npcm-gpio"; + compatible = "nuvoton,npcm-gpio", "nuvoton,npcm845-gpio"; reg = <0x10000 0xB0>; #gpio-cells = <2>; gpio-controller; @@ -77,7 +245,7 @@ }; gpio1: gpio1@11000 { - compatible = "nuvoton,npcm-gpio"; + compatible = "nuvoton,npcm-gpio", "nuvoton,npcm845-gpio"; reg = <0x11000 0xB0>; #gpio-cells = <2>; gpio-controller; @@ -85,7 +253,7 @@ }; gpio2: gpio2@12000 { - compatible = "nuvoton,npcm-gpio"; + compatible = "nuvoton,npcm-gpio", "nuvoton,npcm845-gpio"; reg = <0x12000 0xB0>; #gpio-cells = <2>; gpio-controller; @@ -93,7 +261,7 @@ }; gpio3: gpio3@13000 { - compatible = "nuvoton,npcm-gpio"; + compatible = "nuvoton,npcm-gpio", "nuvoton,npcm845-gpio"; reg = <0x13000 0xB0>; #gpio-cells = <2>; gpio-controller; @@ -101,7 +269,7 @@ }; gpio4: gpio4@14000 { - compatible = "nuvoton,npcm-gpio"; + compatible = "nuvoton,npcm-gpio", "nuvoton,npcm845-gpio"; reg = <0x14000 0xB0>; #gpio-cells = <2>; gpio-controller; @@ -109,7 +277,7 @@ }; gpio5: gpio5@15000 { - compatible = "nuvoton,npcm-gpio"; + compatible = "nuvoton,npcm-gpio", "nuvoton,npcm845-gpio"; reg = <0x15000 0xB0>; #gpio-cells = <2>; gpio-controller; @@ -117,7 +285,7 @@ }; gpio6: gpio6@16000 { - compatible = "nuvoton,npcm-gpio"; + compatible = "nuvoton,npcm-gpio", "nuvoton,npcm845-gpio"; reg = <0x16000 0xB0>; #gpio-cells = <2>; gpio-controller; @@ -125,7 +293,7 @@ }; gpio7: gpio7@17000 { - compatible = "nuvoton,npcm-gpio"; + compatible = "nuvoton,npcm-gpio", "nuvoton,npcm845-gpio"; reg = <0x17000 0xB0>; #gpio-cells = <2>; gpio-controller; @@ -133,4 +301,652 @@ }; }; }; + pinctrl: pinctrl@f0800000 { + compatible = "nuvoton,npcm845-pinctrl", "syscon", "simple-mfd"; + reg = <0x0 0xf0010000 0x0 0x8000>; + syscon-gcr = <&gcr>; + syscon-rst = <&rstc>; + status = "okay"; + + iox1_pins: iox1-pins { + groups = "iox1"; + function = "iox1"; + }; + iox2_pins: iox2-pins { + groups = "iox2"; + function = "iox2"; + }; + smb1d_pins: smb1d-pins { + groups = "smb1d"; + function = "smb1d"; + }; + smb2d_pins: smb2d-pins { + groups = "smb2d"; + function = "smb2d"; + }; + lkgpo1_pins: lkgpo1-pins { + groups = "lkgpo1"; + function = "lkgpo1"; + }; + lkgpo2_pins: lkgpo2-pins { + groups = "lkgpo2"; + function = "lkgpo2"; + }; + ioxh_pins: ioxh-pins { + groups = "ioxh"; + function = "ioxh"; + }; + gspi_pins: gspi-pins { + groups = "gspi"; + function = "gspi"; + }; + smb5b_pins: smb5b-pins { + groups = "smb5b"; + function = "smb5b"; + }; + smb5c_pins: smb5c-pins { + groups = "smb5c"; + function = "smb5c"; + }; + lkgpo0_pins: lkgpo0-pins { + groups = "lkgpo0"; + function = "lkgpo0"; + }; + pspi_pins: pspi-pins { + groups = "pspi"; + function = "pspi"; + }; + vgadig_pins: vgadig-pins { + groups = "vgadig"; + function = "vgadig"; + }; + jm1_pins: jm1-pins { + groups = "jm1"; + function = "jm1"; + }; + jm2_pins: jm2-pins { + groups = "jm2"; + function = "jm2"; + }; + smb4b_pins: smb4b-pins { + groups = "smb4b"; + function = "smb4b"; + }; + smb4c_pins: smb4c-pins { + groups = "smb4c"; + function = "smb4c"; + }; + smb15_pins: smb15-pins { + groups = "smb15"; + function = "smb15"; + }; + smb16_pins: smb16-pins { + groups = "smb16"; + function = "smb16"; + }; + smb17_pins: smb17-pins { + groups = "smb17"; + function = "smb17"; + }; + smb18_pins: smb18-pins { + groups = "smb18"; + function = "smb18"; + }; + smb19_pins: smb19-pins { + groups = "smb19"; + function = "smb19"; + }; + smb20_pins: smb20-pins { + groups = "smb20"; + function = "smb20"; + }; + smb21_pins: smb21-pins { + groups = "smb21"; + function = "smb21"; + }; + smb22_pins: smb22-pins { + groups = "smb22"; + function = "smb22"; + }; + smb23_pins: smb23-pins { + groups = "smb23"; + function = "smb23"; + }; + smb4d_pins: smb4d-pins { + groups = "smb4d"; + function = "smb4d"; + }; + smb14_pins: smb14-pins { + groups = "smb14"; + function = "smb14"; + }; + smb5_pins: smb5-pins { + groups = "smb5"; + function = "smb5"; + }; + smb4_pins: smb4-pins { + groups = "smb4"; + function = "smb4"; + }; + smb3_pins: smb3-pins { + groups = "smb3"; + function = "smb3"; + }; + spi0cs1_pins: spi0cs1-pins { + groups = "spi0cs1"; + function = "spi0cs1"; + }; + spi0cs2_pins: spi0cs2-pins { + groups = "spi0cs2"; + function = "spi0cs2"; + }; + spi0cs3_pins: spi0cs3-pins { + groups = "spi0cs3"; + function = "spi0cs3"; + }; + smb3c_pins: smb3c-pins { + groups = "smb3c"; + function = "smb3c"; + }; + smb3b_pins: smb3b-pins { + groups = "smb3b"; + function = "smb3b"; + }; + hsi1a_pins: hsi1a-pins { + groups = "hsi1a"; + function = "hsi1a"; + }; + hsi1b_pins: hsi1b-pins { + groups = "hsi1b"; + function = "hsi1b"; + }; + hsi1c_pins: hsi1c-pins { + groups = "hsi1c"; + function = "hsi1c"; + }; + hsi2a_pins: hsi2a-pins { + groups = "hsi2a"; + function = "hsi2a"; + }; + hsi2b_pins: hsi2b-pins { + groups = "hsi2b"; + function = "hsi2b"; + }; + hsi2c_pins: hsi2c-pins { + groups = "hsi2c"; + function = "hsi2c"; + }; + bmcuart0a_pins: bmcuart0a-pins { + groups = "bmcuart0a"; + function = "bmcuart0a"; + }; + bmcuart0b_pins: bmcuart0b-pins { + groups = "bmcuart0b"; + function = "bmcuart0b"; + }; + bmcuart1_pins: bmcuart1-pins { + groups = "bmcuart1"; + function = "bmcuart1"; + }; + bu4_pins: bu4-pins { + groups = "bu4"; + function = "bu4"; + }; + bu5_pins: bu5-pins { + groups = "bu5"; + function = "bu5"; + }; + bu6_pins: bu6-pins { + groups = "bu6"; + function = "bu6"; + }; + r1err_pins: r1err-pins { + groups = "r1err"; + function = "r1err"; + }; + r1md_pins: r1md-pins { + groups = "r1md"; + function = "r1md"; + }; + r1oen_pins: r1oen-pins { + groups = "r1oen"; + function = "r1oen"; + }; + r1en_pins: r1en-pins { + groups = "r1en"; + function = "r1en"; + }; + r2oen_pins: r2oen-pins { + groups = "r2oen"; + function = "r2oen"; + }; + r2en_pins: r2en-pins { + groups = "r2en"; + function = "r2en"; + }; + rmii3_pins: rmii3_pins { + groups = "rmii3"; + function = "rmii3"; + }; + r3oen_pins: r3oen-pins { + groups = "r3oen"; + function = "r3oen"; + }; + r3en_pins: r3en-pins { + groups = "r3en"; + function = "r3en"; + }; + smb3d_pins: smb3d-pins { + groups = "smb3d"; + function = "smb3d"; + }; + fanin0_pins: fanin0-pins { + groups = "fanin0"; + function = "fanin0"; + }; + fanin1_pins: fanin1-pins { + groups = "fanin1"; + function = "fanin1"; + }; + fanin2_pins: fanin2-pins { + groups = "fanin2"; + function = "fanin2"; + }; + fanin3_pins: fanin3-pins { + groups = "fanin3"; + function = "fanin3"; + }; + fanin4_pins: fanin4-pins { + groups = "fanin4"; + function = "fanin4"; + }; + fanin5_pins: fanin5-pins { + groups = "fanin5"; + function = "fanin5"; + }; + fanin6_pins: fanin6-pins { + groups = "fanin6"; + function = "fanin6"; + }; + fanin7_pins: fanin7-pins { + groups = "fanin7"; + function = "fanin7"; + }; + fanin8_pins: fanin8-pins { + groups = "fanin8"; + function = "fanin8"; + }; + fanin9_pins: fanin9-pins { + groups = "fanin9"; + function = "fanin9"; + }; + fanin10_pins: fanin10-pins { + groups = "fanin10"; + function = "fanin10"; + }; + fanin11_pins: fanin11-pins { + groups = "fanin11"; + function = "fanin11"; + }; + fanin12_pins: fanin12-pins { + groups = "fanin12"; + function = "fanin12"; + }; + fanin13_pins: fanin13-pins { + groups = "fanin13"; + function = "fanin13"; + }; + fanin14_pins: fanin14-pins { + groups = "fanin14"; + function = "fanin14"; + }; + fanin15_pins: fanin15-pins { + groups = "fanin15"; + function = "fanin15"; + }; + pwm0_pins: pwm0-pins { + groups = "pwm0"; + function = "pwm0"; + }; + pwm1_pins: pwm1-pins { + groups = "pwm1"; + function = "pwm1"; + }; + pwm2_pins: pwm2-pins { + groups = "pwm2"; + function = "pwm2"; + }; + pwm3_pins: pwm3-pins { + groups = "pwm3"; + function = "pwm3"; + }; + r2_pins: r2-pins { + groups = "r2"; + function = "r2"; + }; + r2err_pins: r2err-pins { + groups = "r2err"; + function = "r2err"; + }; + r2md_pins: r2md-pins { + groups = "r2md"; + function = "r2md"; + }; + r3rxer_pins: r3rxer_pins { + groups = "r3rxer"; + function = "r3rxer"; + }; + ga20kbc_pins: ga20kbc-pins { + groups = "ga20kbc"; + function = "ga20kbc"; + }; + smb5d_pins: smb5d-pins { + groups = "smb5d"; + function = "smb5d"; + }; + lpc_pins: lpc-pins { + groups = "lpc"; + function = "lpc"; + }; + espi_pins: espi-pins { + groups = "espi"; + function = "espi"; + }; + rg1_pins: rg1-pins { + groups = "rg1"; + function = "rg1"; + }; + rg1mdio_pins: rg1mdio-pins { + groups = "rg1mdio"; + function = "rg1mdio"; + }; + rg2_pins: rg2-pins { + groups = "rg2"; + function = "rg2"; + }; + ddr_pins: ddr-pins { + groups = "ddr"; + function = "ddr"; + }; + i3c0_pins: i3c0-pins { + groups = "i3c0"; + function = "i3c0"; + }; + i3c1_pins: i3c1-pins { + groups = "i3c1"; + function = "i3c1"; + }; + i3c2_pins: i3c2-pins { + groups = "i3c2"; + function = "i3c2"; + }; + i3c3_pins: i3c3-pins { + groups = "i3c3"; + function = "i3c3"; + }; + i3c4_pins: i3c4-pins { + groups = "i3c4"; + function = "i3c4"; + }; + i3c5_pins: i3c5-pins { + groups = "i3c5"; + function = "i3c5"; + }; + smb0_pins: smb0-pins { + groups = "smb0"; + function = "smb0"; + }; + smb1_pins: smb1-pins { + groups = "smb1"; + function = "smb1"; + }; + smb2_pins: smb2-pins { + groups = "smb2"; + function = "smb2"; + }; + smb2c_pins: smb2c-pins { + groups = "smb2c"; + function = "smb2c"; + }; + smb2b_pins: smb2b-pins { + groups = "smb2b"; + function = "smb2b"; + }; + smb1c_pins: smb1c-pins { + groups = "smb1c"; + function = "smb1c"; + }; + smb1b_pins: smb1b-pins { + groups = "smb1b"; + function = "smb1b"; + }; + smb8_pins: smb8-pins { + groups = "smb8"; + function = "smb8"; + }; + smb9_pins: smb9-pins { + groups = "smb9"; + function = "smb9"; + }; + smb10_pins: smb10-pins { + groups = "smb10"; + function = "smb10"; + }; + smb11_pins: smb11-pins { + groups = "smb11"; + function = "smb11"; + }; + sd1_pins: sd1-pins { + groups = "sd1"; + function = "sd1"; + }; + sd1pwr_pins: sd1pwr-pins { + groups = "sd1pwr"; + function = "sd1pwr"; + }; + pwm4_pins: pwm4-pins { + groups = "pwm4"; + function = "pwm4"; + }; + pwm5_pins: pwm5-pins { + groups = "pwm5"; + function = "pwm5"; + }; + pwm6_pins: pwm6-pins { + groups = "pwm6"; + function = "pwm6"; + }; + pwm7_pins: pwm7-pins { + groups = "pwm7"; + function = "pwm7"; + }; + pwm8_pins: pwm8-pins { + groups = "pwm8"; + function = "pwm8"; + }; + pwm9_pins: pwm9-pins { + groups = "pwm9"; + function = "pwm9"; + }; + pwm10_pins: pwm10-pins { + groups = "pwm10"; + function = "pwm10"; + }; + pwm11_pins: pwm11-pins { + groups = "pwm11"; + function = "pwm11"; + }; + mmc8_pins: mmc8-pins { + groups = "mmc8"; + function = "mmc8"; + }; + mmc_pins: mmc-pins { + groups = "mmc"; + function = "mmc"; + }; + mmcwp_pins: mmcwp-pins { + groups = "mmcwp"; + function = "mmcwp"; + }; + mmccd_pins: mmccd-pins { + groups = "mmccd"; + function = "mmccd"; + }; + mmcrst_pins: mmcrst-pins { + groups = "mmcrst"; + function = "mmcrst"; + }; + clkout_pins: clkout-pins { + groups = "clkout"; + function = "clkout"; + }; + serirq_pins: serirq-pins { + groups = "serirq"; + function = "serirq"; + }; + scipme_pins: scipme-pins { + groups = "scipme"; + function = "scipme"; + }; + sci_pins: sci-pins { + groups = "sci"; + function = "sci"; + }; + smb6_pins: smb6-pins { + groups = "smb6"; + function = "smb6"; + }; + smb7_pins: smb7-pins { + groups = "smb7"; + function = "smb7"; + }; + spi1_pins: spi1-pins { + groups = "spi1"; + function = "spi1"; + }; + spi1d23_pins: spi1d23-pins { + groups = "spi1d23"; + function = "spi1d23"; + }; + faninx_pins: faninx-pins { + groups = "faninx"; + function = "faninx"; + }; + r1_pins: r1-pins { + groups = "r1"; + function = "r1"; + }; + spi3_pins: spi3-pins { + groups = "spi3"; + function = "spi3"; + }; + spi3cs1_pins: spi3cs1-pins { + groups = "spi3cs1"; + function = "spi3cs1"; + }; + spi3quad_pins: spi3quad-pins { + groups = "spi3quad"; + function = "spi3quad"; + }; + spi3cs2_pins: spi3cs2-pins { + groups = "spi3cs2"; + function = "spi3cs2"; + }; + spi3cs3_pins: spi3cs3-pins { + groups = "spi3cs3"; + function = "spi3cs3"; + }; + nprd_smi_pins: nprd-smi-pins { + groups = "nprd_smi"; + function = "nprd_smi"; + }; + smb0b_pins: smb0b-pins { + groups = "smb0b"; + function = "smb0b"; + }; + smb0c_pins: smb0c-pins { + groups = "smb0c"; + function = "smb0c"; + }; + smb0den_pins: smb0den-pins { + groups = "smb0den"; + function = "smb0den"; + }; + smb0d_pins: smb0d-pins { + groups = "smb0d"; + function = "smb0d"; + }; + rg2mdio_pins: rg2mdio-pins { + groups = "rg2mdio"; + function = "rg2mdio"; + }; + rg2refck_pins: rg2refck-pins { + groups = "rg2refck"; + function = "rg2refck"; + }; + wdog1_pins: wdog1-pins { + groups = "wdog1"; + function = "wdog1"; + }; + wdog2_pins: wdog2-pins { + groups = "wdog2"; + function = "wdog2"; + }; + smb12_pins: smb12-pins { + groups = "smb12"; + function = "smb12"; + }; + smb13_pins: smb13-pins { + groups = "smb13"; + function = "smb13"; + }; + spix_pins: spix-pins { + groups = "spix"; + function = "spix"; + }; + spixcs1_pins: spixcs1-pins { + groups = "spixcs1"; + function = "spixcs1"; + }; + clkreq_pins: clkreq-pins { + groups = "clkreq"; + function = "clkreq"; + }; + hgpio0_pins: hgpio0-pins { + groups = "hgpio0"; + function = "hgpio0"; + }; + hgpio1_pins: hgpio1-pins { + groups = "hgpio1"; + function = "hgpio1"; + }; + hgpio2_pins: hgpio2-pins { + groups = "hgpio2"; + function = "hgpio2"; + }; + hgpio3_pins: hgpio3-pins { + groups = "hgpio3"; + function = "hgpio3"; + }; + hgpio4_pins: hgpio4-pins { + groups = "hgpio4"; + function = "hgpio4"; + }; + hgpio5_pins: hgpio5-pins { + groups = "hgpio5"; + function = "hgpio5"; + }; + hgpio6_pins: hgpio6-pins { + groups = "hgpio6"; + function = "hgpio6"; + }; + hgpio7_pins: hgpio7-pins { + groups = "hgpio7"; + function = "hgpio7"; + }; + jtag2_pins: jtag2-pins { + groups = "jtag2"; + function = "jtag2"; + }; + }; }; diff --git a/arch/arm/dts/omap4-u-boot.dtsi b/arch/arm/dts/omap4-u-boot.dtsi index 4a6bafd6ed..d476bfbc50 100644 --- a/arch/arm/dts/omap4-u-boot.dtsi +++ b/arch/arm/dts/omap4-u-boot.dtsi @@ -17,6 +17,14 @@ compatible = "simple-bus"; }; }; + + segment@80000 { + /* USB OTG */ + target-module@2b000 { + compatible = "simple-bus"; + }; + }; + }; &l4_per { diff --git a/arch/arm/dts/rockchip-optee.dtsi b/arch/arm/dts/rockchip-optee.dtsi index 328ba90845..d84c10cf43 100644 --- a/arch/arm/dts/rockchip-optee.dtsi +++ b/arch/arm/dts/rockchip-optee.dtsi @@ -32,8 +32,8 @@ arch = "arm"; os = "tee"; compression = "none"; - load = <(CONFIG_SYS_SDRAM_BASE + 0x8400000)>; - entry = <(CONFIG_SYS_SDRAM_BASE + 0x8400000)>; + load = <(CFG_SYS_SDRAM_BASE + 0x8400000)>; + entry = <(CFG_SYS_SDRAM_BASE + 0x8400000)>; blob-ext { filename = "tee.bin"; diff --git a/arch/arm/dts/s5p4418-nanopi2.dts b/arch/arm/dts/s5p4418-nanopi2.dts index 4deaf10a1c..42251e0a05 100644 --- a/arch/arm/dts/s5p4418-nanopi2.dts +++ b/arch/arm/dts/s5p4418-nanopi2.dts @@ -25,6 +25,7 @@ i2c0 = "/i2c@c00a4000"; i2c1 = "/i2c@c00a5000"; i2c2 = "/i2c@c00a6000"; + serial0 = "/uart@c00a1000"; }; mmc0:mmc@c0062000 { @@ -107,4 +108,9 @@ }; }; }; + + uart0:uart@c00a1000 { + skip-init; + status = "okay"; + }; }; diff --git a/arch/arm/dts/s5p4418-pinctrl.dtsi b/arch/arm/dts/s5p4418-pinctrl.dtsi index a7e1c2c381..0768d80fc9 100644 --- a/arch/arm/dts/s5p4418-pinctrl.dtsi +++ b/arch/arm/dts/s5p4418-pinctrl.dtsi @@ -132,4 +132,75 @@ pinctrl@C0010000 { pin-pull = <2>; pin-strength = <0>; }; + + /* UART */ + uart0_rx:uart0-rx { + pins = "gpiod-14"; + pin-function = <1>; + pin-pull = <2>; + pin-strength = <0>; + }; + + uart0_tx:uart0-tx { + pins = "gpiod-18"; + pin-function = <1>; + pin-pull = <2>; + pin-strength = <0>; + }; + + uart1_rx:uart1-rx { + pins = "gpiod-15"; + pin-function = <2>; + pin-pull = <2>; + pin-strength = <0>; + }; + + uart1_tx:uart1-tx { + pins = "gpiod-19"; + pin-function = <2>; + pin-pull = <2>; + pin-strength = <0>; + }; + + uart2_rx:uart2-rx { + pins = "gpiod-16"; + pin-function = <1>; + pin-pull = <2>; + pin-strength = <0>; + }; + + uart2_tx:uart2-tx { + pins = "gpiod-20"; + pin-function = <1>; + pin-pull = <2>; + pin-strength = <0>; + }; + + uart3_rx:uart3-rx { + pins = "gpiod-17"; + pin-function = <1>; + pin-pull = <2>; + pin-strength = <0>; + }; + + uart3_tx:uart3-tx { + pins = "gpiod-21"; + pin-function = <1>; + pin-pull = <2>; + pin-strength = <0>; + }; + + uart4_rx:uart4-rx { + pins = "gpiob-28"; + pin-function = <3>; + pin-pull = <2>; + pin-strength = <0>; + }; + + uart4_tx:uart4-tx { + pins = "gpiob-29"; + pin-function = <3>; + pin-pull = <2>; + pin-strength = <0>; + }; }; diff --git a/arch/arm/dts/s5p4418.dtsi b/arch/arm/dts/s5p4418.dtsi index a4d1a1bd03..3027cd4bb9 100644 --- a/arch/arm/dts/s5p4418.dtsi +++ b/arch/arm/dts/s5p4418.dtsi @@ -167,4 +167,44 @@ reg = <0xc0010000 0xf000>; u-boot,dm-pre-reloc; }; + + uart0:uart@c00a1000 { + compatible = "nexell,s5p4418-pl011", "arm,primecell"; + reg = <0xc00a1000 0x1000>; + pinctrl-names = "default"; + pinctrl-0 = <&uart0_rx>, <&uart0_tx>; + status = "disabled"; + }; + + uart1:uart@c00a0000 { + compatible = "nexell,s5p4418-pl011", "arm,primecell"; + reg = <0xc00a0000 0x1000>; + pinctrl-names = "default"; + pinctrl-0 = <&uart1_rx>, <&uart1_tx>; + status = "disabled"; + }; + + uart2:uart@c00a2000 { + compatible = "nexell,s5p4418-pl011", "arm,primecell"; + reg = <0xc00a2000 0x1000>; + pinctrl-names = "default"; + pinctrl-0 = <&uart2_rx>, <&uart2_tx>; + status = "disabled"; + }; + + uart3:uart@c00a3000 { + compatible = "nexell,s5p4418-pl011", "arm,primecell"; + reg = <0xc00a3000 0x1000>; + pinctrl-names = "default"; + pinctrl-0 = <&uart3_rx>, <&uart3_tx>; + status = "disabled"; + }; + + uart4:uart@c006d000 { + compatible = "nexell,s5p4418-pl011", "arm,primecell"; + reg = <0xc006d000 0x1000>; + pinctrl-names = "default"; + pinctrl-0 = <&uart4_rx>, <&uart4_tx>; + status = "disabled"; + }; }; diff --git a/arch/arm/dts/sam9x60.dtsi b/arch/arm/dts/sam9x60.dtsi index a5c429eb3a..2b93d08938 100644 --- a/arch/arm/dts/sam9x60.dtsi +++ b/arch/arm/dts/sam9x60.dtsi @@ -69,6 +69,50 @@ #size-cells = <1>; ranges; + usb1: usb@600000 { + compatible = "atmel,at91rm9200-ohci", "usb-ohci"; + reg = <0x00600000 0x100000>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 22>, <&pmc PMC_TYPE_PERIPHERAL 22>, <&pmc PMC_TYPE_SYSTEM 21>; + clock-names = "ohci_clk", "hclk", "uhpck"; + status = "disabled"; + }; + + usb2: usb@700000 { + compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; + reg = <0x00700000 0x100000>; + clocks = <&pmc PMC_TYPE_CORE 8>, <&pmc PMC_TYPE_PERIPHERAL 22>; + clock-names = "usb_clk", "ehci_clk"; + assigned-clocks = <&pmc PMC_TYPE_CORE 8>; + assigned-clock-rates = <480000000>; + status = "disabled"; + }; + + ebi: ebi@10000000 { + compatible = "microchip,sam9x60-ebi"; + #address-cells = <2>; + #size-cells = <1>; + atmel,smc = <&smc>; + microchip,sfr = <&sfr>; + reg = <0x10000000 0x60000000>; + ranges = <0x0 0x0 0x10000000 0x10000000 + 0x1 0x0 0x20000000 0x10000000 + 0x2 0x0 0x30000000 0x10000000 + 0x3 0x0 0x40000000 0x10000000 + 0x4 0x0 0x50000000 0x10000000 + 0x5 0x0 0x60000000 0x10000000>; + clocks = <&pmc PMC_TYPE_CORE 11>; + status = "disabled"; + + nand_controller: nand-controller { + compatible = "microchip,sam9x60-nand-controller"; + ecc-engine = <&pmecc>; + #address-cells = <2>; + #size-cells = <1>; + ranges; + status = "disabled"; + }; + }; + sdhci0: sdhci-host@80000000 { compatible = "microchip,sam9x60-sdhci"; reg = <0x80000000 0x300>; @@ -82,6 +126,19 @@ pinctrl-0 = <&pinctrl_sdhci0>; }; + sdhci1: sdhci-host@90000000 { + compatible = "microchip,sam9x60-sdhci"; + reg = <0x90000000 0x300>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 26>, <&pmc PMC_TYPE_GCK 26>; + clock-names = "hclock", "multclk"; + assigned-clocks = <&pmc PMC_TYPE_GCK 26>; + assigned-clock-rates = <100000000>; + assigned-clock-parents = <&pmc PMC_TYPE_CORE 10>; /* ID_PLL_A_DIV */ + bus-width = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sdhci1>; + }; + apb { compatible = "simple-bus"; #address-cells = <1>; @@ -119,6 +176,11 @@ status = "disabled"; }; + sfr: sfr@f8050000 { + compatible = "microchip,sam9x60-sfr", "syscon"; + reg = <0xf8050000 0x100>; + }; + dbgu: serial@fffff200 { compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; reg = <0xfffff200 0x200>; @@ -180,6 +242,29 @@ (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI | AT91_PINCTRL_SLEWRATE_ENA)>; /* PA20 DAT3 periph A with pullup */ }; }; + + sdhci1 { + pinctrl_sdhci1: sdhci1 { + atmel,pins = + <AT91_PIOA 13 AT91_PERIPH_B (AT91_PINCTRL_DRIVE_STRENGTH_HI) /* PA13 CK periph B */ + AT91_PIOA 12 AT91_PERIPH_B (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI) /* PA12 CMD periph B with pullup */ + AT91_PIOA 11 AT91_PERIPH_B (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI) /* PA11 DAT0 periph B with pullup */ + AT91_PIOA 2 AT91_PERIPH_B (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI) /* PA2 DAT1 periph B with pullup */ + AT91_PIOA 3 AT91_PERIPH_B (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI) /* PA3 DAT2 periph B with pullup */ + AT91_PIOA 4 AT91_PERIPH_B (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI)>; /* PA4 DAT3 periph B with pullup */ + }; + }; + }; + + pmecc: ecc-engine@ffffe000 { + compatible = "microchip,sam9x60-pmecc", "atmel,at91sam9g45-pmecc"; + reg = <0xffffe000 0x300>, + <0xffffe600 0x100>; + }; + + smc: smc@ffffea00 { + compatible = "microchip,sam9x60-smc", "atmel,at91sam9260-smc", "syscon"; + reg = <0xffffea00 0x100>; }; pioA: gpio@fffff400 { diff --git a/arch/arm/dts/sam9x60ek.dts b/arch/arm/dts/sam9x60ek.dts index eb44868a3e..45e2f4cc40 100644 --- a/arch/arm/dts/sam9x60ek.dts +++ b/arch/arm/dts/sam9x60ek.dts @@ -80,6 +80,44 @@ }; pinctrl { + nand { + pinctrl_nand_oe_we: nand-oe-we-0 { + atmel,pins = + <AT91_PIOD 0 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS) + AT91_PIOD 1 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)>; + }; + + pinctrl_nand_rb: nand-rb-0 { + atmel,pins = + <AT91_PIOD 5 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>; + }; + + pinctrl_nand_cs: nand-cs-0 { + atmel,pins = + <AT91_PIOD 4 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>; + }; + }; + + ebi { + pinctrl_ebi_data_0_7: ebi-data-lsb-0 { + atmel,pins = + <AT91_PIOD 6 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS) + AT91_PIOD 7 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS) + AT91_PIOD 8 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS) + AT91_PIOD 9 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS) + AT91_PIOD 10 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS) + AT91_PIOD 11 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS) + AT91_PIOD 12 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS) + AT91_PIOD 13 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)>; + }; + + pinctrl_ebi_addr_nand: ebi-addr-0 { + atmel,pins = + <AT91_PIOD 2 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS) + AT91_PIOD 3 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)>; + }; + }; + pinctrl_qspi: qspi { atmel,pins = <AT91_PIOB 19 AT91_PERIPH_A AT91_PINCTRL_NONE @@ -101,6 +139,78 @@ <AT91_PIOD 14 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>; }; + usb1 { + pinctrl_usb_default: usb_default { + atmel,pins = <AT91_PIOD 15 AT91_PERIPH_GPIO AT91_PINCTRL_NONE + AT91_PIOD 16 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>; + }; + }; + + }; + }; + }; +}; + +&ebi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ebi_addr_nand &pinctrl_ebi_data_0_7>; + status = "okay"; + + nand_controller: nand-controller { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_nand_oe_we &pinctrl_nand_cs &pinctrl_nand_rb>; + status = "okay"; + + nand@3 { + reg = <0x3 0x0 0x800000>; + rb-gpios = <&pioD 5 GPIO_ACTIVE_HIGH>; + cs-gpios = <&pioD 4 GPIO_ACTIVE_HIGH>; + nand-bus-width = <8>; + nand-ecc-mode = "hw"; + nand-ecc-strength = <8>; + nand-ecc-step-size = <512>; + nand-on-flash-bbt; + label = "atmel_nand"; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + at91bootstrap@0 { + label = "at91bootstrap"; + reg = <0x0 0x40000>; + }; + + uboot@40000 { + label = "u-boot"; + reg = <0x40000 0xc0000>; + }; + + ubootenvred@100000 { + label = "U-Boot Env Redundant"; + reg = <0x100000 0x40000>; + }; + + ubootenv@140000 { + label = "U-Boot Env"; + reg = <0x140000 0x40000>; + }; + + dtb@180000 { + label = "device tree"; + reg = <0x180000 0x80000>; + }; + + kernel@200000 { + label = "kernel"; + reg = <0x200000 0x600000>; + }; + + rootfs@800000 { + label = "rootfs"; + reg = <0x800000 0x1f800000>; + }; }; }; }; @@ -110,3 +220,17 @@ phy-mode = "rmii"; status = "okay"; }; + +&usb1 { + num-ports = <3>; + atmel,vbus-gpio = <0 + &pioD 15 GPIO_ACTIVE_HIGH + &pioD 16 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_default>; + status = "okay"; +}; + +&usb2 { + status = "okay"; +}; diff --git a/arch/arm/dts/sama5d2.dtsi b/arch/arm/dts/sama5d2.dtsi index 790b746ed1..187c2ff2fb 100644 --- a/arch/arm/dts/sama5d2.dtsi +++ b/arch/arm/dts/sama5d2.dtsi @@ -84,7 +84,6 @@ reg = <0xf0014000 0x160>; #address-cells = <1>; #size-cells = <0>; - #interrupt-cells = <1>; u-boot,dm-pre-reloc; main: mainck { diff --git a/arch/arm/dts/sama7g5.dtsi b/arch/arm/dts/sama7g5.dtsi index d38090d7dd..6388a60e53 100644 --- a/arch/arm/dts/sama7g5.dtsi +++ b/arch/arm/dts/sama7g5.dtsi @@ -15,6 +15,7 @@ #include <dt-bindings/clk/at91.h> #include <dt-bindings/dma/at91.h> #include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/mfd/at91-usart.h> / { model = "Microchip SAMA7G5 family SoC"; @@ -195,11 +196,11 @@ <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 11>; interrupt-controller; #interrupt-cells = <2>; gpio-controller; #gpio-cells = <2>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 11>; }; pmc: pmc@e0018000 { @@ -211,6 +212,13 @@ clock-names = "td_slck", "md_slck", "main_xtal", "main_rc"; }; + reset_controller: reset-controller@e001d000 { + compatible = "microchip,sama7g5-rstc"; + reg = <0xe001d000 0xc>, <0xe001d0e4 0x4>; + #reset-cells = <1>; + clocks = <&clk32k 0>; + }; + shdwc: shdwc@e001d010 { compatible = "microchip,sama7g5-shdwc", "syscon"; reg = <0xe001d010 0x10>; @@ -229,13 +237,6 @@ clocks = <&clk32k 0>; }; - reset_controller: rstc@e001d000 { - compatible = "microchip,sama7g5-rstc", "microchip,sam9x60-rstc"; - reg = <0xe001d000 0xc>, <0xe001d0e4 0x4>; - #reset-cells = <1>; - clocks = <&clk32k 0>; - }; - clk32k: clock-controller@e001d050 { compatible = "microchip,sama7g5-sckc", "microchip,sam9x60-sckc"; reg = <0xe001d050 0x4>; @@ -620,6 +621,7 @@ uart0: serial@200 { compatible = "atmel,at91sam9260-usart"; reg = <0x200 0x200>; + atmel,usart-mode = <AT91_USART_MODE_SERIAL>; interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; clocks = <&pmc PMC_TYPE_PERIPHERAL 38>; clock-names = "usart"; @@ -668,6 +670,7 @@ uart3: serial@200 { compatible = "atmel,at91sam9260-usart"; reg = <0x200 0x200>; + atmel,usart-mode = <AT91_USART_MODE_SERIAL>; interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; clocks = <&pmc PMC_TYPE_PERIPHERAL 41>; clock-names = "usart"; @@ -711,6 +714,7 @@ uart4: serial@200 { compatible = "atmel,at91sam9260-usart"; reg = <0x200 0x200>; + atmel,usart-mode = <AT91_USART_MODE_SERIAL>; interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; clocks = <&pmc PMC_TYPE_PERIPHERAL 42>; clock-names = "usart"; @@ -736,6 +740,7 @@ uart7: serial@200 { compatible = "atmel,at91sam9260-usart"; reg = <0x200 0x200>; + atmel,usart-mode = <AT91_USART_MODE_SERIAL>; interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; clocks = <&pmc PMC_TYPE_PERIPHERAL 45>; clock-names = "usart"; @@ -884,9 +889,9 @@ #address-cells = <1>; #size-cells = <0>; atmel,fifo-size = <32>; - dmas = <&dma0 AT91_XDMAC_DT_PERID(27)>, - <&dma0 AT91_XDMAC_DT_PERID(28)>; - dma-names = "rx", "tx"; + dmas = <&dma0 AT91_XDMAC_DT_PERID(28)>, + <&dma0 AT91_XDMAC_DT_PERID(27)>; + dma-names = "tx", "rx"; status = "disabled"; }; }; diff --git a/arch/arm/dts/synquacer-sc2a11-developerbox-u-boot.dtsi b/arch/arm/dts/synquacer-sc2a11-developerbox-u-boot.dtsi index 7a56116d6f..9f9837b33b 100644 --- a/arch/arm/dts/synquacer-sc2a11-developerbox-u-boot.dtsi +++ b/arch/arm/dts/synquacer-sc2a11-developerbox-u-boot.dtsi @@ -20,10 +20,8 @@ #address-cells = <1>; #size-cells = <0>; status = "okay"; - active_clk_edges; - chipselect_num = <1>; - spi-flash@0 { + flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "jedec,spi-nor"; diff --git a/arch/arm/dts/synquacer-sc2a11-developerbox.dts b/arch/arm/dts/synquacer-sc2a11-developerbox.dts index 42b6cbbb82..c8087b99a7 100644 --- a/arch/arm/dts/synquacer-sc2a11-developerbox.dts +++ b/arch/arm/dts/synquacer-sc2a11-developerbox.dts @@ -18,7 +18,7 @@ compatible = "gpio-keys"; interrupt-parent = <&exiu>; - power { + power-button { label = "Power Button"; linux,code = <KEY_POWER>; interrupts = <GIC_SPI 120 IRQ_TYPE_EDGE_FALLING>; diff --git a/arch/arm/dts/synquacer-sc2a11.dtsi b/arch/arm/dts/synquacer-sc2a11.dtsi index 1fe7d214b9..7ba1cd1bee 100644 --- a/arch/arm/dts/synquacer-sc2a11.dtsi +++ b/arch/arm/dts/synquacer-sc2a11.dtsi @@ -41,168 +41,168 @@ CPU0: cpu@0 { device_type = "cpu"; - compatible = "arm,cortex-a53","arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0x0>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; }; CPU1: cpu@1 { device_type = "cpu"; - compatible = "arm,cortex-a53","arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0x1>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; }; CPU2: cpu@100 { device_type = "cpu"; - compatible = "arm,cortex-a53","arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0x100>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; }; CPU3: cpu@101 { device_type = "cpu"; - compatible = "arm,cortex-a53","arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0x101>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; }; CPU4: cpu@200 { device_type = "cpu"; - compatible = "arm,cortex-a53","arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0x200>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; }; CPU5: cpu@201 { device_type = "cpu"; - compatible = "arm,cortex-a53","arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0x201>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; }; CPU6: cpu@300 { device_type = "cpu"; - compatible = "arm,cortex-a53","arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0x300>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; }; CPU7: cpu@301 { device_type = "cpu"; - compatible = "arm,cortex-a53","arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0x301>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; }; CPU8: cpu@400 { device_type = "cpu"; - compatible = "arm,cortex-a53","arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0x400>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; }; CPU9: cpu@401 { device_type = "cpu"; - compatible = "arm,cortex-a53","arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0x401>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; }; CPU10: cpu@500 { device_type = "cpu"; - compatible = "arm,cortex-a53","arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0x500>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; }; CPU11: cpu@501 { device_type = "cpu"; - compatible = "arm,cortex-a53","arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0x501>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; }; CPU12: cpu@600 { device_type = "cpu"; - compatible = "arm,cortex-a53","arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0x600>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; }; CPU13: cpu@601 { device_type = "cpu"; - compatible = "arm,cortex-a53","arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0x601>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; }; CPU14: cpu@700 { device_type = "cpu"; - compatible = "arm,cortex-a53","arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0x700>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; }; CPU15: cpu@701 { device_type = "cpu"; - compatible = "arm,cortex-a53","arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0x701>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; }; CPU16: cpu@800 { device_type = "cpu"; - compatible = "arm,cortex-a53","arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0x800>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; }; CPU17: cpu@801 { device_type = "cpu"; - compatible = "arm,cortex-a53","arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0x801>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; }; CPU18: cpu@900 { device_type = "cpu"; - compatible = "arm,cortex-a53","arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0x900>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; }; CPU19: cpu@901 { device_type = "cpu"; - compatible = "arm,cortex-a53","arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0x901>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; }; CPU20: cpu@a00 { device_type = "cpu"; - compatible = "arm,cortex-a53","arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0xa00>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; }; CPU21: cpu@a01 { device_type = "cpu"; - compatible = "arm,cortex-a53","arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0xa01>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; }; CPU22: cpu@b00 { device_type = "cpu"; - compatible = "arm,cortex-a53","arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0xb00>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; }; CPU23: cpu@b01 { device_type = "cpu"; - compatible = "arm,cortex-a53","arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0xb01>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; @@ -309,7 +309,7 @@ }; idle-states { - entry-method = "arm,psci"; + entry-method = "psci"; CPU_SLEEP_0: cpu-sleep-0 { compatible = "arm,idle-state"; @@ -344,7 +344,7 @@ interrupt-controller; interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; - its: gic-its@30020000 { + its: msi-controller@30020000 { compatible = "arm,gic-v3-its"; reg = <0x0 0x30020000 0x0 0x20000>; #msi-cells = <1>; @@ -361,16 +361,16 @@ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; // HYP }; - mmio-timer@2a810000 { + timer@2a810000 { compatible = "arm,armv7-timer-mem"; reg = <0x0 0x2a810000 0x0 0x10000>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - frame@2a830000 { + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x2a810000 0x30000>; + frame@20000 { frame-number = <0>; interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; - reg = <0x0 0x2a830000 0x0 0x10000>; + reg = <0x20000 0x10000>; }; }; @@ -398,7 +398,7 @@ clock-output-names = "apb_pclk"; }; - soc_uart0: uart@2a400000 { + soc_uart0: serial@2a400000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x0 0x2a400000 0x0 0x1000>; interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; @@ -406,7 +406,7 @@ clock-names = "uartclk", "apb_pclk"; }; - fuart: uart@51040000 { + fuart: serial@51040000 { compatible = "snps,dw-apb-uart"; reg = <0x0 0x51040000 0x0 0x1000>; interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; @@ -497,7 +497,6 @@ gpio-controller; #gpio-cells = <2>; clocks = <&clk_apb>; - base = <0>; }; exiu: interrupt-controller@510c0000 { @@ -523,7 +522,7 @@ clock-output-names = "sd_sd4clk"; }; - sdhci: sdhci@52300000 { + sdhci: mmc@52300000 { compatible = "socionext,synquacer-sdhci", "fujitsu,mb86s70-sdhci-3.0"; reg = <0 0x52300000 0x0 0x1000>; interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, diff --git a/arch/arm/dts/uniphier-v7-u-boot.dtsi b/arch/arm/dts/uniphier-v7-u-boot.dtsi index 9459bf0377..603b33dd2b 100644 --- a/arch/arm/dts/uniphier-v7-u-boot.dtsi +++ b/arch/arm/dts/uniphier-v7-u-boot.dtsi @@ -2,6 +2,10 @@ soc { u-boot,dm-pre-reloc; + timer@60000200 { + u-boot,dm-pre-reloc; + }; + serial@54006800 { u-boot,dm-pre-reloc; }; diff --git a/arch/arm/include/asm/arch-am33xx/clock.h b/arch/arm/include/asm/arch-am33xx/clock.h index 79e3b8c7d9..ad25b3e8aa 100644 --- a/arch/arm/include/asm/arch-am33xx/clock.h +++ b/arch/arm/include/asm/arch-am33xx/clock.h @@ -13,7 +13,7 @@ #include <asm/arch/clocks_am33xx.h> #include <asm/arch/hardware.h> -#if defined(CONFIG_TI816X) || defined(CONFIG_TI814X) +#if defined(CONFIG_TI816X) #include <asm/arch/clock_ti81xx.h> #endif diff --git a/arch/arm/include/asm/arch-am33xx/clock_ti81xx.h b/arch/arm/include/asm/arch-am33xx/clock_ti81xx.h index f0699229a3..d22d958706 100644 --- a/arch/arm/include/asm/arch-am33xx/clock_ti81xx.h +++ b/arch/arm/include/asm/arch-am33xx/clock_ti81xx.h @@ -44,9 +44,7 @@ struct cm_alwon { unsigned int mmu_clkstctrl; unsigned int mmucfg_clkstctrl; unsigned int ocmc0clkstctrl; -#if defined(CONFIG_TI814X) - unsigned int vcpclkstctrl; -#elif defined(CONFIG_TI816X) +#if defined(CONFIG_TI816X) unsigned int ocmc1clkstctrl; #endif unsigned int mpuclkstctrl; @@ -67,16 +65,7 @@ struct cm_alwon { unsigned int gpio1clkctrl; unsigned int i2c0clkctrl; unsigned int i2c1clkctrl; -#if defined(CONFIG_TI814X) - unsigned int mcasp345clkctrl; - unsigned int atlclkctrl; - unsigned int mlbclkctrl; - unsigned int pataclkctrl; - unsigned int resv1[1]; - unsigned int uart3clkctrl; - unsigned int uart4clkctrl; - unsigned int uart5clkctrl; -#elif defined(CONFIG_TI816X) +#if defined(CONFIG_TI816X) unsigned int resv1[1]; unsigned int timer1clkctrl; unsigned int timer2clkctrl; @@ -93,16 +82,12 @@ struct cm_alwon { unsigned int mmudataclkctrl; unsigned int resv2[2]; unsigned int mmucfgclkctrl; -#if defined(CONFIG_TI814X) - unsigned int resv3[2]; -#elif defined(CONFIG_TI816X) +#if defined(CONFIG_TI816X) unsigned int resv3[1]; unsigned int sdioclkctrl; #endif unsigned int ocmc0clkctrl; -#if defined(CONFIG_TI814X) - unsigned int vcpclkctrl; -#elif defined(CONFIG_TI816X) +#if defined(CONFIG_TI816X) unsigned int ocmc1clkctrl; #endif unsigned int resv4[2]; @@ -112,9 +97,7 @@ struct cm_alwon { unsigned int ethernet0clkctrl; unsigned int ethernet1clkctrl; unsigned int mpuclkctrl; -#if defined(CONFIG_TI814X) - unsigned int debugssclkctrl; -#elif defined(CONFIG_TI816X) +#if defined(CONFIG_TI816X) unsigned int resv6[1]; #endif unsigned int l3clkctrl; @@ -126,14 +109,7 @@ struct cm_alwon { unsigned int tptc1clkctrl; unsigned int tptc2clkctrl; unsigned int tptc3clkctrl; -#if defined(CONFIG_TI814X) - unsigned int resv6[4]; - unsigned int dcan01clkctrl; - unsigned int mmchs0clkctrl; - unsigned int mmchs1clkctrl; - unsigned int mmchs2clkctrl; - unsigned int custefuseclkctrl; -#elif defined(CONFIG_TI816X) +#if defined(CONFIG_TI816X) unsigned int sr0clkctrl; unsigned int sr1clkctrl; #endif diff --git a/arch/arm/include/asm/arch-am33xx/hardware.h b/arch/arm/include/asm/arch-am33xx/hardware.h index 0508b8c912..2d7f9da365 100644 --- a/arch/arm/include/asm/arch-am33xx/hardware.h +++ b/arch/arm/include/asm/arch-am33xx/hardware.h @@ -16,8 +16,6 @@ #include <asm/arch/hardware_am33xx.h> #elif defined(CONFIG_TI816X) #include <asm/arch/hardware_ti816x.h> -#elif defined(CONFIG_TI814X) -#include <asm/arch/hardware_ti814x.h> #elif defined(CONFIG_AM43XX) #include <asm/arch/hardware_am43xx.h> #endif diff --git a/arch/arm/include/asm/arch-am33xx/hardware_ti814x.h b/arch/arm/include/asm/arch-am33xx/hardware_ti814x.h deleted file mode 100644 index b00d592bc3..0000000000 --- a/arch/arm/include/asm/arch-am33xx/hardware_ti814x.h +++ /dev/null @@ -1,60 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * hardware_ti814x.h - * - * TI814x hardware specific header - * - * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/ - */ - -#ifndef __AM33XX_HARDWARE_TI814X_H -#define __AM33XX_HARDWARE_TI814X_H - -/* Module base addresses */ - -/* UART Base Address */ -#define UART0_BASE 0x48020000 - -/* Watchdog Timer */ -#define WDT_BASE 0x481C7000 - -/* Control Module Base Address */ -#define CTRL_BASE 0x48140000 -#define CTRL_DEVICE_BASE 0x48140600 - -/* PRCM Base Address */ -#define PRCM_BASE 0x48180000 -#define CM_PER 0x44E00000 -#define CM_WKUP 0x44E00400 - -#define PRM_RSTCTRL (PRCM_BASE + 0x00A0) -#define PRM_RSTST (PRM_RSTCTRL + 8) - -/* PLL Subsystem Base Address */ -#define PLL_SUBSYS_BASE 0x481C5000 - -/* VTP Base address */ -#define VTP0_CTRL_ADDR 0x48140E0C -#define VTP1_CTRL_ADDR 0x48140E10 - -/* DDR Base address */ -#define DDR_PHY_CMD_ADDR 0x47C0C400 -#define DDR_PHY_DATA_ADDR 0x47C0C4C8 -#define DDR_PHY_CMD_ADDR2 0x47C0C800 -#define DDR_PHY_DATA_ADDR2 0x47C0C8C8 -#define DDR_DATA_REGS_NR 4 - -#define DDRPHY_0_CONFIG_BASE (CTRL_BASE + 0x1400) -#define DDRPHY_CONFIG_BASE DDRPHY_0_CONFIG_BASE - -/* CPSW Config space */ -#define CPSW_MDIO_BASE 0x4A100800 - -/* RTC base address */ -#define RTC_BASE 0x480C0000 - -/* OTG */ -#define USB0_OTG_BASE 0x47401000 -#define USB1_OTG_BASE 0x47401800 - -#endif /* __AM33XX_HARDWARE_TI814X_H */ diff --git a/arch/arm/include/asm/arch-am33xx/mmc_host_def.h b/arch/arm/include/asm/arch-am33xx/mmc_host_def.h index 5a2ea8faef..ed15d15c5b 100644 --- a/arch/arm/include/asm/arch-am33xx/mmc_host_def.h +++ b/arch/arm/include/asm/arch-am33xx/mmc_host_def.h @@ -24,10 +24,7 @@ #define OMAP_HSMMC1_BASE 0x48060000 #define OMAP_HSMMC2_BASE 0x481D8000 -#if defined(CONFIG_TI814X) -#undef MMC_CLOCK_REFERENCE -#define MMC_CLOCK_REFERENCE 192 /* MHz */ -#elif defined(CONFIG_TI816X) +#if defined(CONFIG_TI816X) #undef MMC_CLOCK_REFERENCE #define MMC_CLOCK_REFERENCE 48 /* MHz */ #endif diff --git a/arch/arm/include/asm/arch-am33xx/mux.h b/arch/arm/include/asm/arch-am33xx/mux.h index b16b184733..7cf973710d 100644 --- a/arch/arm/include/asm/arch-am33xx/mux.h +++ b/arch/arm/include/asm/arch-am33xx/mux.h @@ -20,8 +20,6 @@ #ifdef CONFIG_AM33XX #include <asm/arch/mux_am33xx.h> -#elif defined(CONFIG_TI814X) -#include <asm/arch/mux_ti814x.h> #elif defined(CONFIG_TI816X) #include <asm/arch/mux_ti816x.h> #elif defined(CONFIG_AM43XX) diff --git a/arch/arm/include/asm/arch-am33xx/mux_ti814x.h b/arch/arm/include/asm/arch-am33xx/mux_ti814x.h deleted file mode 100644 index a26e5038f7..0000000000 --- a/arch/arm/include/asm/arch-am33xx/mux_ti814x.h +++ /dev/null @@ -1,311 +0,0 @@ -/* - * mux_ti814x.h - * - * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation version 2. - * - * This program is distributed "as is" WITHOUT ANY WARRANTY of any - * kind, whether express or implied; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _MUX_TI814X_H_ -#define _MUX_TI814X_H_ - -/* PAD Control Fields */ -#define PINCNTL_RSV_MSK (0x3 << 18) /* Reserved bitmask */ -#define PULLUP_EN (0x1 << 17) /* Pull UP Selection */ -#define PULLUDEN (0x0 << 16) /* Pull up enabled */ -#define PULLUDDIS (0x1 << 16) /* Pull up disabled */ -#define MODE(val) val /* used for Readability */ - -#define MUX_CFG(value, offset) \ -{ \ - int tmp; \ - tmp = __raw_readl(CTRL_BASE + offset); \ - tmp &= PINCNTL_RSV_MSK; \ - __raw_writel(tmp | value, (CTRL_BASE + offset));\ -} - -/* - * PAD CONTROL OFFSETS - * Field names corresponds to the pad signal name - */ -struct pad_signals { - int pincntl1; - int pincntl2; - int pincntl3; - int pincntl4; - int pincntl5; - int pincntl6; - int pincntl7; - int pincntl8; - int pincntl9; - int pincntl10; - int pincntl11; - int pincntl12; - int pincntl13; - int pincntl14; - int pincntl15; - int pincntl16; - int pincntl17; - int pincntl18; - int pincntl19; - int pincntl20; - int pincntl21; - int pincntl22; - int pincntl23; - int pincntl24; - int pincntl25; - int pincntl26; - int pincntl27; - int pincntl28; - int pincntl29; - int pincntl30; - int pincntl31; - int pincntl32; - int pincntl33; - int pincntl34; - int pincntl35; - int pincntl36; - int pincntl37; - int pincntl38; - int pincntl39; - int pincntl40; - int pincntl41; - int pincntl42; - int pincntl43; - int pincntl44; - int pincntl45; - int pincntl46; - int pincntl47; - int pincntl48; - int pincntl49; - int pincntl50; - int pincntl51; - int pincntl52; - int pincntl53; - int pincntl54; - int pincntl55; - int pincntl56; - int pincntl57; - int pincntl58; - int pincntl59; - int pincntl60; - int pincntl61; - int pincntl62; - int pincntl63; - int pincntl64; - int pincntl65; - int pincntl66; - int pincntl67; - int pincntl68; - int pincntl69; - int pincntl70; - int pincntl71; - int pincntl72; - int pincntl73; - int pincntl74; - int pincntl75; - int pincntl76; - int pincntl77; - int pincntl78; - int pincntl79; - int pincntl80; - int pincntl81; - int pincntl82; - int pincntl83; - int pincntl84; - int pincntl85; - int pincntl86; - int pincntl87; - int pincntl88; - int pincntl89; - int pincntl90; - int pincntl91; - int pincntl92; - int pincntl93; - int pincntl94; - int pincntl95; - int pincntl96; - int pincntl97; - int pincntl98; - int pincntl99; - int pincntl100; - int pincntl101; - int pincntl102; - int pincntl103; - int pincntl104; - int pincntl105; - int pincntl106; - int pincntl107; - int pincntl108; - int pincntl109; - int pincntl110; - int pincntl111; - int pincntl112; - int pincntl113; - int pincntl114; - int pincntl115; - int pincntl116; - int pincntl117; - int pincntl118; - int pincntl119; - int pincntl120; - int pincntl121; - int pincntl122; - int pincntl123; - int pincntl124; - int pincntl125; - int pincntl126; - int pincntl127; - int pincntl128; - int pincntl129; - int pincntl130; - int pincntl131; - int pincntl132; - int pincntl133; - int pincntl134; - int pincntl135; - int pincntl136; - int pincntl137; - int pincntl138; - int pincntl139; - int pincntl140; - int pincntl141; - int pincntl142; - int pincntl143; - int pincntl144; - int pincntl145; - int pincntl146; - int pincntl147; - int pincntl148; - int pincntl149; - int pincntl150; - int pincntl151; - int pincntl152; - int pincntl153; - int pincntl154; - int pincntl155; - int pincntl156; - int pincntl157; - int pincntl158; - int pincntl159; - int pincntl160; - int pincntl161; - int pincntl162; - int pincntl163; - int pincntl164; - int pincntl165; - int pincntl166; - int pincntl167; - int pincntl168; - int pincntl169; - int pincntl170; - int pincntl171; - int pincntl172; - int pincntl173; - int pincntl174; - int pincntl175; - int pincntl176; - int pincntl177; - int pincntl178; - int pincntl179; - int pincntl180; - int pincntl181; - int pincntl182; - int pincntl183; - int pincntl184; - int pincntl185; - int pincntl186; - int pincntl187; - int pincntl188; - int pincntl189; - int pincntl190; - int pincntl191; - int pincntl192; - int pincntl193; - int pincntl194; - int pincntl195; - int pincntl196; - int pincntl197; - int pincntl198; - int pincntl199; - int pincntl200; - int pincntl201; - int pincntl202; - int pincntl203; - int pincntl204; - int pincntl205; - int pincntl206; - int pincntl207; - int pincntl208; - int pincntl209; - int pincntl210; - int pincntl211; - int pincntl212; - int pincntl213; - int pincntl214; - int pincntl215; - int pincntl216; - int pincntl217; - int pincntl218; - int pincntl219; - int pincntl220; - int pincntl221; - int pincntl222; - int pincntl223; - int pincntl224; - int pincntl225; - int pincntl226; - int pincntl227; - int pincntl228; - int pincntl229; - int pincntl230; - int pincntl231; - int pincntl232; - int pincntl233; - int pincntl234; - int pincntl235; - int pincntl236; - int pincntl237; - int pincntl238; - int pincntl239; - int pincntl240; - int pincntl241; - int pincntl242; - int pincntl243; - int pincntl244; - int pincntl245; - int pincntl246; - int pincntl247; - int pincntl248; - int pincntl249; - int pincntl250; - int pincntl251; - int pincntl252; - int pincntl253; - int pincntl254; - int pincntl255; - int pincntl256; - int pincntl257; - int pincntl258; - int pincntl259; - int pincntl260; - int pincntl261; - int pincntl262; - int pincntl263; - int pincntl264; - int pincntl265; - int pincntl266; - int pincntl267; - int pincntl268; - int pincntl269; - int pincntl270; -}; - -#endif /* endif _MUX_TI814X_H_ */ diff --git a/arch/arm/include/asm/arch-am33xx/omap.h b/arch/arm/include/asm/arch-am33xx/omap.h index bc9f0a1146..4c71dbf3ab 100644 --- a/arch/arm/include/asm/arch-am33xx/omap.h +++ b/arch/arm/include/asm/arch-am33xx/omap.h @@ -20,7 +20,7 @@ #define NON_SECURE_SRAM_START 0x402F0400 #define NON_SECURE_SRAM_END 0x40310000 #define NON_SECURE_SRAM_IMG_END 0x4030B800 -#elif defined(CONFIG_TI816X) || defined(CONFIG_TI814X) +#elif defined(CONFIG_TI816X) #define NON_SECURE_SRAM_START 0x40300000 #define NON_SECURE_SRAM_END 0x40320000 #define NON_SECURE_SRAM_IMG_END 0x4031B800 diff --git a/arch/arm/include/asm/arch-am33xx/spl.h b/arch/arm/include/asm/arch-am33xx/spl.h index f3910c2123..6bd3ca0d07 100644 --- a/arch/arm/include/asm/arch-am33xx/spl.h +++ b/arch/arm/include/asm/arch-am33xx/spl.h @@ -9,21 +9,7 @@ #define BOOT_DEVICE_NONE 0x00 #define BOOT_DEVICE_MMC2_2 0xFF -#if defined(CONFIG_TI814X) -#define BOOT_DEVICE_XIP 0x01 -#define BOOT_DEVICE_XIPWAIT 0x02 -#define BOOT_DEVICE_NAND 0x05 -#define BOOT_DEVICE_NAND_I2C 0x06 -#define BOOT_DEVICE_MMC2 0x08 /* ROM only supports 2nd instance. */ -#define BOOT_DEVICE_MMC1 0x09 -#define BOOT_DEVICE_SPI 0x15 -#define BOOT_DEVICE_UART 0x41 -#define BOOT_DEVICE_USBETH 0x44 -#define BOOT_DEVICE_CPGMAC 0x46 - -#define MMC_BOOT_DEVICES_START BOOT_DEVICE_MMC2 -#define MMC_BOOT_DEVICES_END BOOT_DEVICE_MMC1 -#elif defined(CONFIG_TI816X) +#if defined(CONFIG_TI816X) #define BOOT_DEVICE_XIP 0x01 #define BOOT_DEVICE_XIPWAIT 0x02 #define BOOT_DEVICE_NAND 0x03 diff --git a/arch/arm/include/asm/arch-bcmcygnus/configs.h b/arch/arm/include/asm/arch-bcmcygnus/configs.h index 327c0e0697..fd8dad394a 100644 --- a/arch/arm/include/asm/arch-bcmcygnus/configs.h +++ b/arch/arm/include/asm/arch-bcmcygnus/configs.h @@ -11,12 +11,8 @@ /* uArchitecture specifics */ /* Serial Info */ -/* Post pad 3 bytes after each reg addr */ -#define CONFIG_SYS_NS16550_REG_SIZE (-4) -#define CONFIG_SYS_NS16550_MEM32 - -#define CONFIG_SYS_NS16550_CLK 100000000 -#define CONFIG_SYS_NS16550_CLK_DIV 54 -#define CONFIG_SYS_NS16550_COM3 0x18023000 +#define CFG_SYS_NS16550_CLK 100000000 +#define CFG_SYS_NS16550_CLK_DIV 54 +#define CFG_SYS_NS16550_COM3 0x18023000 #endif /* __ARCH_CONFIGS_H */ diff --git a/arch/arm/include/asm/arch-bcmnsp/configs.h b/arch/arm/include/asm/arch-bcmnsp/configs.h index 05fa9b9612..0d4baf3c00 100644 --- a/arch/arm/include/asm/arch-bcmnsp/configs.h +++ b/arch/arm/include/asm/arch-bcmnsp/configs.h @@ -11,10 +11,7 @@ /* uArchitecture specifics */ /* Serial Info */ -/* no padding */ -#define CONFIG_SYS_NS16550_REG_SIZE 1 - -#define CONFIG_SYS_NS16550_CLK 0x03b9aca0 -#define CONFIG_SYS_NS16550_COM1 0x18000300 +#define CFG_SYS_NS16550_CLK 0x03b9aca0 +#define CFG_SYS_NS16550_COM1 0x18000300 #endif /* __ARCH_CONFIGS_H */ diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h index ff752c21b1..516c9eab04 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h @@ -14,19 +14,17 @@ #include <linux/bitops.h> #endif -#define CONFIG_STANDALONE_LOAD_ADDR 0x80300000 - /* * Reserve secure memory * To be aligned with MMU block size */ -#define CONFIG_SYS_MEM_RESERVE_SECURE (66 * 1024 * 1024) /* 66MB */ +#define CFG_SYS_MEM_RESERVE_SECURE (66 * 1024 * 1024) /* 66MB */ #define SPL_TLB_SETBACK 0x1000000 /* 16MB under effective memory top */ #ifdef CONFIG_ARCH_LS2080A #define CFG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4, 4 } #define SRDS_MAX_LANES 8 -#define CONFIG_SYS_PAGE_SIZE 0x10000 +#define CFG_SYS_PAGE_SIZE 0x10000 #ifndef L1_CACHE_BYTES #define L1_CACHE_SHIFT 6 #define L1_CACHE_BYTES BIT(L1_CACHE_SHIFT) @@ -37,8 +35,8 @@ #define CFG_SYS_FSL_OCRAM_SIZE 0x00020000 /* Real size 128K */ /* DDR */ -#define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) -#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE +#define CFG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) +#define CFG_MAX_MEM_MAPPED CFG_SYS_DDR_BLOCK1_SIZE /* Generic Interrupt Controller Definitions */ #define GICD_BASE 0x06000000 @@ -96,7 +94,7 @@ #elif defined(CONFIG_ARCH_LS1088A) #define CFG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 } -#define CONFIG_SYS_PAGE_SIZE 0x10000 +#define CFG_SYS_PAGE_SIZE 0x10000 #define SRDS_MAX_LANES 4 #define SRDS_BITS_PER_LANE 4 @@ -122,8 +120,8 @@ #define SMMU_BASE 0x05000000 /* GR0 Base */ /* DDR */ -#define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) -#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE +#define CFG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) +#define CFG_MAX_MEM_MAPPED CFG_SYS_DDR_BLOCK1_SIZE /* DCFG - GUR */ #define CFG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */ @@ -141,15 +139,15 @@ #endif #define CFG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1, 4, 4, 4, 4 } -#define CONFIG_SYS_PAGE_SIZE 0x10000 +#define CFG_SYS_PAGE_SIZE 0x10000 #define CFG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */ #define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M space */ #define CFG_SYS_FSL_OCRAM_SIZE 0x00040000 /* Real size 256K */ /* DDR */ -#define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) -#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE +#define CFG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) +#define CFG_MAX_MEM_MAPPED CFG_SYS_DDR_BLOCK1_SIZE /* Generic Interrupt Controller Definitions */ #define GICD_BASE 0x06000000 @@ -162,7 +160,6 @@ #elif defined(CONFIG_ARCH_LS1028A) #define CFG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 } -#define CONFIG_FSL_TZASC_400 /* TZ Protection Controller Definitions */ #define TZPC_BASE 0x02200000 @@ -192,8 +189,8 @@ #define SMMU_BASE 0x05000000 /* GR0 Base */ /* DDR */ -#define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) -#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE +#define CFG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) +#define CFG_MAX_MEM_MAPPED CFG_SYS_DDR_BLOCK1_SIZE /* SEC */ @@ -209,11 +206,11 @@ /* SoC related */ #ifdef CONFIG_ARCH_LS1043A -#define CONFIG_SYS_NUM_FMAN 1 -#define CONFIG_SYS_NUM_FM1_DTSEC 7 -#define CONFIG_SYS_NUM_FM1_10GEC 1 -#define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) -#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE +#define CFG_SYS_NUM_FMAN 1 +#define CFG_SYS_NUM_FM1_DTSEC 7 +#define CFG_SYS_NUM_FM1_10GEC 1 +#define CFG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) +#define CFG_MAX_MEM_MAPPED CFG_SYS_DDR_BLOCK1_SIZE #define QE_MURAM_SIZE 0x6000UL #define MAX_QE_RISC 1 @@ -251,15 +248,15 @@ #elif defined(CONFIG_ARCH_LS1012A) #define GICD_BASE 0x01401000 #define GICC_BASE 0x01402000 -#define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) -#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE +#define CFG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) +#define CFG_MAX_MEM_MAPPED CFG_SYS_DDR_BLOCK1_SIZE #elif defined(CONFIG_ARCH_LS1046A) -#define CONFIG_SYS_NUM_FMAN 1 -#define CONFIG_SYS_NUM_FM1_DTSEC 8 -#define CONFIG_SYS_NUM_FM1_10GEC 2 -#define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) -#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE +#define CFG_SYS_NUM_FMAN 1 +#define CFG_SYS_NUM_FM1_DTSEC 8 +#define CFG_SYS_NUM_FM1_10GEC 2 +#define CFG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) +#define CFG_MAX_MEM_MAPPED CFG_SYS_DDR_BLOCK1_SIZE /* SMMU Defintions */ #define SMMU_BASE 0x09000000 diff --git a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h index 4db479140e..20f9671387 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h @@ -35,17 +35,17 @@ #define CONFIG_SYS_FSL_QBMAN_SIZE 0x8000000 #define CONFIG_SYS_FSL_QBMAN_SIZE_1 0x4000000 #ifdef CONFIG_ARCH_LS2080A -#define CONFIG_SYS_PCIE1_PHYS_SIZE 0x200000000 -#define CONFIG_SYS_PCIE2_PHYS_SIZE 0x200000000 -#define CONFIG_SYS_PCIE3_PHYS_SIZE 0x200000000 -#define CONFIG_SYS_PCIE4_PHYS_SIZE 0x200000000 +#define CFG_SYS_PCIE1_PHYS_SIZE 0x200000000 +#define CFG_SYS_PCIE2_PHYS_SIZE 0x200000000 +#define CFG_SYS_PCIE3_PHYS_SIZE 0x200000000 +#define CFG_SYS_PCIE4_PHYS_SIZE 0x200000000 #else -#define CONFIG_SYS_PCIE1_PHYS_SIZE 0x800000000 -#define CONFIG_SYS_PCIE2_PHYS_SIZE 0x800000000 -#ifndef CONFIG_SYS_PCIE3_PHYS_SIZE -#define CONFIG_SYS_PCIE3_PHYS_SIZE 0x800000000 +#define CFG_SYS_PCIE1_PHYS_SIZE 0x800000000 +#define CFG_SYS_PCIE2_PHYS_SIZE 0x800000000 +#ifndef CFG_SYS_PCIE3_PHYS_SIZE +#define CFG_SYS_PCIE3_PHYS_SIZE 0x800000000 #endif -#define CONFIG_SYS_PCIE4_PHYS_SIZE 0x800000000 +#define CFG_SYS_PCIE4_PHYS_SIZE 0x800000000 #define SYS_PCIE5_PHYS_SIZE 0x800000000 #define SYS_PCIE6_PHYS_SIZE 0x800000000 #endif @@ -83,9 +83,9 @@ #define CONFIG_SYS_FSL_QBMAN_SIZE 0x10000000 #define CONFIG_SYS_FSL_DRAM_BASE2 0x880000000 #define CONFIG_SYS_FSL_DRAM_SIZE2 0x780000000 /* 30GB */ -#define CONFIG_SYS_PCIE1_PHYS_SIZE 0x800000000 -#define CONFIG_SYS_PCIE2_PHYS_SIZE 0x800000000 -#define CONFIG_SYS_PCIE3_PHYS_SIZE 0x800000000 +#define CFG_SYS_PCIE1_PHYS_SIZE 0x800000000 +#define CFG_SYS_PCIE2_PHYS_SIZE 0x800000000 +#define CFG_SYS_PCIE3_PHYS_SIZE 0x800000000 #define CONFIG_SYS_FSL_DRAM_BASE3 0x8800000000 #define CONFIG_SYS_FSL_DRAM_SIZE3 0x7800000000 /* 480GB */ #endif diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h b/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h index 9cddb41a89..d5f63f4a7e 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h @@ -75,7 +75,7 @@ void fdt_fixup_icid(void *blob); #define SET_USB_ICID(usb_num, compat, streamid) \ SET_SCFG_ICID(compat, streamid, usb##usb_num##_icid,\ - CONFIG_SYS_XHCI_USB##usb_num##_ADDR) + CFG_SYS_XHCI_USB##usb_num##_ADDR) #define SET_SATA_ICID(compat, streamid) \ SET_SCFG_ICID(compat, streamid, sata_icid,\ @@ -142,7 +142,7 @@ extern int fman_icid_tbl_sz; #define SET_USB_ICID(usb_num, compat, streamid) \ SET_GUR_ICID(compat, streamid, usb##usb_num##_amqr,\ - CONFIG_SYS_XHCI_USB##usb_num##_ADDR) + CFG_SYS_XHCI_USB##usb_num##_ADDR) #define SET_SATA_ICID(sata_num, compat, streamid) \ SET_GUR_ICID(compat, streamid, sata##sata_num##_amqr, \ diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h index e8bd8d2713..9794db0449 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h @@ -11,11 +11,11 @@ #include <linux/bitops.h> #endif -#define CONFIG_SYS_DCSRBAR 0x20000000 -#define CONFIG_SYS_DCSR_DCFG_ADDR (CONFIG_SYS_DCSRBAR + 0x00140000) +#define CFG_SYS_DCSRBAR 0x20000000 +#define CFG_SYS_DCSR_DCFG_ADDR (CFG_SYS_DCSRBAR + 0x00140000) #define CFG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000) -#define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x00530000) +#define CFG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x00530000) #define SYS_FSL_QSPI_ADDR (CONFIG_SYS_IMMR + 0x00550000) #define CFG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x00560000) #define CFG_SYS_FSL_CSU_ADDR (CONFIG_SYS_IMMR + 0x00510000) @@ -26,44 +26,41 @@ #define CFG_SYS_FSL_QMAN_ADDR (CONFIG_SYS_IMMR + 0x00880000) #define CFG_SYS_FSL_SERDES_ADDR (CONFIG_SYS_IMMR + 0x00ea0000) #define CFG_SYS_FSL_CLK_ADDR (CONFIG_SYS_IMMR + 0x00ee1000) -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011c0500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011c0600) -#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_IMMR + 0x011d0500) -#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_IMMR + 0x011d0600) -#define CONFIG_SYS_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x01f00000) -#define CONFIG_SYS_XHCI_USB2_ADDR (CONFIG_SYS_IMMR + 0x02000000) -#define CONFIG_SYS_XHCI_USB3_ADDR (CONFIG_SYS_IMMR + 0x02100000) -#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000) -#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000) -#define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_IMMR + 0x2600000) -#define CONFIG_SYS_SEC_MON_ADDR (CONFIG_SYS_IMMR + 0xe90000) -#define CONFIG_SYS_SFP_ADDR (CONFIG_SYS_IMMR + 0xe80200) - -#define CONFIG_SYS_BMAN_NUM_PORTALS 10 -#define CONFIG_SYS_BMAN_MEM_BASE 0x508000000 -#define CONFIG_SYS_BMAN_MEM_PHYS (0xf00000000ull + \ - CONFIG_SYS_BMAN_MEM_BASE) -#define CONFIG_SYS_BMAN_MEM_SIZE 0x08000000 -#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x10000 -#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x10000 -#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE -#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ - CONFIG_SYS_BMAN_CENA_SIZE) -#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0x3E80 -#define CONFIG_SYS_QMAN_NUM_PORTALS 10 -#define CONFIG_SYS_QMAN_MEM_BASE 0x500000000 -#define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE -#define CONFIG_SYS_QMAN_MEM_SIZE 0x08000000 -#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x10000 -#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x10000 -#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE -#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ - CONFIG_SYS_QMAN_CENA_SIZE) -#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0x3680 +#define CFG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011c0500) +#define CFG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011c0600) +#define CFG_SYS_NS16550_COM3 (CONFIG_SYS_IMMR + 0x011d0500) +#define CFG_SYS_NS16550_COM4 (CONFIG_SYS_IMMR + 0x011d0600) +#define CFG_SYS_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x01f00000) +#define CFG_SYS_XHCI_USB2_ADDR (CONFIG_SYS_IMMR + 0x02000000) +#define CFG_SYS_XHCI_USB3_ADDR (CONFIG_SYS_IMMR + 0x02100000) +#define CFG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000) +#define CFG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000) +#define CFG_SYS_SEC_MON_ADDR (CONFIG_SYS_IMMR + 0xe90000) +#define CFG_SYS_SFP_ADDR (CONFIG_SYS_IMMR + 0xe80200) + +#define CFG_SYS_BMAN_NUM_PORTALS 10 +#define CFG_SYS_BMAN_MEM_BASE 0x508000000 +#define CFG_SYS_BMAN_MEM_PHYS (0xf00000000ull + \ + CFG_SYS_BMAN_MEM_BASE) +#define CFG_SYS_BMAN_MEM_SIZE 0x08000000 +#define CFG_SYS_BMAN_SP_CENA_SIZE 0x10000 +#define CFG_SYS_BMAN_SP_CINH_SIZE 0x10000 +#define CFG_SYS_BMAN_CENA_BASE CFG_SYS_BMAN_MEM_BASE +#define CFG_SYS_BMAN_CENA_SIZE (CFG_SYS_BMAN_MEM_SIZE >> 1) +#define CFG_SYS_BMAN_CINH_BASE (CFG_SYS_BMAN_MEM_BASE + \ + CFG_SYS_BMAN_CENA_SIZE) +#define CFG_SYS_BMAN_CINH_SIZE (CFG_SYS_BMAN_MEM_SIZE >> 1) +#define CFG_SYS_BMAN_SWP_ISDR_REG 0x3E80 +#define CFG_SYS_QMAN_NUM_PORTALS 10 +#define CFG_SYS_QMAN_MEM_BASE 0x500000000 +#define CFG_SYS_QMAN_MEM_PHYS CFG_SYS_QMAN_MEM_BASE +#define CFG_SYS_QMAN_MEM_SIZE 0x08000000 +#define CFG_SYS_QMAN_SP_CINH_SIZE 0x10000 +#define CFG_SYS_QMAN_CENA_SIZE (CFG_SYS_QMAN_MEM_SIZE >> 1) +#define CFG_SYS_QMAN_CINH_BASE (CFG_SYS_QMAN_MEM_BASE + \ + CFG_SYS_QMAN_CENA_SIZE) +#define CFG_SYS_QMAN_CINH_SIZE (CFG_SYS_QMAN_MEM_SIZE >> 1) +#define CFG_SYS_QMAN_SWP_ISDR_REG 0x3680 #define CFG_SYS_FSL_TIMER_ADDR 0x02b00000 @@ -93,9 +90,9 @@ #define QDMA_BASE_ADDR (CONFIG_SYS_IMMR + 0x07380000) #define QMAN_CQSIDR_REG 0x20a80 -#define CONFIG_SYS_PCIE1_PHYS_ADDR 0x4000000000ULL -#define CONFIG_SYS_PCIE2_PHYS_ADDR 0x4800000000ULL -#define CONFIG_SYS_PCIE3_PHYS_ADDR 0x5000000000ULL +#define CFG_SYS_PCIE1_PHYS_ADDR 0x4000000000ULL +#define CFG_SYS_PCIE2_PHYS_ADDR 0x4800000000ULL +#define CFG_SYS_PCIE3_PHYS_ADDR 0x5000000000ULL /* LUT registers */ #ifdef CONFIG_ARCH_LS1012A #define PCIE_LUT_BASE 0xC0000 @@ -137,20 +134,20 @@ #define TP_CLUSTER_INIT_MASK 0x0000003f /* initiator mask */ #define TP_INIT_PER_CLUSTER 4 -#ifndef CONFIG_SYS_CCSRBAR -#define CONFIG_SYS_CCSRBAR 0x01000000 +#ifndef CFG_SYS_CCSRBAR +#define CFG_SYS_CCSRBAR 0x01000000 #endif -#ifndef CONFIG_SYS_CCSRBAR_PHYS_HIGH -#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0 +#ifndef CFG_SYS_CCSRBAR_PHYS_HIGH +#define CFG_SYS_CCSRBAR_PHYS_HIGH 0 #endif -#ifndef CONFIG_SYS_CCSRBAR_PHYS_LOW -#define CONFIG_SYS_CCSRBAR_PHYS_LOW 0x01000000 +#ifndef CFG_SYS_CCSRBAR_PHYS_LOW +#define CFG_SYS_CCSRBAR_PHYS_LOW 0x01000000 #endif -#define CONFIG_SYS_CCSRBAR_PHYS ((CONFIG_SYS_CCSRBAR_PHYS_HIGH * 1ull) << 32 | \ - CONFIG_SYS_CCSRBAR_PHYS_LOW) +#define CFG_SYS_CCSRBAR_PHYS ((CFG_SYS_CCSRBAR_PHYS_HIGH * 1ull) << 32 | \ + CFG_SYS_CCSRBAR_PHYS_LOW) struct sys_info { unsigned long freq_processor[CONFIG_MAX_CPUS]; @@ -160,7 +157,7 @@ struct sys_info { unsigned long freq_localbus; unsigned long freq_cga_m2; #ifdef CONFIG_SYS_DPAA_FMAN - unsigned long freq_fman[CONFIG_SYS_NUM_FMAN]; + unsigned long freq_fman[CFG_SYS_NUM_FMAN]; #endif unsigned long freq_qman; }; diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h index f1ffb2327d..ca5e33379b 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h @@ -33,10 +33,10 @@ #define FSL_ESDHC1_BASE_ADDR CFG_SYS_FSL_ESDHC_ADDR #define FSL_ESDHC2_BASE_ADDR (CONFIG_SYS_IMMR + 0x01150000) #ifndef CONFIG_NXP_LSCH3_2 -#define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x01240000) +#define CFG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x01240000) #endif -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011C0500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011C0600) +#define CFG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011C0500) +#define CFG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011C0600) #define SYS_FSL_LS2080A_LS2085A_TIMER_ADDR 0x023d0000 #define CFG_SYS_FSL_TIMER_ADDR 0x023e0000 #define CFG_SYS_FSL_PMU_CLTBENR (CFG_SYS_FSL_PMU_ADDR + \ @@ -67,8 +67,8 @@ #define GPIO4_GPDIR_ADDR (GPIO4_BASE_ADDR + 0x0) #define GPIO4_GPDAT_ADDR (GPIO4_BASE_ADDR + 0x8) -#define CONFIG_SYS_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x02100000) -#define CONFIG_SYS_XHCI_USB2_ADDR (CONFIG_SYS_IMMR + 0x02110000) +#define CFG_SYS_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x02100000) +#define CFG_SYS_XHCI_USB2_ADDR (CONFIG_SYS_IMMR + 0x02110000) /* TZ Address Space Controller Definitions */ #define TZASC1_BASE 0x01100000 /* as per CCSR map. */ @@ -105,7 +105,7 @@ #define GPU_BASE_ADDR (CONFIG_SYS_IMMR + 0x0e0c0000) /* SFP */ -#define CONFIG_SYS_SFP_ADDR (CONFIG_SYS_IMMR + 0x00e80200) +#define CFG_SYS_SFP_ADDR (CONFIG_SYS_IMMR + 0x00e80200) /* SEC */ #define CFG_SYS_FSL_SEC_OFFSET 0x07000000ull @@ -173,7 +173,7 @@ #endif /* Security Monitor */ -#define CONFIG_SYS_SEC_MON_ADDR (CONFIG_SYS_IMMR + 0x00e90000) +#define CFG_SYS_SEC_MON_ADDR (CONFIG_SYS_IMMR + 0x00e90000) /* MMU 500 */ #define SMMU_SCR0 (SMMU_BASE + 0x0) @@ -192,37 +192,35 @@ /* PCIe */ -#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000) -#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000) -#define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_IMMR + 0x2600000) -#define CONFIG_SYS_PCIE4_ADDR (CONFIG_SYS_IMMR + 0x2700000) +#define CFG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000) +#define CFG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000) #if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A) #define SYS_PCIE5_ADDR (CONFIG_SYS_IMMR + 0x2800000) #define SYS_PCIE6_ADDR (CONFIG_SYS_IMMR + 0x2900000) #endif #if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A) -#define CONFIG_SYS_PCIE1_PHYS_ADDR 0x8000000000ULL -#define CONFIG_SYS_PCIE2_PHYS_ADDR 0x8800000000ULL -#define CONFIG_SYS_PCIE3_PHYS_ADDR 0x9000000000ULL -#define CONFIG_SYS_PCIE4_PHYS_ADDR 0x9800000000ULL +#define CFG_SYS_PCIE1_PHYS_ADDR 0x8000000000ULL +#define CFG_SYS_PCIE2_PHYS_ADDR 0x8800000000ULL +#define CFG_SYS_PCIE3_PHYS_ADDR 0x9000000000ULL +#define CFG_SYS_PCIE4_PHYS_ADDR 0x9800000000ULL #define SYS_PCIE5_PHYS_ADDR 0xa000000000ULL #define SYS_PCIE6_PHYS_ADDR 0xa800000000ULL #elif CONFIG_ARCH_LS1088A -#define CONFIG_SYS_PCIE1_PHYS_ADDR 0x2000000000ULL -#define CONFIG_SYS_PCIE2_PHYS_ADDR 0x2800000000ULL -#define CONFIG_SYS_PCIE3_PHYS_ADDR 0x3000000000ULL +#define CFG_SYS_PCIE1_PHYS_ADDR 0x2000000000ULL +#define CFG_SYS_PCIE2_PHYS_ADDR 0x2800000000ULL +#define CFG_SYS_PCIE3_PHYS_ADDR 0x3000000000ULL #elif CONFIG_ARCH_LS1028A -#define CONFIG_SYS_PCIE1_PHYS_ADDR 0x8000000000ULL -#define CONFIG_SYS_PCIE2_PHYS_ADDR 0x8800000000ULL -#define CONFIG_SYS_PCIE3_PHYS_ADDR 0x01f0000000ULL +#define CFG_SYS_PCIE1_PHYS_ADDR 0x8000000000ULL +#define CFG_SYS_PCIE2_PHYS_ADDR 0x8800000000ULL +#define CFG_SYS_PCIE3_PHYS_ADDR 0x01f0000000ULL /* this is used by integrated PCI on LS1028, includes ECAM and register space */ -#define CONFIG_SYS_PCIE3_PHYS_SIZE 0x0010000000ULL +#define CFG_SYS_PCIE3_PHYS_SIZE 0x0010000000ULL #else -#define CONFIG_SYS_PCIE1_PHYS_ADDR 0x1000000000ULL -#define CONFIG_SYS_PCIE2_PHYS_ADDR 0x1200000000ULL -#define CONFIG_SYS_PCIE3_PHYS_ADDR 0x1400000000ULL -#define CONFIG_SYS_PCIE4_PHYS_ADDR 0x1600000000ULL +#define CFG_SYS_PCIE1_PHYS_ADDR 0x1000000000ULL +#define CFG_SYS_PCIE2_PHYS_ADDR 0x1200000000ULL +#define CFG_SYS_PCIE3_PHYS_ADDR 0x1400000000ULL +#define CFG_SYS_PCIE4_PHYS_ADDR 0x1600000000ULL #endif /* Device Configuration */ @@ -306,7 +304,7 @@ struct sys_info { unsigned long freq_localbus; unsigned long freq_qe; #ifdef CONFIG_SYS_DPAA_FMAN - unsigned long freq_fman[CONFIG_SYS_NUM_FMAN]; + unsigned long freq_fman[CFG_SYS_NUM_FMAN]; #endif #ifdef CONFIG_SYS_DPAA_QBMAN unsigned long freq_qman; diff --git a/arch/arm/include/asm/arch-lpc32xx/config.h b/arch/arm/include/asm/arch-lpc32xx/config.h index dc414c7d84..41160384a4 100644 --- a/arch/arm/include/asm/arch-lpc32xx/config.h +++ b/arch/arm/include/asm/arch-lpc32xx/config.h @@ -11,19 +11,11 @@ /* Basic CPU architecture */ -/* UART configuration */ -#if (CONFIG_CONS_INDEX == 1) || (CONFIG_CONS_INDEX == 2) || \ - (CONFIG_CONS_INDEX == 7) -#if !defined(CONFIG_LPC32XX_HSUART) -#define CONFIG_LPC32XX_HSUART -#endif -#endif - -#if !defined(CONFIG_SYS_NS16550_CLK) -#define CONFIG_SYS_NS16550_CLK 13000000 +#if !defined(CFG_SYS_NS16550_CLK) +#define CFG_SYS_NS16550_CLK 13000000 #endif -#define CONFIG_SYS_BAUDRATE_TABLE \ +#define CFG_SYS_BAUDRATE_TABLE \ { 9600, 19200, 38400, 57600, 115200, 230400, 460800 } /* NAND */ @@ -32,24 +24,24 @@ #define NAND_SMALL_BLOCK_PAGE_SIZE 0x200 #if (CONFIG_SYS_NAND_PAGE_SIZE == NAND_LARGE_BLOCK_PAGE_SIZE) -#define CONFIG_SYS_NAND_ECCPOS { 40, 41, 42, 43, 44, 45, 46, 47, \ +#define CFG_SYS_NAND_ECCPOS { 40, 41, 42, 43, 44, 45, 46, 47, \ 48, 49, 50, 51, 52, 53, 54, 55, \ 56, 57, 58, 59, 60, 61, 62, 63, } #elif (CONFIG_SYS_NAND_PAGE_SIZE == NAND_SMALL_BLOCK_PAGE_SIZE) -#define CONFIG_SYS_NAND_ECCPOS { 10, 11, 12, 13, 14, 15, } +#define CFG_SYS_NAND_ECCPOS { 10, 11, 12, 13, 14, 15, } #else #error "CONFIG_SYS_NAND_PAGE_SIZE set to an invalid value" #endif -#define CONFIG_SYS_NAND_ECCSIZE 0x100 -#define CONFIG_SYS_NAND_ECCBYTES 3 +#define CFG_SYS_NAND_ECCSIZE 0x100 +#define CFG_SYS_NAND_ECCBYTES 3 #endif /* CONFIG_NAND_LPC32XX_SLC */ /* NOR Flash */ /* USB OHCI */ #if defined(CONFIG_USB_OHCI_LPC32XX) -#define CONFIG_SYS_USB_OHCI_REGS_BASE USB_BASE +#define CFG_SYS_USB_OHCI_REGS_BASE USB_BASE #endif #endif /* _LPC32XX_CONFIG_H */ diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h index e85918eb7e..d0abbdadf0 100644 --- a/arch/arm/include/asm/arch-ls102xa/config.h +++ b/arch/arm/include/asm/arch-ls102xa/config.h @@ -11,36 +11,31 @@ #define OCRAM_BASE_S_ADDR 0x10010000 #define OCRAM_S_SIZE 0x00010000 -#define CONFIG_SYS_DCSRBAR 0x20000000 +#define CFG_SYS_DCSRBAR 0x20000000 -#define CONFIG_SYS_DCSR_DCFG_ADDR (CONFIG_SYS_DCSRBAR + 0x00220000) -#define SYS_FSL_DCSR_RCPM_ADDR (CONFIG_SYS_DCSRBAR + 0x00222000) +#define CFG_SYS_DCSR_DCFG_ADDR (CFG_SYS_DCSRBAR + 0x00220000) +#define SYS_FSL_DCSR_RCPM_ADDR (CFG_SYS_DCSRBAR + 0x00222000) #define SYS_FSL_GIC_ADDR (CONFIG_SYS_IMMR + 0x00400000) #define CFG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000) #define CFG_SYS_FSL_CSU_ADDR (CONFIG_SYS_IMMR + 0x00510000) -#define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x00530000) +#define CFG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x00530000) #define CFG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x00560000) #define CFG_SYS_FSL_SCFG_ADDR (CONFIG_SYS_IMMR + 0x00570000) #define CFG_SYS_FSL_SEC_ADDR (CONFIG_SYS_IMMR + 0x700000) #define CFG_SYS_FSL_JR0_ADDR (CONFIG_SYS_IMMR + 0x710000) -#define CONFIG_SYS_SEC_MON_ADDR (CONFIG_SYS_IMMR + 0x00e90000) -#define CONFIG_SYS_SFP_ADDR (CONFIG_SYS_IMMR + 0x00e80200) +#define CFG_SYS_SEC_MON_ADDR (CONFIG_SYS_IMMR + 0x00e90000) +#define CFG_SYS_SFP_ADDR (CONFIG_SYS_IMMR + 0x00e80200) #define CFG_SYS_FSL_SERDES_ADDR (CONFIG_SYS_IMMR + 0x00ea0000) #define CFG_SYS_FSL_GUTS_ADDR (CONFIG_SYS_IMMR + 0x00ee0000) #define CFG_SYS_FSL_LS1_CLK_ADDR (CONFIG_SYS_IMMR + 0x00ee1000) #define CFG_SYS_FSL_RCPM_ADDR (CONFIG_SYS_IMMR + 0x00ee2000) -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011c0500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011d0500) -#define CONFIG_SYS_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x02100000) +#define CFG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011c0500) +#define CFG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011d0500) +#define CFG_SYS_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x02100000) #define CFG_SYS_FSL_SEC_OFFSET 0x00700000 #define CFG_SYS_FSL_JR0_OFFSET 0x00710000 -#define CONFIG_SYS_TSEC1_OFFSET 0x01d10000 -#define CONFIG_SYS_MDIO1_OFFSET 0x01d24000 - -#define TSEC_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET) -#define MDIO_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MDIO1_OFFSET) #define SCTR_BASE_ADDR (CONFIG_SYS_IMMR + 0x01b00000) @@ -55,28 +50,27 @@ #define LPUART_BASE (CONFIG_SYS_IMMR + 0x01950000) -#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000) -#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000) +#define CFG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000) +#define CFG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000) -#define CONFIG_SYS_PCIE1_PHYS_BASE 0x4000000000ULL -#define CONFIG_SYS_PCIE2_PHYS_BASE 0x4800000000ULL -#define CONFIG_SYS_PCIE1_VIRT_ADDR 0x24000000UL -#define CONFIG_SYS_PCIE2_VIRT_ADDR 0x34000000UL -#define CONFIG_SYS_PCIE_MMAP_SIZE (192 * 1024 * 1024) /* 192M */ +#define CFG_SYS_PCIE1_PHYS_BASE 0x4000000000ULL +#define CFG_SYS_PCIE2_PHYS_BASE 0x4800000000ULL +#define CFG_SYS_PCIE1_VIRT_ADDR 0x24000000UL +#define CFG_SYS_PCIE2_VIRT_ADDR 0x34000000UL +#define CFG_SYS_PCIE_MMAP_SIZE (192 * 1024 * 1024) /* 192M */ /* * TLB will map VIRT_ADDR to (PHYS_BASE + VIRT_ADDR) * So 40bit PCIe PHY addr can directly be converted to a 32bit virtual addr. */ -#define CONFIG_SYS_PCIE1_PHYS_ADDR (CONFIG_SYS_PCIE1_PHYS_BASE + \ - CONFIG_SYS_PCIE1_VIRT_ADDR) -#define CONFIG_SYS_PCIE2_PHYS_ADDR (CONFIG_SYS_PCIE2_PHYS_BASE + \ - CONFIG_SYS_PCIE2_VIRT_ADDR) +#define CFG_SYS_PCIE1_PHYS_ADDR (CFG_SYS_PCIE1_PHYS_BASE + \ + CFG_SYS_PCIE1_VIRT_ADDR) +#define CFG_SYS_PCIE2_PHYS_ADDR (CFG_SYS_PCIE2_PHYS_BASE + \ + CFG_SYS_PCIE2_VIRT_ADDR) /* SATA */ #define AHCI_BASE_ADDR (CONFIG_SYS_IMMR + 0x02200000) #ifdef CONFIG_DDR_SPD -#define CONFIG_VERY_BIG_RAM -#define CONFIG_MAX_MEM_MAPPED ((phys_size_t)2 << 30) +#define CFG_MAX_MEM_MAPPED ((phys_size_t)2 << 30) #endif #define DCU_LAYER_MAX_NUM 16 diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h index b0acf67798..a0c3da7f46 100644 --- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h +++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h @@ -42,24 +42,24 @@ #define DCFG_DCSR_PORCR1 0 -#ifndef CONFIG_SYS_CCSRBAR -#define CONFIG_SYS_CCSRBAR CONFIG_SYS_IMMR +#ifndef CFG_SYS_CCSRBAR +#define CFG_SYS_CCSRBAR CONFIG_SYS_IMMR #endif -#ifndef CONFIG_SYS_CCSRBAR_PHYS_HIGH +#ifndef CFG_SYS_CCSRBAR_PHYS_HIGH #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0xf +#define CFG_SYS_CCSRBAR_PHYS_HIGH 0xf #else -#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0 +#define CFG_SYS_CCSRBAR_PHYS_HIGH 0 #endif #endif -#ifndef CONFIG_SYS_CCSRBAR_PHYS_LOW -#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_IMMR +#ifndef CFG_SYS_CCSRBAR_PHYS_LOW +#define CFG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_IMMR #endif -#define CONFIG_SYS_CCSRBAR_PHYS ((CONFIG_SYS_CCSRBAR_PHYS_HIGH * 1ull) << 32 | \ - CONFIG_SYS_CCSRBAR_PHYS_LOW) +#define CFG_SYS_CCSRBAR_PHYS ((CFG_SYS_CCSRBAR_PHYS_HIGH * 1ull) << 32 | \ + CFG_SYS_CCSRBAR_PHYS_LOW) struct sys_info { unsigned long freq_processor[CONFIG_MAX_CPUS]; diff --git a/arch/arm/include/asm/arch-ls102xa/ls102xa_stream_id.h b/arch/arm/include/asm/arch-ls102xa/ls102xa_stream_id.h index fb5ded8907..acd8c69f69 100644 --- a/arch/arm/include/asm/arch-ls102xa/ls102xa_stream_id.h +++ b/arch/arm/include/asm/arch-ls102xa/ls102xa_stream_id.h @@ -12,14 +12,14 @@ { .compat = name, \ .id = { idA }, .num_ids = 1, \ .reg_offset = off + CONFIG_SYS_IMMR, \ - .compat_offset = compatoff + CONFIG_SYS_CCSRBAR_PHYS, \ + .compat_offset = compatoff + CFG_SYS_CCSRBAR_PHYS, \ } #define SET_LIODN_ENTRY_2(name, idA, idB, off, compatoff) \ { .compat = name, \ .id = { idA, idB }, .num_ids = 2, \ .reg_offset = off + CONFIG_SYS_IMMR, \ - .compat_offset = compatoff + CONFIG_SYS_CCSRBAR_PHYS, \ + .compat_offset = compatoff + CFG_SYS_CCSRBAR_PHYS, \ } /* diff --git a/arch/arm/include/asm/arch-mx31/imx-regs.h b/arch/arm/include/asm/arch-mx31/imx-regs.h index d5c0ed8e6c..a0ab3a0e66 100644 --- a/arch/arm/include/asm/arch-mx31/imx-regs.h +++ b/arch/arm/include/asm/arch-mx31/imx-regs.h @@ -899,9 +899,9 @@ struct esdc_regs { * Generic timer support */ #ifdef CONFIG_MX31_CLK32 -#define CONFIG_SYS_TIMER_RATE CONFIG_MX31_CLK32 +#define CFG_SYS_TIMER_RATE CONFIG_MX31_CLK32 #else -#define CONFIG_SYS_TIMER_RATE 32768 +#define CFG_SYS_TIMER_RATE 32768 #endif #endif /* __ASM_ARCH_MX31_IMX_REGS_H */ diff --git a/arch/arm/include/asm/arch-rockchip/bootrom.h b/arch/arm/include/asm/arch-rockchip/bootrom.h index 0da78f30b6..4276a0f681 100644 --- a/arch/arm/include/asm/arch-rockchip/bootrom.h +++ b/arch/arm/include/asm/arch-rockchip/bootrom.h @@ -57,6 +57,6 @@ extern const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1]; /** * Locations of the boot-device identifier in SRAM */ -#define BROM_BOOTSOURCE_ID_ADDR (CONFIG_IRAM_BASE + 0x10) +#define BROM_BOOTSOURCE_ID_ADDR (CFG_IRAM_BASE + 0x10) #endif diff --git a/arch/arm/include/asm/arch-stv0991/stv0991_gpt.h b/arch/arm/include/asm/arch-stv0991/stv0991_gpt.h index 5b12d90d58..eb1ddca600 100644 --- a/arch/arm/include/asm/arch-stv0991/stv0991_gpt.h +++ b/arch/arm/include/asm/arch-stv0991/stv0991_gpt.h @@ -36,6 +36,6 @@ struct gpt_regs *const gpt1_regs_ptr = #define GPT_FREE_RUNNING 0xFFFF /* Timer, HZ specific defines */ -#define CONFIG_SYS_HZ_CLOCK ((27 * 1000 * 1000) / GPT_PRESCALER_128) +#define CFG_SYS_HZ_CLOCK ((27 * 1000 * 1000) / GPT_PRESCALER_128) #endif diff --git a/arch/arm/include/asm/arch-sunxi/i2c.h b/arch/arm/include/asm/arch-sunxi/i2c.h index 3525f22e7d..e3dcfdf370 100644 --- a/arch/arm/include/asm/arch-sunxi/i2c.h +++ b/arch/arm/include/asm/arch-sunxi/i2c.h @@ -8,16 +8,16 @@ #include <asm/arch/cpu.h> #ifdef CONFIG_I2C0_ENABLE -#define CONFIG_I2C_MVTWSI_BASE0 SUNXI_TWI0_BASE +#define CFG_I2C_MVTWSI_BASE0 SUNXI_TWI0_BASE #endif #ifdef CONFIG_I2C1_ENABLE -#define CONFIG_I2C_MVTWSI_BASE1 SUNXI_TWI1_BASE +#define CFG_I2C_MVTWSI_BASE1 SUNXI_TWI1_BASE #endif #ifdef CONFIG_R_I2C_ENABLE #define CONFIG_I2C_MVTWSI_BASE2 SUNXI_R_TWI_BASE #endif /* This is abp0-clk on sun4i/5i/7i / abp1-clk on sun6i/sun8i which is 24MHz */ -#define CONFIG_SYS_TCLK 24000000 +#define CFG_SYS_TCLK 24000000 #endif diff --git a/arch/arm/include/asm/arch-vf610/imx-regs.h b/arch/arm/include/asm/arch-vf610/imx-regs.h index 97211f4b12..fa3a97824f 100644 --- a/arch/arm/include/asm/arch-vf610/imx-regs.h +++ b/arch/arm/include/asm/arch-vf610/imx-regs.h @@ -103,9 +103,6 @@ #define QSPI0_AMBA_BASE 0x20000000 -/* MUX mode and PAD ctrl are in one register */ -#define CONFIG_IOMUX_SHARE_CONF_REG - #define FEC_QUIRK_ENET_MAC #define I2C_QUIRK_REG diff --git a/arch/arm/include/asm/emif.h b/arch/arm/include/asm/emif.h index 35424345bf..2141a4581c 100644 --- a/arch/arm/include/asm/emif.h +++ b/arch/arm/include/asm/emif.h @@ -583,7 +583,7 @@ (DMM_SDRC_MAP_EMIF1_AND_EMIF2 << EMIF_SDRC_MAP_SHIFT) |\ (DMM_SDRC_ADDR_SPC_SDRAM << EMIF_SDRC_ADDRSPC_SHIFT) |\ (DMM_SDRC_INTL_128B << EMIF_SDRC_INTL_SHIFT) |\ - (CONFIG_SYS_SDRAM_BASE << EMIF_SYS_ADDR_SHIFT)) + (CFG_SYS_SDRAM_BASE << EMIF_SYS_ADDR_SHIFT)) #define DMM_LISA_MAP_EMIF1_ONLY_BASE_VAL (\ (DMM_SDRC_MAP_EMIF1_ONLY << EMIF_SDRC_MAP_SHIFT)|\ diff --git a/arch/arm/include/asm/fsl_secure_boot.h b/arch/arm/include/asm/fsl_secure_boot.h index a4f4961fc8..6a9d198cb8 100644 --- a/arch/arm/include/asm/fsl_secure_boot.h +++ b/arch/arm/include/asm/fsl_secure_boot.h @@ -9,21 +9,6 @@ #ifdef CONFIG_CHAIN_OF_TRUST #ifndef CONFIG_SPL_BUILD -#ifndef CONFIG_SYS_RAMBOOT -/* The key used for verification of next level images - * is picked up from an Extension Table which has - * been verified by the ISBC (Internal Secure boot Code) - * in boot ROM of the SoC. - * The feature is only applicable in case of NOR boot and is - * not applicable in case of RAMBOOT (NAND, SD, SPI). - * For LS, this feature is available for all device if IE Table - * is copied to XIP memory - * Also, for LS, ISBC doesn't verify this table. - */ -#define CONFIG_FSL_ISBC_KEY_EXT - -#endif - #ifdef CONFIG_FSL_LS_PPA /* Define the key hash here if SRK used for signing PPA image is * different from SRK hash put in SFP used for U-Boot. diff --git a/arch/arm/include/asm/global_data.h b/arch/arm/include/asm/global_data.h index cd6112dfcd..9e746e380a 100644 --- a/arch/arm/include/asm/global_data.h +++ b/arch/arm/include/asm/global_data.h @@ -54,7 +54,7 @@ struct arch_global_data { unsigned long tlb_emerg; #endif #endif -#ifdef CONFIG_SYS_MEM_RESERVE_SECURE +#ifdef CFG_SYS_MEM_RESERVE_SECURE #define MEM_RESERVE_SECURE_SECURED 0x1 #define MEM_RESERVE_SECURE_MAINTAINED 0x2 #define MEM_RESERVE_SECURE_ADDR_MASK (~0x3) diff --git a/arch/arm/include/asm/iproc-common/configs.h b/arch/arm/include/asm/iproc-common/configs.h index 4733c0793c..ce831bc13a 100644 --- a/arch/arm/include/asm/iproc-common/configs.h +++ b/arch/arm/include/asm/iproc-common/configs.h @@ -8,10 +8,7 @@ #include <linux/stringify.h> -/* Architecture, CPU, chip, etc */ -#define CONFIG_IPROC - /* Memory Info */ -#define CONFIG_SYS_SDRAM_BASE 0x61000000 +#define CFG_SYS_SDRAM_BASE 0x61000000 #endif /* __IPROC_COMMON_CONFIGS_H */ diff --git a/arch/arm/include/asm/ti-common/davinci_nand.h b/arch/arm/include/asm/ti-common/davinci_nand.h index a4cc27e920..38a1a6ea0d 100644 --- a/arch/arm/include/asm/ti-common/davinci_nand.h +++ b/arch/arm/include/asm/ti-common/davinci_nand.h @@ -18,13 +18,13 @@ #define MASK_CLE 0x10 #define MASK_ALE 0x08 -#ifdef CONFIG_SYS_NAND_MASK_CLE +#ifdef CFG_SYS_NAND_MASK_CLE #undef MASK_CLE -#define MASK_CLE CONFIG_SYS_NAND_MASK_CLE +#define MASK_CLE CFG_SYS_NAND_MASK_CLE #endif -#ifdef CONFIG_SYS_NAND_MASK_ALE +#ifdef CFG_SYS_NAND_MASK_ALE #undef MASK_ALE -#define MASK_ALE CONFIG_SYS_NAND_MASK_ALE +#define MASK_ALE CFG_SYS_NAND_MASK_ALE #endif struct davinci_emif_regs { diff --git a/arch/arm/include/asm/ti-common/keystone_net.h b/arch/arm/include/asm/ti-common/keystone_net.h index 0852ce80a6..bedbcdc8ba 100644 --- a/arch/arm/include/asm/ti-common/keystone_net.h +++ b/arch/arm/include/asm/ti-common/keystone_net.h @@ -18,7 +18,7 @@ /* EMAC */ #ifdef CONFIG_KSNET_NETCP_V1_0 -#define GBETH_BASE (CONFIG_KSNET_NETCP_BASE + 0x00090000) +#define GBETH_BASE (CFG_KSNET_NETCP_BASE + 0x00090000) #define EMAC_EMACSL_BASE_ADDR (GBETH_BASE + 0x900) #define EMAC_MDIO_BASE_ADDR (GBETH_BASE + 0x300) #define EMAC_SGMII_BASE_ADDR (GBETH_BASE + 0x100) @@ -32,7 +32,7 @@ #elif defined CONFIG_KSNET_NETCP_V1_5 -#define GBETH_BASE (CONFIG_KSNET_NETCP_BASE + 0x00200000) +#define GBETH_BASE (CFG_KSNET_NETCP_BASE + 0x00200000) #define CPGMACSL_REG_RX_PRI_MAP 0x020 #define EMAC_EMACSL_BASE_ADDR (GBETH_BASE + 0x22000) #define EMAC_MDIO_BASE_ADDR (GBETH_BASE + 0x00f00) @@ -49,7 +49,7 @@ #define KEYSTONE2_EMAC_GIG_ENABLE -#define MAC_ID_BASE_ADDR CONFIG_KSNET_MAC_ID_BASE +#define MAC_ID_BASE_ADDR CFG_KSNET_MAC_ID_BASE /* MDIO module input frequency */ #ifdef CONFIG_SOC_K2G @@ -117,7 +117,7 @@ struct mac_sl_cfg { #define CPSW_CTL_VLAN_AWARE BIT(1) #define CPSW_CTL_FIFO_LOOPBACK BIT(0) -#define DEVICE_CPSW_NUM_PORTS CONFIG_KSNET_CPSW_NUM_PORTS +#define DEVICE_CPSW_NUM_PORTS CFG_KSNET_CPSW_NUM_PORTS #define DEVICE_N_GMACSL_PORTS (DEVICE_CPSW_NUM_PORTS - 1) #ifdef CONFIG_KSNET_NETCP_V1_0 @@ -190,14 +190,14 @@ struct mac_sl_cfg { /* PSS */ #ifdef CONFIG_KSNET_NETCP_V1_0 -#define DEVICE_PSTREAM_CFG_REG_ADDR (CONFIG_KSNET_NETCP_BASE + 0x604) +#define DEVICE_PSTREAM_CFG_REG_ADDR (CFG_KSNET_NETCP_BASE + 0x604) #define DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI 0x06060606 #define hw_config_streaming_switch()\ writel(DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI, DEVICE_PSTREAM_CFG_REG_ADDR); #elif defined CONFIG_KSNET_NETCP_V1_5 -#define DEVICE_PSTREAM_CFG_REG_ADDR (CONFIG_KSNET_NETCP_BASE + 0x500) +#define DEVICE_PSTREAM_CFG_REG_ADDR (CFG_KSNET_NETCP_BASE + 0x500) #define DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI 0x0 #define hw_config_streaming_switch()\ diff --git a/arch/arm/lib/asm-offsets.c b/arch/arm/lib/asm-offsets.c index 22fd541f9a..6de0ce9152 100644 --- a/arch/arm/lib/asm-offsets.c +++ b/arch/arm/lib/asm-offsets.c @@ -15,8 +15,7 @@ #include <linux/kbuild.h> #include <linux/arm-smccc.h> -#if defined(CONFIG_MX27) \ - || defined(CONFIG_MX51) || defined(CONFIG_MX53) +#if defined(CONFIG_MX51) || defined(CONFIG_MX53) #include <asm/arch/imx-regs.h> #endif @@ -35,32 +34,6 @@ int main(void) * code. Is it better to define the macros directly in headers? */ -#if defined(CONFIG_MX27) - DEFINE(AIPI1_PSR0, IMX_AIPI1_BASE + offsetof(struct aipi_regs, psr0)); - DEFINE(AIPI1_PSR1, IMX_AIPI1_BASE + offsetof(struct aipi_regs, psr1)); - DEFINE(AIPI2_PSR0, IMX_AIPI2_BASE + offsetof(struct aipi_regs, psr0)); - DEFINE(AIPI2_PSR1, IMX_AIPI2_BASE + offsetof(struct aipi_regs, psr1)); - - DEFINE(CSCR, IMX_PLL_BASE + offsetof(struct pll_regs, cscr)); - DEFINE(MPCTL0, IMX_PLL_BASE + offsetof(struct pll_regs, mpctl0)); - DEFINE(SPCTL0, IMX_PLL_BASE + offsetof(struct pll_regs, spctl0)); - DEFINE(PCDR0, IMX_PLL_BASE + offsetof(struct pll_regs, pcdr0)); - DEFINE(PCDR1, IMX_PLL_BASE + offsetof(struct pll_regs, pcdr1)); - DEFINE(PCCR0, IMX_PLL_BASE + offsetof(struct pll_regs, pccr0)); - DEFINE(PCCR1, IMX_PLL_BASE + offsetof(struct pll_regs, pccr1)); - - DEFINE(ESDCTL0_ROF, offsetof(struct esdramc_regs, esdctl0)); - DEFINE(ESDCFG0_ROF, offsetof(struct esdramc_regs, esdcfg0)); - DEFINE(ESDCTL1_ROF, offsetof(struct esdramc_regs, esdctl1)); - DEFINE(ESDCFG1_ROF, offsetof(struct esdramc_regs, esdcfg1)); - DEFINE(ESDMISC_ROF, offsetof(struct esdramc_regs, esdmisc)); - - DEFINE(GPCR, IMX_SYSTEM_CTL_BASE + - offsetof(struct system_control_regs, gpcr)); - DEFINE(FMCR, IMX_SYSTEM_CTL_BASE + - offsetof(struct system_control_regs, fmcr)); -#endif - #if defined(CONFIG_MX51) || defined(CONFIG_MX53) /* Round up to make sure size gives nice stack alignment */ DEFINE(CLKCTL_CCMR, offsetof(struct clkctl, ccr)); diff --git a/arch/arm/lib/bdinfo.c b/arch/arm/lib/bdinfo.c index 826e09e72c..5e6eaad968 100644 --- a/arch/arm/lib/bdinfo.c +++ b/arch/arm/lib/bdinfo.c @@ -29,7 +29,7 @@ void arch_print_bdinfo(void) struct bd_info *bd = gd->bd; bdinfo_print_num_l("arch_number", bd->bi_arch_number); -#ifdef CONFIG_SYS_MEM_RESERVE_SECURE +#ifdef CFG_SYS_MEM_RESERVE_SECURE if (gd->arch.secure_ram & MEM_RESERVE_SECURE_SECURED) { bdinfo_print_num_ll("Secure ram", gd->arch.secure_ram & diff --git a/arch/arm/lib/cache-pl310.c b/arch/arm/lib/cache-pl310.c index bbaaaa4157..d05314ee57 100644 --- a/arch/arm/lib/cache-pl310.c +++ b/arch/arm/lib/cache-pl310.c @@ -11,7 +11,7 @@ #include <config.h> #include <common.h> -struct pl310_regs *const pl310 = (struct pl310_regs *)CONFIG_SYS_PL310_BASE; +struct pl310_regs *const pl310 = (struct pl310_regs *)CFG_SYS_PL310_BASE; static void pl310_cache_sync(void) { diff --git a/arch/arm/lib/cache.c b/arch/arm/lib/cache.c index a2bf2e57b9..1a589c7e2a 100644 --- a/arch/arm/lib/cache.c +++ b/arch/arm/lib/cache.c @@ -152,7 +152,7 @@ __weak int arm_reserve_mmu(void) debug("TLB table from %08lx to %08lx\n", gd->arch.tlb_addr, gd->arch.tlb_addr + gd->arch.tlb_size); -#ifdef CONFIG_SYS_MEM_RESERVE_SECURE +#ifdef CFG_SYS_MEM_RESERVE_SECURE /* * Record allocated tlb_addr in case gd->tlb_addr to be overwritten * with location within secure ram. diff --git a/arch/arm/lib/relocate.S b/arch/arm/lib/relocate.S index dd6f2e3bd5..345e282e3e 100644 --- a/arch/arm/lib/relocate.S +++ b/arch/arm/lib/relocate.S @@ -23,9 +23,8 @@ */ .section .text.relocate_vectors,"ax",%progbits - .weak relocate_vectors -ENTRY(relocate_vectors) +WEAK(relocate_vectors) #ifdef CONFIG_CPU_V7M /* diff --git a/arch/arm/lib/vectors.S b/arch/arm/lib/vectors.S index a54c84b062..7cf7d1636f 100644 --- a/arch/arm/lib/vectors.S +++ b/arch/arm/lib/vectors.S @@ -83,8 +83,8 @@ */ _start: -#ifdef CONFIG_SYS_DV_NOR_BOOT_CFG - .word CONFIG_SYS_DV_NOR_BOOT_CFG +#ifdef CFG_SYS_DV_NOR_BOOT_CFG + .word CFG_SYS_DV_NOR_BOOT_CFG #endif ARM_VECTORS #endif /* !defined(CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK) */ diff --git a/arch/arm/mach-aspeed/ast2500/board_common.c b/arch/arm/mach-aspeed/ast2500/board_common.c index aca2002231..bae1027184 100644 --- a/arch/arm/mach-aspeed/ast2500/board_common.c +++ b/arch/arm/mach-aspeed/ast2500/board_common.c @@ -31,7 +31,7 @@ DECLARE_GLOBAL_DATA_PTR; int board_init(void) { - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; return 0; } diff --git a/arch/arm/mach-aspeed/ast2600/board_common.c b/arch/arm/mach-aspeed/ast2600/board_common.c index 82ff21908f..dc6cdc35d1 100644 --- a/arch/arm/mach-aspeed/ast2600/board_common.c +++ b/arch/arm/mach-aspeed/ast2600/board_common.c @@ -54,7 +54,7 @@ int board_init(void) int i = 0, rc; struct udevice *dev; - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; while (1) { rc = uclass_get_device(UCLASS_MISC, i++, &dev); diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig index 094c9891f6..7c2e4ebbdb 100644 --- a/arch/arm/mach-at91/Kconfig +++ b/arch/arm/mach-at91/Kconfig @@ -85,7 +85,6 @@ config TARGET_GURNARD select AT91_WANTS_COMMON_PHY select BOARD_LATE_INIT select DM - select DM_ETH select DM_GPIO select DM_SERIAL select DM_SPI @@ -253,7 +252,6 @@ config TARGET_CORVUS select AT91SAM9M10G45 select AT91_WANTS_COMMON_PHY select DM - select DM_ETH select DM_GPIO select DM_SERIAL select SUPPORT_SPL @@ -271,7 +269,6 @@ config TARGET_TAURUS select AT91SAM9G20 select AT91_WANTS_COMMON_PHY select DM - select DM_ETH select DM_GPIO select DM_SERIAL select DM_SPI @@ -284,7 +281,6 @@ config TARGET_SMARTWEB select AT91SAM9260 select AT91_WANTS_COMMON_PHY select DM - select DM_ETH select DM_GPIO select DM_SERIAL select SUPPORT_SPL diff --git a/arch/arm/mach-at91/arm920t/clock.c b/arch/arm/mach-at91/arm920t/clock.c index c7440278d8..09ac66d619 100644 --- a/arch/arm/mach-at91/arm920t/clock.c +++ b/arch/arm/mach-at91/arm920t/clock.c @@ -26,7 +26,7 @@ static unsigned long at91_css_to_rate(unsigned long css) { switch (css) { case AT91_PMC_MCKR_CSS_SLOW: - return CONFIG_SYS_AT91_SLOW_CLOCK; + return CFG_SYS_AT91_SLOW_CLOCK; case AT91_PMC_MCKR_CSS_MAIN: return gd->arch.main_clk_rate_hz; case AT91_PMC_MCKR_CSS_PLLA: @@ -107,7 +107,7 @@ int at91_clock_init(unsigned long main_clock) { unsigned freq, mckr; at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; -#ifndef CONFIG_SYS_AT91_MAIN_CLOCK +#ifndef CFG_SYS_AT91_MAIN_CLOCK unsigned tmp; /* * When the bootloader initialized the main oscillator correctly, @@ -120,7 +120,7 @@ int at91_clock_init(unsigned long main_clock) tmp = readl(&pmc->mcfr); } while (!(tmp & AT91_PMC_MCFR_MAINRDY)); tmp &= AT91_PMC_MCFR_MAINF_MASK; - main_clock = tmp * (CONFIG_SYS_AT91_SLOW_CLOCK / 16); + main_clock = tmp * (CFG_SYS_AT91_SLOW_CLOCK / 16); } #endif gd->arch.main_clk_rate_hz = main_clock; diff --git a/arch/arm/mach-at91/arm920t/cpu.c b/arch/arm/mach-at91/arm920t/cpu.c index 44c079c0fd..9bf03fd68e 100644 --- a/arch/arm/mach-at91/arm920t/cpu.c +++ b/arch/arm/mach-at91/arm920t/cpu.c @@ -16,11 +16,11 @@ #include <asm/arch/hardware.h> #include <asm/arch/clk.h> -#ifndef CONFIG_SYS_AT91_MAIN_CLOCK -#define CONFIG_SYS_AT91_MAIN_CLOCK 0 +#ifndef CFG_SYS_AT91_MAIN_CLOCK +#define CFG_SYS_AT91_MAIN_CLOCK 0 #endif int arch_cpu_init(void) { - return at91_clock_init(CONFIG_SYS_AT91_MAIN_CLOCK); + return at91_clock_init(CFG_SYS_AT91_MAIN_CLOCK); } diff --git a/arch/arm/mach-at91/arm920t/lowlevel_init.S b/arch/arm/mach-at91/arm920t/lowlevel_init.S index 57e51c8105..6b7d3cbc71 100644 --- a/arch/arm/mach-at91/arm920t/lowlevel_init.S +++ b/arch/arm/mach-at91/arm920t/lowlevel_init.S @@ -94,11 +94,11 @@ SMRDATA: .word AT91_ASM_MC_SMC_CSR0 .word CONFIG_SYS_SMC_CSR0_VAL .word AT91_ASM_PMC_PLLAR - .word CONFIG_SYS_PLLAR_VAL + .word CFG_SYS_PLLAR_VAL .word AT91_ASM_PMC_PLLBR .word CONFIG_SYS_PLLBR_VAL .word AT91_ASM_PMC_MCKR - .word CONFIG_SYS_MCKR_VAL + .word CFG_SYS_MCKR_VAL SMRDATAE: /* here there's a delay */ SMRDATA1: @@ -107,45 +107,45 @@ SMRDATA1: .word AT91_ASM_PIOC_BSR .word CONFIG_SYS_PIOC_BSR_VAL .word AT91_ASM_PIOC_PDR - .word CONFIG_SYS_PIOC_PDR_VAL + .word CFG_SYS_PIOC_PDR_VAL .word AT91_ASM_MC_EBI_CSA .word CONFIG_SYS_EBI_CSA_VAL .word AT91_ASM_MC_SDRAMC_CR - .word CONFIG_SYS_SDRC_CR_VAL + .word CFG_SYS_SDRC_CR_VAL .word AT91_ASM_MC_SDRAMC_MR - .word CONFIG_SYS_SDRC_MR_VAL - .word CONFIG_SYS_SDRAM - .word CONFIG_SYS_SDRAM_VAL + .word CFG_SYS_SDRC_MR_VAL + .word CFG_SYS_SDRAM + .word CFG_SYS_SDRAM_VAL .word AT91_ASM_MC_SDRAMC_MR - .word CONFIG_SYS_SDRC_MR_VAL1 - .word CONFIG_SYS_SDRAM - .word CONFIG_SYS_SDRAM_VAL - .word CONFIG_SYS_SDRAM - .word CONFIG_SYS_SDRAM_VAL - .word CONFIG_SYS_SDRAM - .word CONFIG_SYS_SDRAM_VAL - .word CONFIG_SYS_SDRAM - .word CONFIG_SYS_SDRAM_VAL - .word CONFIG_SYS_SDRAM - .word CONFIG_SYS_SDRAM_VAL - .word CONFIG_SYS_SDRAM - .word CONFIG_SYS_SDRAM_VAL - .word CONFIG_SYS_SDRAM - .word CONFIG_SYS_SDRAM_VAL - .word CONFIG_SYS_SDRAM - .word CONFIG_SYS_SDRAM_VAL + .word CFG_SYS_SDRC_MR_VAL1 + .word CFG_SYS_SDRAM + .word CFG_SYS_SDRAM_VAL + .word CFG_SYS_SDRAM + .word CFG_SYS_SDRAM_VAL + .word CFG_SYS_SDRAM + .word CFG_SYS_SDRAM_VAL + .word CFG_SYS_SDRAM + .word CFG_SYS_SDRAM_VAL + .word CFG_SYS_SDRAM + .word CFG_SYS_SDRAM_VAL + .word CFG_SYS_SDRAM + .word CFG_SYS_SDRAM_VAL + .word CFG_SYS_SDRAM + .word CFG_SYS_SDRAM_VAL + .word CFG_SYS_SDRAM + .word CFG_SYS_SDRAM_VAL .word AT91_ASM_MC_SDRAMC_MR - .word CONFIG_SYS_SDRC_MR_VAL2 - .word CONFIG_SYS_SDRAM1 - .word CONFIG_SYS_SDRAM_VAL + .word CFG_SYS_SDRC_MR_VAL2 + .word CFG_SYS_SDRAM1 + .word CFG_SYS_SDRAM_VAL .word AT91_ASM_MC_SDRAMC_TR - .word CONFIG_SYS_SDRC_TR_VAL - .word CONFIG_SYS_SDRAM - .word CONFIG_SYS_SDRAM_VAL + .word CFG_SYS_SDRC_TR_VAL + .word CFG_SYS_SDRAM + .word CFG_SYS_SDRAM_VAL .word AT91_ASM_MC_SDRAMC_MR - .word CONFIG_SYS_SDRC_MR_VAL3 - .word CONFIG_SYS_SDRAM - .word CONFIG_SYS_SDRAM_VAL + .word CFG_SYS_SDRC_MR_VAL3 + .word CFG_SYS_SDRAM + .word CFG_SYS_SDRAM_VAL SMRDATA1E: /* SMRDATA1 is 176 bytes long */ #endif /* CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) */ diff --git a/arch/arm/mach-at91/arm920t/timer.c b/arch/arm/mach-at91/arm920t/timer.c index c400e87813..8ef5764e31 100644 --- a/arch/arm/mach-at91/arm920t/timer.c +++ b/arch/arm/mach-at91/arm920t/timer.c @@ -27,7 +27,7 @@ DECLARE_GLOBAL_DATA_PTR; /* the number of clocks per CONFIG_SYS_HZ */ -#define TIMER_LOAD_VAL (CONFIG_SYS_HZ_CLOCK/CONFIG_SYS_HZ) +#define TIMER_LOAD_VAL (CFG_SYS_HZ_CLOCK/CONFIG_SYS_HZ) int timer_init(void) { @@ -92,7 +92,7 @@ void __udelay(unsigned long usec) u32 endtime; signed long diff; - tmo = CONFIG_SYS_HZ_CLOCK / 1000; + tmo = CFG_SYS_HZ_CLOCK / 1000; tmo *= usec; tmo /= 1000; diff --git a/arch/arm/mach-at91/arm926ejs/clock.c b/arch/arm/mach-at91/arm926ejs/clock.c index c68e0c0c3c..013daf43b7 100644 --- a/arch/arm/mach-at91/arm926ejs/clock.c +++ b/arch/arm/mach-at91/arm926ejs/clock.c @@ -26,7 +26,7 @@ static unsigned long at91_css_to_rate(unsigned long css) { switch (css) { case AT91_PMC_MCKR_CSS_SLOW: - return CONFIG_SYS_AT91_SLOW_CLOCK; + return CFG_SYS_AT91_SLOW_CLOCK; case AT91_PMC_MCKR_CSS_MAIN: return gd->arch.main_clk_rate_hz; case AT91_PMC_MCKR_CSS_PLLA: @@ -115,7 +115,7 @@ int at91_clock_init(unsigned long main_clock) { unsigned freq, mckr; at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; -#ifndef CONFIG_SYS_AT91_MAIN_CLOCK +#ifndef CFG_SYS_AT91_MAIN_CLOCK unsigned tmp; /* * When the bootloader initialized the main oscillator correctly, @@ -128,7 +128,7 @@ int at91_clock_init(unsigned long main_clock) tmp = readl(&pmc->mcfr); } while (!(tmp & AT91_PMC_MCFR_MAINRDY)); tmp &= AT91_PMC_MCFR_MAINF_MASK; - main_clock = tmp * (CONFIG_SYS_AT91_SLOW_CLOCK / 16); + main_clock = tmp * (CFG_SYS_AT91_SLOW_CLOCK / 16); } #endif gd->arch.main_clk_rate_hz = main_clock; diff --git a/arch/arm/mach-at91/arm926ejs/cpu.c b/arch/arm/mach-at91/arm926ejs/cpu.c index 761edb6df5..5e84b0a40e 100644 --- a/arch/arm/mach-at91/arm926ejs/cpu.c +++ b/arch/arm/mach-at91/arm926ejs/cpu.c @@ -15,13 +15,13 @@ #include <asm/arch/at91_gpbr.h> #include <asm/arch/clk.h> -#ifndef CONFIG_SYS_AT91_MAIN_CLOCK -#define CONFIG_SYS_AT91_MAIN_CLOCK 0 +#ifndef CFG_SYS_AT91_MAIN_CLOCK +#define CFG_SYS_AT91_MAIN_CLOCK 0 #endif int arch_cpu_init(void) { - return at91_clock_init(CONFIG_SYS_AT91_MAIN_CLOCK); + return at91_clock_init(CFG_SYS_AT91_MAIN_CLOCK); } void arch_preboot_os(void) diff --git a/arch/arm/mach-at91/arm926ejs/lowlevel_init.S b/arch/arm/mach-at91/arm926ejs/lowlevel_init.S index c51eee2f17..e159a74eea 100644 --- a/arch/arm/mach-at91/arm926ejs/lowlevel_init.S +++ b/arch/arm/mach-at91/arm926ejs/lowlevel_init.S @@ -21,8 +21,8 @@ #ifdef CONFIG_ATMEL_LEGACY #include <asm/arch/at91sam9_matrix.h> #endif -#ifndef CONFIG_SYS_MATRIX_EBICSA_VAL -#define CONFIG_SYS_MATRIX_EBICSA_VAL CONFIG_SYS_MATRIX_EBI0CSA_VAL +#ifndef CFG_SYS_MATRIX_EBICSA_VAL +#define CFG_SYS_MATRIX_EBICSA_VAL CFG_SYS_MATRIX_EBI0CSA_VAL #endif .globl lowlevel_init @@ -67,7 +67,7 @@ POS1: ldr r1, =(AT91_ASM_PMC_MOR) ldr r2, =(AT91_ASM_PMC_SR) /* Main oscillator Enable register PMC_MOR: */ - ldr r0, =CONFIG_SYS_MOR_VAL + ldr r0, =CFG_SYS_MOR_VAL str r0, [r1] /* Reading the PMC Status to detect when the Main Oscillator is enabled */ @@ -85,7 +85,7 @@ MOSCS_Loop: * ---------------------------------------------------------------------------- */ ldr r1, =(AT91_ASM_PMC_PLLAR) - ldr r0, =CONFIG_SYS_PLLAR_VAL + ldr r0, =CFG_SYS_PLLAR_VAL str r0, [r1] /* Reading the PMC Status register to detect when the PLLA is locked */ @@ -105,7 +105,7 @@ MOSCS_Loop1: ldr r1, =(AT91_ASM_PMC_MCKR) /* -Master Clock Controller register PMC_MCKR */ - ldr r0, =CONFIG_SYS_MCKR1_VAL + ldr r0, =CFG_SYS_MCKR1_VAL str r0, [r1] /* Reading the PMC Status to detect when the Master clock is ready */ @@ -116,7 +116,7 @@ MCKRDY_Loop: cmp r3, #AT91_PMC_IXR_MCKRDY bne MCKRDY_Loop - ldr r0, =CONFIG_SYS_MCKR2_VAL + ldr r0, =CFG_SYS_MCKR2_VAL str r0, [r1] /* Reading the PMC Status to detect when the Master clock is ready */ @@ -158,84 +158,84 @@ SDRAM_setup_end: SMRDATA: .word AT91_ASM_WDT_MR - .word CONFIG_SYS_WDTC_WDMR_VAL + .word CFG_SYS_WDTC_WDMR_VAL /* configure PIOx as EBI0 D[16-31] */ #if defined(CONFIG_AT91SAM9263) .word AT91_ASM_PIOD_PDR - .word CONFIG_SYS_PIOD_PDR_VAL1 + .word CFG_SYS_PIOD_PDR_VAL1 .word AT91_ASM_PIOD_PUDR - .word CONFIG_SYS_PIOD_PPUDR_VAL + .word CFG_SYS_PIOD_PPUDR_VAL .word AT91_ASM_PIOD_ASR - .word CONFIG_SYS_PIOD_PPUDR_VAL + .word CFG_SYS_PIOD_PPUDR_VAL #elif defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9261) \ || defined(CONFIG_AT91SAM9G20) .word AT91_ASM_PIOC_PDR - .word CONFIG_SYS_PIOC_PDR_VAL1 + .word CFG_SYS_PIOC_PDR_VAL1 .word AT91_ASM_PIOC_PUDR - .word CONFIG_SYS_PIOC_PPUDR_VAL + .word CFG_SYS_PIOC_PPUDR_VAL #endif .word AT91_ASM_MATRIX_CSA0 - .word CONFIG_SYS_MATRIX_EBICSA_VAL + .word CFG_SYS_MATRIX_EBICSA_VAL /* flash */ .word AT91_ASM_SMC_MODE0 - .word CONFIG_SYS_SMC0_MODE0_VAL + .word CFG_SYS_SMC0_MODE0_VAL .word AT91_ASM_SMC_CYCLE0 - .word CONFIG_SYS_SMC0_CYCLE0_VAL + .word CFG_SYS_SMC0_CYCLE0_VAL .word AT91_ASM_SMC_PULSE0 - .word CONFIG_SYS_SMC0_PULSE0_VAL + .word CFG_SYS_SMC0_PULSE0_VAL .word AT91_ASM_SMC_SETUP0 - .word CONFIG_SYS_SMC0_SETUP0_VAL + .word CFG_SYS_SMC0_SETUP0_VAL SMRDATA1: .word AT91_ASM_SDRAMC_MR - .word CONFIG_SYS_SDRC_MR_VAL1 + .word CFG_SYS_SDRC_MR_VAL1 .word AT91_ASM_SDRAMC_TR - .word CONFIG_SYS_SDRC_TR_VAL1 + .word CFG_SYS_SDRC_TR_VAL1 .word AT91_ASM_SDRAMC_CR - .word CONFIG_SYS_SDRC_CR_VAL + .word CFG_SYS_SDRC_CR_VAL .word AT91_ASM_SDRAMC_MDR - .word CONFIG_SYS_SDRC_MDR_VAL + .word CFG_SYS_SDRC_MDR_VAL .word AT91_ASM_SDRAMC_MR - .word CONFIG_SYS_SDRC_MR_VAL2 - .word CONFIG_SYS_SDRAM_BASE - .word CONFIG_SYS_SDRAM_VAL1 + .word CFG_SYS_SDRC_MR_VAL2 + .word CFG_SYS_SDRAM_BASE + .word CFG_SYS_SDRAM_VAL1 .word AT91_ASM_SDRAMC_MR - .word CONFIG_SYS_SDRC_MR_VAL3 - .word CONFIG_SYS_SDRAM_BASE - .word CONFIG_SYS_SDRAM_VAL2 - .word CONFIG_SYS_SDRAM_BASE - .word CONFIG_SYS_SDRAM_VAL3 - .word CONFIG_SYS_SDRAM_BASE - .word CONFIG_SYS_SDRAM_VAL4 - .word CONFIG_SYS_SDRAM_BASE - .word CONFIG_SYS_SDRAM_VAL5 - .word CONFIG_SYS_SDRAM_BASE - .word CONFIG_SYS_SDRAM_VAL6 - .word CONFIG_SYS_SDRAM_BASE - .word CONFIG_SYS_SDRAM_VAL7 - .word CONFIG_SYS_SDRAM_BASE - .word CONFIG_SYS_SDRAM_VAL8 - .word CONFIG_SYS_SDRAM_BASE - .word CONFIG_SYS_SDRAM_VAL9 + .word CFG_SYS_SDRC_MR_VAL3 + .word CFG_SYS_SDRAM_BASE + .word CFG_SYS_SDRAM_VAL2 + .word CFG_SYS_SDRAM_BASE + .word CFG_SYS_SDRAM_VAL3 + .word CFG_SYS_SDRAM_BASE + .word CFG_SYS_SDRAM_VAL4 + .word CFG_SYS_SDRAM_BASE + .word CFG_SYS_SDRAM_VAL5 + .word CFG_SYS_SDRAM_BASE + .word CFG_SYS_SDRAM_VAL6 + .word CFG_SYS_SDRAM_BASE + .word CFG_SYS_SDRAM_VAL7 + .word CFG_SYS_SDRAM_BASE + .word CFG_SYS_SDRAM_VAL8 + .word CFG_SYS_SDRAM_BASE + .word CFG_SYS_SDRAM_VAL9 .word AT91_ASM_SDRAMC_MR - .word CONFIG_SYS_SDRC_MR_VAL4 - .word CONFIG_SYS_SDRAM_BASE - .word CONFIG_SYS_SDRAM_VAL10 + .word CFG_SYS_SDRC_MR_VAL4 + .word CFG_SYS_SDRAM_BASE + .word CFG_SYS_SDRAM_VAL10 .word AT91_ASM_SDRAMC_MR - .word CONFIG_SYS_SDRC_MR_VAL5 - .word CONFIG_SYS_SDRAM_BASE - .word CONFIG_SYS_SDRAM_VAL11 + .word CFG_SYS_SDRC_MR_VAL5 + .word CFG_SYS_SDRAM_BASE + .word CFG_SYS_SDRAM_VAL11 .word AT91_ASM_SDRAMC_TR - .word CONFIG_SYS_SDRC_TR_VAL2 - .word CONFIG_SYS_SDRAM_BASE - .word CONFIG_SYS_SDRAM_VAL12 + .word CFG_SYS_SDRC_TR_VAL2 + .word CFG_SYS_SDRAM_BASE + .word CFG_SYS_SDRAM_VAL12 /* User reset enable*/ .word AT91_ASM_RSTC_MR - .word CONFIG_SYS_RSTC_RMR_VAL + .word CFG_SYS_RSTC_RMR_VAL #ifdef CONFIG_SYS_MATRIX_MCFG_REMAP /* MATRIX_MCFG - REMAP all masters */ .word AT91_ASM_MATRIX_MCFG diff --git a/arch/arm/mach-at91/armv7/clock.c b/arch/arm/mach-at91/armv7/clock.c index aa6bb6bf31..6bfa02d1d0 100644 --- a/arch/arm/mach-at91/armv7/clock.c +++ b/arch/arm/mach-at91/armv7/clock.c @@ -28,7 +28,7 @@ static unsigned long at91_css_to_rate(unsigned long css) { switch (css) { case AT91_PMC_MCKR_CSS_SLOW: - return CONFIG_SYS_AT91_SLOW_CLOCK; + return CFG_SYS_AT91_SLOW_CLOCK; case AT91_PMC_MCKR_CSS_MAIN: return gd->arch.main_clk_rate_hz; case AT91_PMC_MCKR_CSS_PLLA: @@ -58,7 +58,7 @@ int at91_clock_init(unsigned long main_clock) { unsigned freq, mckr; struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; -#ifndef CONFIG_SYS_AT91_MAIN_CLOCK +#ifndef CFG_SYS_AT91_MAIN_CLOCK unsigned tmp; /* * When the bootloader initialized the main oscillator correctly, @@ -71,7 +71,7 @@ int at91_clock_init(unsigned long main_clock) tmp = readl(&pmc->mcfr); } while (!(tmp & AT91_PMC_MCFR_MAINRDY)); tmp &= AT91_PMC_MCFR_MAINF_MASK; - main_clock = tmp * (CONFIG_SYS_AT91_SLOW_CLOCK / 16); + main_clock = tmp * (CFG_SYS_AT91_SLOW_CLOCK / 16); } #endif gd->arch.main_clk_rate_hz = main_clock; @@ -271,7 +271,7 @@ u32 at91_get_periph_generated_clk(u32 id) clk_source = regval & AT91_PMC_PCR_GCKCSS; switch (clk_source) { case AT91_PMC_PCR_GCKCSS_SLOW_CLK: - freq = CONFIG_SYS_AT91_SLOW_CLOCK; + freq = CFG_SYS_AT91_SLOW_CLOCK; break; case AT91_PMC_PCR_GCKCSS_MAIN_CLK: freq = gd->arch.main_clk_rate_hz; diff --git a/arch/arm/mach-at91/armv7/cpu.c b/arch/arm/mach-at91/armv7/cpu.c index 9b3753491e..616621a1f9 100644 --- a/arch/arm/mach-at91/armv7/cpu.c +++ b/arch/arm/mach-at91/armv7/cpu.c @@ -18,8 +18,8 @@ #include <asm/arch/at91_gpbr.h> #include <asm/arch/clk.h> -#ifndef CONFIG_SYS_AT91_MAIN_CLOCK -#define CONFIG_SYS_AT91_MAIN_CLOCK 0 +#ifndef CFG_SYS_AT91_MAIN_CLOCK +#define CFG_SYS_AT91_MAIN_CLOCK 0 #endif int arch_cpu_init(void) @@ -27,7 +27,7 @@ int arch_cpu_init(void) #if defined(CONFIG_CLK_CCF) return 0; #else - return at91_clock_init(CONFIG_SYS_AT91_MAIN_CLOCK); + return at91_clock_init(CFG_SYS_AT91_MAIN_CLOCK); #endif } diff --git a/arch/arm/mach-at91/armv7/sama7g5_devices.c b/arch/arm/mach-at91/armv7/sama7g5_devices.c index 0b702c7fb7..6f2c1fc914 100644 --- a/arch/arm/mach-at91/armv7/sama7g5_devices.c +++ b/arch/arm/mach-at91/armv7/sama7g5_devices.c @@ -4,7 +4,31 @@ * Eugen Hristev <eugen.hristev@microchip.com> */ +#include <asm/arch/sama7g5.h> + char *get_cpu_name(void) { - return "SAMA7G5"; + unsigned int extension_id = get_extension_chip_id(); + + if (cpu_is_sama7g5()) + switch (extension_id) { + case ARCH_EXID_SAMA7G51: + return "SAMA7G51"; + case ARCH_EXID_SAMA7G52: + return "SAMA7G52"; + case ARCH_EXID_SAMA7G53: + return "SAMA7G53"; + case ARCH_EXID_SAMA7G54: + return "SAMA7G54"; + case ARCH_EXID_SAMA7G54_D1G: + return "SAMA7G54 1Gb DDR3L SiP"; + case ARCH_EXID_SAMA7G54_D2G: + return "SAMA7G54 2Gb DDR3L SiP"; + case ARCH_EXID_SAMA7G54_D4G: + return "SAMA7G54 4Gb DDR3L SiP"; + default: + return "Unknown CPU type"; + } + else + return "Unknown CPU type"; } diff --git a/arch/arm/mach-at91/include/mach/at91sam9260.h b/arch/arm/mach-at91/include/mach/at91sam9260.h index 2daeb4fef8..103db26953 100644 --- a/arch/arm/mach-at91/include/mach/at91sam9260.h +++ b/arch/arm/mach-at91/include/mach/at91sam9260.h @@ -128,7 +128,7 @@ #define ATMEL_BASE_CS7 0x80000000 /* Timer */ -#define CONFIG_SYS_TIMER_COUNTER 0xfffffd3c +#define CFG_SYS_TIMER_COUNTER 0xfffffd3c /* * Other misc defines diff --git a/arch/arm/mach-at91/include/mach/at91sam9261.h b/arch/arm/mach-at91/include/mach/at91sam9261.h index d5de8d5551..2b252f1e1e 100644 --- a/arch/arm/mach-at91/include/mach/at91sam9261.h +++ b/arch/arm/mach-at91/include/mach/at91sam9261.h @@ -112,7 +112,7 @@ #define ATMEL_BASE_CS7 0x80000000 /* Timer */ -#define CONFIG_SYS_TIMER_COUNTER 0xfffffd3c +#define CFG_SYS_TIMER_COUNTER 0xfffffd3c /* * Other misc defines diff --git a/arch/arm/mach-at91/include/mach/at91sam9263.h b/arch/arm/mach-at91/include/mach/at91sam9263.h index c9fff934da..0aa1862567 100644 --- a/arch/arm/mach-at91/include/mach/at91sam9263.h +++ b/arch/arm/mach-at91/include/mach/at91sam9263.h @@ -127,7 +127,7 @@ #define ATMEL_BASE_CS7 0x80000000 /* Timer */ -#define CONFIG_SYS_TIMER_COUNTER 0xfffffd3c +#define CFG_SYS_TIMER_COUNTER 0xfffffd3c /* * Other misc defines diff --git a/arch/arm/mach-at91/include/mach/at91sam9g45.h b/arch/arm/mach-at91/include/mach/at91sam9g45.h index 588032582b..22116f375b 100644 --- a/arch/arm/mach-at91/include/mach/at91sam9g45.h +++ b/arch/arm/mach-at91/include/mach/at91sam9g45.h @@ -132,7 +132,7 @@ #define ATMEL_BASE_CS7 0x80000000 /* Timer */ -#define CONFIG_SYS_TIMER_COUNTER 0xfffffd3c +#define CFG_SYS_TIMER_COUNTER 0xfffffd3c /* * Other misc defines diff --git a/arch/arm/mach-at91/include/mach/at91sam9rl.h b/arch/arm/mach-at91/include/mach/at91sam9rl.h index 8f9155c9ea..b2c074e93e 100644 --- a/arch/arm/mach-at91/include/mach/at91sam9rl.h +++ b/arch/arm/mach-at91/include/mach/at91sam9rl.h @@ -112,7 +112,7 @@ #define ATMEL_BASE_CS5 0x60000000 /* Compact Flash Slot 1 */ /* Timer */ -#define CONFIG_SYS_TIMER_COUNTER 0xfffffd3c +#define CFG_SYS_TIMER_COUNTER 0xfffffd3c /* * Other misc defines diff --git a/arch/arm/mach-at91/include/mach/at91sam9x5.h b/arch/arm/mach-at91/include/mach/at91sam9x5.h index e3c494c5d5..0efb4a9f6d 100644 --- a/arch/arm/mach-at91/include/mach/at91sam9x5.h +++ b/arch/arm/mach-at91/include/mach/at91sam9x5.h @@ -162,7 +162,7 @@ #endif /* Timer */ -#define CONFIG_SYS_TIMER_COUNTER 0xfffffe3c +#define CFG_SYS_TIMER_COUNTER 0xfffffe3c /* * Other misc defines diff --git a/arch/arm/mach-at91/include/mach/sam9x60.h b/arch/arm/mach-at91/include/mach/sam9x60.h index c08d19c691..47c7c7209e 100644 --- a/arch/arm/mach-at91/include/mach/sam9x60.h +++ b/arch/arm/mach-at91/include/mach/sam9x60.h @@ -140,7 +140,7 @@ #define ATMEL_CPU_NAME get_cpu_name() /* Timer */ -#define CONFIG_SYS_TIMER_COUNTER 0xfffffe4c +#define CFG_SYS_TIMER_COUNTER 0xfffffe4c /* * Other misc defines diff --git a/arch/arm/mach-at91/include/mach/sama5d2.h b/arch/arm/mach-at91/include/mach/sama5d2.h index 5ff20e9573..567cdd3cba 100644 --- a/arch/arm/mach-at91/include/mach/sama5d2.h +++ b/arch/arm/mach-at91/include/mach/sama5d2.h @@ -238,7 +238,7 @@ #define cpu_is_sama5d2 _cpu_is_sama5d2 /* PIT Timer(PIT_PIIR) */ -#define CONFIG_SYS_TIMER_COUNTER 0xf804803c +#define CFG_SYS_TIMER_COUNTER 0xf804803c #ifndef __ASSEMBLY__ unsigned int get_chip_id(void); diff --git a/arch/arm/mach-at91/include/mach/sama5d3.h b/arch/arm/mach-at91/include/mach/sama5d3.h index 83f18a8148..9efcf5f4fa 100644 --- a/arch/arm/mach-at91/include/mach/sama5d3.h +++ b/arch/arm/mach-at91/include/mach/sama5d3.h @@ -185,7 +185,7 @@ #define CPU_HAS_PCR /* Timer */ -#define CONFIG_SYS_TIMER_COUNTER 0xfffffe3c +#define CFG_SYS_TIMER_COUNTER 0xfffffe3c /* * PMECC table in ROM diff --git a/arch/arm/mach-at91/include/mach/sama5d4.h b/arch/arm/mach-at91/include/mach/sama5d4.h index e2edb6a51b..9c80286ade 100644 --- a/arch/arm/mach-at91/include/mach/sama5d4.h +++ b/arch/arm/mach-at91/include/mach/sama5d4.h @@ -217,7 +217,7 @@ (get_extension_chip_id() == ARCH_EXID_SAMA5D44)) /* Timer */ -#define CONFIG_SYS_TIMER_COUNTER 0xfc06863c +#define CFG_SYS_TIMER_COUNTER 0xfc06863c /* * No PMECC Galois table in ROM diff --git a/arch/arm/mach-at91/include/mach/sama7-sfr.h b/arch/arm/mach-at91/include/mach/sama7-sfr.h new file mode 100644 index 0000000000..a987ff5465 --- /dev/null +++ b/arch/arm/mach-at91/include/mach/sama7-sfr.h @@ -0,0 +1,59 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Microchip SFR (Special Function Registers) registers for SAMA7 family. + * + * Copyright (C) 2022 Microchip Technology Inc. and its subsidiaries + * + * Author: Cristian Birsan <cristian.birsan@microchip.com> + */ + +#ifndef _LINUX_MFD_SYSCON_AT91_SAMA7_SFR_H +#define _LINUX_MFD_SYSCON_AT91_SAMA7_SFR_H + +#define SAMA7_SFR_OHCIICR 0x00 /* OHCI INT Configuration Register */ +#define SAMA7_SFR_OHCIISR 0x04 /* OHCI INT Status Register */ +/* 0x08 ~ 0xe3: Reserved */ +#define SAMA7_SFR_WPMR 0xe4 /* Write Protection Mode Register */ +#define SAMA7_SFR_WPSR 0xe4 /* Write Protection Status Register */ +/* 0xec ~ 0x200b: Reserved */ +#define SAMA7_SFR_DEBUG 0x200c /* Debug Register */ + +/* 0x2010 ~ 0x2027: Reserved */ +#define SAMA7_SFR_EHCIOHCI 0x2020 /* EHCI OHCI Clock Configuration Reg */ + +#define SAMA7_SFR_HSS_AXI_QOS 0x2028 /* HSS AXI QOS Register */ +#define SAMA7_SFR_UDDRC 0x202c /* UDDRC Register */ +#define SAMA7_SFR_CAN_SRAM_SEL 0x2030 /* CAN SRAM Select. Register */ +/* 0x2034 ~ 0x203f: Reserved */ + +#define SAMA7_SFR_UTMI0 0x2040 +#define SAMA7_SFR_UTMI0R(x) (SAMA7_SFR_UTMI0 + 4 * (x)) + +#define SAMA7_SFR_UTMI0R0 0x2040 /* UTMI0 Configuration Register */ +#define SAMA7_SFR_UTMI0R1 0x2044 /* UTMI1 Configuration Register */ +#define SAMA7_SFR_UTMI0R2 0x2048 /* UTMI2 Configuration Register */ + +/* Field definitions */ +#define SAMA7_SFR_OHCIICR_ARIE BIT(0) +#define SAMA7_SFR_OHCIICR_APPSTART BIT(1) +#define SAMA7_SFR_OHCIICR_USB_SUSP(x) BIT(8 + (x)) +#define SAMA7_SFR_OHCIICR_USB_SUSPEND GENMASK(10, 8) + +#define SAMA7_SFR_OHCIISR_RIS(x) BIT(x) + +#define SAMA7_SFR_WPMR_WPEN BIT(0) +#define SAMA7_SFR_WPMR_KEY 0x53465200 /* SFR in ASCII*/ +#define SAMA7_SFR_WPMR_WPKEY_MASK GENMASK(31, 8) + +#define SAMA7_SFR_WPSR_WPSRC_MASK GENMASK(23, 8) +#define SAMA7_SFR_WPSR_WPVS_MASK BIT(0) + +#define SAMA7_SFR_CAN_SRAM_UPPER(x) BIT(x) + +#define SAMA7_SFR_UTMI_RX_VBUS BIT(25) /* VBUS Valid bit */ +#define SAMA7_SFR_UTMI_RX_TX_PREEM_AMP_TUNE_1X BIT(23) /* TXPREEMPAMPTUNE 1x */ +#define SAMA7_SFR_UTMI_COMMONON BIT(3) /* PLL Common ON bit */ + +#define SAMA7_SFR_EHCIOHCI_PHYCLK BIT(1) /* Alternate PHY Clk */ + +#endif /* _LINUX_MFD_SYSCON_AT91_SAMA7_SFR_H */ diff --git a/arch/arm/mach-at91/include/mach/sama7g5.h b/arch/arm/mach-at91/include/mach/sama7g5.h index ae43e8700b..621a26f6eb 100644 --- a/arch/arm/mach-at91/include/mach/sama7g5.h +++ b/arch/arm/mach-at91/include/mach/sama7g5.h @@ -67,7 +67,35 @@ #define ATMEL_BASE_PIT64BC ATMEL_BASE_PIT64B0 +/* SAMA7G5 series chip id definitions */ +#define ARCH_ID_SAMA7G5 0x80162100 +#define ARCH_EXID_SAMA7G51 0x00000003 +#define ARCH_EXID_SAMA7G52 0x00000002 +#define ARCH_EXID_SAMA7G53 0x00000001 +#define ARCH_EXID_SAMA7G54 0x00000000 +#define ARCH_EXID_SAMA7G54_D1G 0x00000018 +#define ARCH_EXID_SAMA7G54_D2G 0x00000020 +#define ARCH_EXID_SAMA7G54_D4G 0x00000028 + +#define cpu_is_sama7g5() (get_chip_id() == ARCH_ID_SAMA7G5) +#define cpu_is_sama7g51() (cpu_is_sama7g5() && \ + (get_extension_chip_id() == ARCH_EXID_SAMA7G51)) +#define cpu_is_sama7g52() (cpu_is_sama7g5() && \ + (get_extension_chip_id() == ARCH_EXID_SAMA7G52)) +#define cpu_is_sama7g53() (cpu_is_sama7g5() && \ + (get_extension_chip_id() == ARCH_EXID_SAMA7G53)) +#define cpu_is_sama7g54() (cpu_is_sama7g5() && \ + (get_extension_chip_id() == ARCH_EXID_SAMA7G54)) +#define cpu_is_sama7g54d1g() (cpu_is_sama7g5() && \ + (get_extension_chip_id() == ARCH_EXID_SAMA7G54_D1G)) +#define cpu_is_sama7g54d2g() (cpu_is_sama7g5() && \ + (get_extension_chip_id() == ARCH_EXID_SAMA7G54_D2G)) +#define cpu_is_sama7g54d4g() (cpu_is_sama7g5() && \ + (get_extension_chip_id() == ARCH_EXID_SAMA7G54_D4G)) + #ifndef __ASSEMBLY__ +unsigned int get_chip_id(void); +unsigned int get_extension_chip_id(void); char *get_cpu_name(void); #endif diff --git a/arch/arm/mach-at91/spl_at91.c b/arch/arm/mach-at91/spl_at91.c index ea19ec322e..dfba9f730c 100644 --- a/arch/arm/mach-at91/spl_at91.c +++ b/arch/arm/mach-at91/spl_at91.c @@ -101,17 +101,17 @@ void board_init_f(ulong dummy) at91_pllicpr_init(0x00); /* Configure PLLA = MOSC * (PLL_MULA + 1) / PLL_DIVA */ - at91_plla_init(CONFIG_SYS_AT91_PLLA); + at91_plla_init(CFG_SYS_AT91_PLLA); /* PCK = PLLA = 2 * MCK */ - at91_mck_init(CONFIG_SYS_MCKR); + at91_mck_init(CFG_SYS_MCKR); /* Switch MCK on PLLA output */ - at91_mck_init(CONFIG_SYS_MCKR_CSS); + at91_mck_init(CFG_SYS_MCKR_CSS); -#if defined(CONFIG_SYS_AT91_PLLB) +#if defined(CFG_SYS_AT91_PLLB) /* Configure PLLB */ - at91_pllb_init(CONFIG_SYS_AT91_PLLB); + at91_pllb_init(CFG_SYS_AT91_PLLB); #endif /* Enable External Reset */ @@ -120,7 +120,7 @@ void board_init_f(ulong dummy) /* Initialize matrix */ matrix_init(); - gd->arch.mck_rate_hz = CONFIG_SYS_MASTER_CLOCK; + gd->arch.mck_rate_hz = CFG_SYS_MASTER_CLOCK; /* * init timer long enough for using in spl. */ diff --git a/arch/arm/mach-at91/spl_atmel.c b/arch/arm/mach-at91/spl_atmel.c index 217ed12e31..a30c4f6c07 100644 --- a/arch/arm/mach-at91/spl_atmel.c +++ b/arch/arm/mach-at91/spl_atmel.c @@ -124,7 +124,7 @@ void board_init_f(ulong dummy) /* PMC configuration */ at91_pmc_init(); - at91_clock_init(CONFIG_SYS_AT91_MAIN_CLOCK); + at91_clock_init(CFG_SYS_AT91_MAIN_CLOCK); matrix_init(); diff --git a/arch/arm/mach-davinci/cpu.c b/arch/arm/mach-davinci/cpu.c index 0f68f9fe59..dae60262f5 100644 --- a/arch/arm/mach-davinci/cpu.c +++ b/arch/arm/mach-davinci/cpu.c @@ -42,7 +42,7 @@ int clk_get(enum davinci_clk_ids id) int pll_out; unsigned int pll_base; - pll_out = CONFIG_SYS_OSCIN_FREQ; + pll_out = CFG_SYS_OSCIN_FREQ; if (id == DAVINCI_AUXCLK_CLKID) goto out; diff --git a/arch/arm/mach-davinci/da850_lowlevel.c b/arch/arm/mach-davinci/da850_lowlevel.c index 759c93747c..08c8f59252 100644 --- a/arch/arm/mach-davinci/da850_lowlevel.c +++ b/arch/arm/mach-davinci/da850_lowlevel.c @@ -185,9 +185,9 @@ static int da850_ddr_setup(void) setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_POWERDWN); } setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_IOPWRDWN); - writel(CONFIG_SYS_DA850_DDR2_DDRPHYCR, &dv_ddr2_regs_ctrl->ddrphycr); + writel(CFG_SYS_DA850_DDR2_DDRPHYCR, &dv_ddr2_regs_ctrl->ddrphycr); - if (CONFIG_SYS_DA850_DDR2_SDBCR & (1 << DV_DDR_SDCR_DDR2EN_SHIFT)) { + if (CFG_SYS_DA850_DDR2_SDBCR & (1 << DV_DDR_SDCR_DDR2EN_SHIFT)) { /* DDR2 */ clrbits_le32(&davinci_syscfg1_regs->ddr_slew, (1 << DDR_SLEW_DDR_PDENA_BIT) | @@ -211,19 +211,19 @@ static int da850_ddr_setup(void) * At the same time, set the TIMUNLOCK bit to allow changing * the timing registers */ - tmp = CONFIG_SYS_DA850_DDR2_SDBCR; + tmp = CFG_SYS_DA850_DDR2_SDBCR; tmp &= ~DV_DDR_BOOTUNLOCK; tmp |= DV_DDR_TIMUNLOCK; writel(tmp, &dv_ddr2_regs_ctrl->sdbcr); /* write memory configuration and timing */ - if (!(CONFIG_SYS_DA850_DDR2_SDBCR & (1 << DV_DDR_SDCR_DDR2EN_SHIFT))) { + if (!(CFG_SYS_DA850_DDR2_SDBCR & (1 << DV_DDR_SDCR_DDR2EN_SHIFT))) { /* MOBILE DDR only*/ - writel(CONFIG_SYS_DA850_DDR2_SDBCR2, + writel(CFG_SYS_DA850_DDR2_SDBCR2, &dv_ddr2_regs_ctrl->sdbcr2); } - writel(CONFIG_SYS_DA850_DDR2_SDTIMR, &dv_ddr2_regs_ctrl->sdtimr); - writel(CONFIG_SYS_DA850_DDR2_SDTIMR2, &dv_ddr2_regs_ctrl->sdtimr2); + writel(CFG_SYS_DA850_DDR2_SDTIMR, &dv_ddr2_regs_ctrl->sdtimr); + writel(CFG_SYS_DA850_DDR2_SDTIMR2, &dv_ddr2_regs_ctrl->sdtimr2); /* clear the TIMUNLOCK bit and write the value of the CL field */ tmp &= ~DV_DDR_TIMUNLOCK; @@ -233,7 +233,7 @@ static int da850_ddr_setup(void) * LPMODEN and MCLKSTOPEN must be set! * Without this bits set, PSC don;t switch states !! */ - writel(CONFIG_SYS_DA850_DDR2_SDRCR | + writel(CFG_SYS_DA850_DDR2_SDRCR | (1 << DV_DDR_SRCR_LPMODEN_SHIFT) | (1 << DV_DDR_SRCR_MCLKSTOPEN_SHIFT), &dv_ddr2_regs_ctrl->sdrcr); @@ -246,7 +246,7 @@ static int da850_ddr_setup(void) /* disable self refresh */ clrbits_le32(&dv_ddr2_regs_ctrl->sdrcr, DV_DDR_SDRCR_LPMODEN | DV_DDR_SDRCR_MCLKSTOPEN); - writel(CONFIG_SYS_DA850_DDR2_PBBPR, &dv_ddr2_regs_ctrl->pbbpr); + writel(CFG_SYS_DA850_DDR2_PBBPR, &dv_ddr2_regs_ctrl->pbbpr); return 0; } @@ -265,7 +265,7 @@ int arch_cpu_init(void) writel(DV_SYSCFG_KICK1_UNLOCK, &davinci_syscfg_regs->kick1); dv_maskbits(&davinci_syscfg_regs->suspsrc, - CONFIG_SYS_DA850_SYSCFG_SUSPSRC); + CFG_SYS_DA850_SYSCFG_SUSPSRC); /* configure pinmux settings */ if (davinci_configure_pin_mux_items(pinmuxes, pinmuxes_size)) @@ -273,8 +273,8 @@ int arch_cpu_init(void) #if defined(CONFIG_SYS_DA850_PLL_INIT) /* PLL setup */ - da850_pll_init(davinci_pllc0_regs, CONFIG_SYS_DA850_PLL0_PLLM); - da850_pll_init(davinci_pllc1_regs, CONFIG_SYS_DA850_PLL1_PLLM); + da850_pll_init(davinci_pllc0_regs, CFG_SYS_DA850_PLL0_PLLM); + da850_pll_init(davinci_pllc1_regs, CFG_SYS_DA850_PLL1_PLLM); #endif /* setup CSn config */ #if defined(CONFIG_SYS_DA850_CS2CFG) @@ -290,8 +290,8 @@ int arch_cpu_init(void) board_gpio_init(); #if !CONFIG_IS_ENABLED(DM_SERIAL) - ns16550_init((struct ns16550 *)(CONFIG_SYS_NS16550_COM1), - CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE); + ns16550_init((struct ns16550 *)(CFG_SYS_NS16550_COM1), + CFG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE); #endif /* * Fix Power and Emulation Management Register @@ -299,7 +299,7 @@ int arch_cpu_init(void) */ writel((DAVINCI_UART_PWREMU_MGMT_FREE | DAVINCI_UART_PWREMU_MGMT_URRST | DAVINCI_UART_PWREMU_MGMT_UTRST), -#if (CONFIG_SYS_NS16550_COM1 == DAVINCI_UART0_BASE) +#if (CFG_SYS_NS16550_COM1 == DAVINCI_UART0_BASE) &davinci_uart0_ctrl_regs->pwremu_mgmt); #else &davinci_uart2_ctrl_regs->pwremu_mgmt); diff --git a/arch/arm/mach-davinci/misc.c b/arch/arm/mach-davinci/misc.c index 73fdd1f243..cfad28c43d 100644 --- a/arch/arm/mach-davinci/misc.c +++ b/arch/arm/mach-davinci/misc.c @@ -26,14 +26,14 @@ int dram_init(void) { /* dram_init must store complete ramsize in gd->ram_size */ gd->ram_size = get_ram_size( - (void *)CONFIG_SYS_SDRAM_BASE, - CONFIG_MAX_RAM_BANK_SIZE); + (void *)CFG_SYS_SDRAM_BASE, + CFG_MAX_RAM_BANK_SIZE); return 0; } int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; gd->bd->bi_dram[0].size = gd->ram_size; return 0; diff --git a/arch/arm/mach-davinci/spl.c b/arch/arm/mach-davinci/spl.c index 54aff78894..5f5b9ebbf9 100644 --- a/arch/arm/mach-davinci/spl.c +++ b/arch/arm/mach-davinci/spl.c @@ -27,9 +27,9 @@ void puts(const char *str) void putc(char c) { if (c == '\n') - ns16550_putc((struct ns16550 *)(CONFIG_SYS_NS16550_COM1), '\r'); + ns16550_putc((struct ns16550 *)(CFG_SYS_NS16550_COM1), '\r'); - ns16550_putc((struct ns16550 *)(CONFIG_SYS_NS16550_COM1), c); + ns16550_putc((struct ns16550 *)(CFG_SYS_NS16550_COM1), c); } #endif /* CONFIG_SPL_LIBCOMMON_SUPPORT */ diff --git a/arch/arm/mach-davinci/timer.c b/arch/arm/mach-davinci/timer.c index 43e0574901..83c190b620 100644 --- a/arch/arm/mach-davinci/timer.c +++ b/arch/arm/mach-davinci/timer.c @@ -32,7 +32,7 @@ DECLARE_GLOBAL_DATA_PTR; static struct davinci_timer * const timer = - (struct davinci_timer *)CONFIG_SYS_TIMERBASE; + (struct davinci_timer *)CFG_SYS_TIMERBASE; #define TIMER_LOAD_VAL 0xffffffff @@ -47,7 +47,7 @@ int timer_init(void) writel(0x0, &timer->tim34); writel(TIMER_LOAD_VAL, &timer->prd34); writel(2 << 22, &timer->tcr); - gd->arch.timer_rate_hz = CONFIG_SYS_HZ_CLOCK / TIM_CLK_DIV; + gd->arch.timer_rate_hz = CFG_SYS_HZ_CLOCK / TIM_CLK_DIV; gd->arch.timer_reset_value = 0; return(0); diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig index 8410290856..8f3aee052c 100644 --- a/arch/arm/mach-exynos/Kconfig +++ b/arch/arm/mach-exynos/Kconfig @@ -4,6 +4,12 @@ config BOARD_COMMON def_bool y depends on !TARGET_SMDKV310 && !TARGET_ARNDALE +config SPI_BOOTING + bool + +config USB_BOOTING + bool + choice prompt "EXYNOS architecture type select" optional @@ -24,6 +30,8 @@ config ARCH_EXYNOS5 select BOARD_EARLY_INIT_F select CPU_V7A select SHA_HW_ACCEL + select SPI_BOOTING if EXYNOS5_DT + select USB_BOOTING imply CMD_HASH imply CRC32_VERIFY imply HASH_VERIFY @@ -67,10 +75,12 @@ config TARGET_SMDKV310 select SUPPORT_SPL config TARGET_TRATS + select MISC_COMMON bool "Exynos4210 Trats board" config TARGET_S5PC210_UNIVERSAL bool "EXYNOS4210 Universal C210 board" + select MISC_COMMON config TARGET_ORIGEN bool "Exynos4412 Origen board" @@ -79,9 +89,11 @@ config TARGET_ORIGEN config TARGET_TRATS2 bool "Exynos4412 Trat2 board" + select MISC_COMMON config TARGET_ODROID bool "Exynos4412 Odroid board" + select MISC_COMMON endchoice endif @@ -113,6 +125,7 @@ config TARGET_ODROID_XU3 bool "Exynos5422 Odroid board" select EXYNOS5_DT select EXYNOS5420 + select MISC_COMMON select OF_CONTROL config TARGET_ARNDALE diff --git a/arch/arm/mach-exynos/dmc_init_ddr3.c b/arch/arm/mach-exynos/dmc_init_ddr3.c index fa867f27f3..cad8ccc531 100644 --- a/arch/arm/mach-exynos/dmc_init_ddr3.c +++ b/arch/arm/mach-exynos/dmc_init_ddr3.c @@ -236,7 +236,7 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int reset) * better have similar timings, since there's only a single adjustment that is * shared by both chips). */ -const unsigned int test_addr = CONFIG_SYS_SDRAM_BASE; +const unsigned int test_addr = CFG_SYS_SDRAM_BASE; /* Test pattern with which RAM will be tested */ static const unsigned int test_pattern[] = { diff --git a/arch/arm/mach-exynos/include/mach/pwm.h b/arch/arm/mach-exynos/include/mach/pwm.h index 417fc15551..17372492d5 100644 --- a/arch/arm/mach-exynos/include/mach/pwm.h +++ b/arch/arm/mach-exynos/include/mach/pwm.h @@ -49,6 +49,11 @@ struct s5p_timer { unsigned int tcnto4; unsigned int tintcstat; }; + +int s5p_pwm_init (int pwm_id, int div, int invert); +int s5p_pwm_config (int pwm_id, int duty_ns, int period_ns); +int s5p_pwm_enable (int pwm_id); +void s5p_pwm_disable (int pwm_id); #endif /* __ASSEMBLY__ */ #endif diff --git a/arch/arm/mach-exynos/lowlevel_init.c b/arch/arm/mach-exynos/lowlevel_init.c index 1ff5fcac1b..c57b8aee79 100644 --- a/arch/arm/mach-exynos/lowlevel_init.c +++ b/arch/arm/mach-exynos/lowlevel_init.c @@ -51,7 +51,7 @@ enum { #ifdef CONFIG_EXYNOS5420 /* Address for relocating helper code (Last 4 KB of IRAM) */ -#define EXYNOS_RELOCATE_CODE_BASE (CONFIG_IRAM_TOP - 0x1000) +#define EXYNOS_RELOCATE_CODE_BASE (CFG_IRAM_TOP - 0x1000) /* * Power up secondary CPUs. @@ -73,14 +73,14 @@ static void low_power_start(void) reg_val = readl(EXYNOS5420_SPARE_BASE); if (reg_val != CPU_RST_FLAG_VAL) { - writel(0x0, CONFIG_LOWPOWER_FLAG); + writel(0x0, CFG_LOWPOWER_FLAG); branch_bx(0x0); } - reg_val = readl(CONFIG_PHY_IRAM_BASE + 0x4); + reg_val = readl(CFG_PHY_IRAM_BASE + 0x4); if (reg_val != (uint32_t)&low_power_start) { /* Store jump address as low_power_start if not present */ - writel((uint32_t)&low_power_start, CONFIG_PHY_IRAM_BASE + 0x4); + writel((uint32_t)&low_power_start, CFG_PHY_IRAM_BASE + 0x4); dsb(); sev(); } @@ -160,11 +160,11 @@ static void secondary_cores_configure(void) writel(0x0, (EXYNOS_RELOCATE_CODE_BASE + 0x1C)); /* set lowpower flag and address */ - writel(CPU_RST_FLAG_VAL, CONFIG_LOWPOWER_FLAG); - writel((uint32_t)&low_power_start, CONFIG_LOWPOWER_ADDR); + writel(CPU_RST_FLAG_VAL, CFG_LOWPOWER_FLAG); + writel((uint32_t)&low_power_start, CFG_LOWPOWER_ADDR); writel(CPU_RST_FLAG_VAL, EXYNOS5420_SPARE_BASE); /* Store jump address for power down */ - writel((uint32_t)&power_down_core, CONFIG_PHY_IRAM_BASE + 0x4); + writel((uint32_t)&power_down_core, CFG_PHY_IRAM_BASE + 0x4); /* Need all core power down check */ dsb(); diff --git a/arch/arm/mach-exynos/sec_boot.S b/arch/arm/mach-exynos/sec_boot.S index 40c07209e4..1303544d83 100644 --- a/arch/arm/mach-exynos/sec_boot.S +++ b/arch/arm/mach-exynos/sec_boot.S @@ -21,7 +21,7 @@ relocate_wait_code: .ltorg /* * Secondary core waits here until Primary wake it up. - * Below code is copied to (CONFIG_IRAM_TOP - 0x1000) + * Below code is copied to (CFG_IRAM_TOP - 0x1000) * This is a workaround code which is supposed to act as a * substitute/supplement to the iROM code. * diff --git a/arch/arm/mach-exynos/spl_boot.c b/arch/arm/mach-exynos/spl_boot.c index f518539057..553dac75b6 100644 --- a/arch/arm/mach-exynos/spl_boot.c +++ b/arch/arm/mach-exynos/spl_boot.c @@ -141,7 +141,7 @@ static void exynos_spi_copy(unsigned int uboot_size, unsigned int uboot_addr) { int upto, todo; int i, timeout = 100; - struct exynos_spi *regs = (struct exynos_spi *)CONFIG_SYS_SPI_BASE; + struct exynos_spi *regs = (struct exynos_spi *)CFG_SYS_SPI_BASE; set_spi_clk(PERIPH_ID_SPI1, 50000000); /* set spi clock to 50Mhz */ /* set the spi1 GPIO */ diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index b72b6af434..3266545c26 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -18,6 +18,9 @@ config SYSCOUNTER_TIMER config GPT_TIMER bool +config MXC_GPT_HCLK + bool + config IMX_RDC bool "i.MX Resource domain controller driver" depends on ARCH_MX6 || ARCH_MX7 @@ -195,3 +198,9 @@ config IMX_CONTAINER_CFG help This is to specific the cfg file for generating container image which will be loaded by SPL. + +config IOMUX_LPSR + bool + +config IOMUX_SHARE_CONF_REG + bool diff --git a/arch/arm/mach-imx/image-container.c b/arch/arm/mach-imx/image-container.c index 0e76786482..06ee608c4a 100644 --- a/arch/arm/mach-imx/image-container.c +++ b/arch/arm/mach-imx/image-container.c @@ -248,13 +248,13 @@ unsigned long spl_nor_get_uboot_base(void) int end; /* Calculate the image set end, - * if it is less than CONFIG_SYS_UBOOT_BASE(0x8281000), - * we use CONFIG_SYS_UBOOT_BASE + * if it is less than CFG_SYS_UBOOT_BASE(0x8281000), + * we use CFG_SYS_UBOOT_BASE * Otherwise, use the calculated address */ end = get_imageset_end((void *)NULL, QSPI_NOR_DEV); - if (end <= CONFIG_SYS_UBOOT_BASE) - end = CONFIG_SYS_UBOOT_BASE; + if (end <= CFG_SYS_UBOOT_BASE) + end = CFG_SYS_UBOOT_BASE; else end = ROUND(end, SZ_1K); diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c index a4863281e3..8050406613 100644 --- a/arch/arm/mach-imx/imx8m/soc.c +++ b/arch/arm/mach-imx/imx8m/soc.c @@ -178,7 +178,7 @@ static unsigned int imx8m_find_dram_entry_in_mem_map(void) int i; for (i = 0; i < ARRAY_SIZE(imx8m_mem_map); i++) - if (imx8m_mem_map[i].phys == CONFIG_SYS_SDRAM_BASE) + if (imx8m_mem_map[i].phys == CFG_SYS_SDRAM_BASE) return i; hang(); /* Entry not found, this must never happen. */ diff --git a/arch/arm/mach-imx/imx8ulp/soc.c b/arch/arm/mach-imx/imx8ulp/soc.c index 802cb0e2ba..5d95fb89a6 100644 --- a/arch/arm/mach-imx/imx8ulp/soc.c +++ b/arch/arm/mach-imx/imx8ulp/soc.c @@ -373,7 +373,7 @@ static unsigned int imx8ulp_find_dram_entry_in_mem_map(void) int i; for (i = 0; i < ARRAY_SIZE(imx8ulp_arm64_mem_map); i++) - if (imx8ulp_arm64_mem_map[i].phys == CONFIG_SYS_SDRAM_BASE) + if (imx8ulp_arm64_mem_map[i].phys == CFG_SYS_SDRAM_BASE) return i; hang(); /* Entry not found, this must never happen. */ diff --git a/arch/arm/mach-imx/mx5/Kconfig b/arch/arm/mach-imx/mx5/Kconfig index 494e2136dc..d282663dcf 100644 --- a/arch/arm/mach-imx/mx5/Kconfig +++ b/arch/arm/mach-imx/mx5/Kconfig @@ -22,7 +22,6 @@ config TARGET_KP_IMX53 bool "Support K+P imx53 board" select BOARD_LATE_INIT select DM - select DM_ETH select DM_GPIO select DM_I2C select DM_PMIC diff --git a/arch/arm/mach-imx/mx5/lowlevel_init.S b/arch/arm/mach-imx/mx5/lowlevel_init.S index b42cc3e9e4..6ec38dcfa4 100644 --- a/arch/arm/mach-imx/mx5/lowlevel_init.S +++ b/arch/arm/mach-imx/mx5/lowlevel_init.S @@ -205,7 +205,7 @@ setup_pll_func: /* Switch peripheral to PLL 3 */ ldr r0, =CCM_BASE_ADDR - ldr r1, =0x000010C0 | CONFIG_SYS_DDR_CLKSEL + ldr r1, =0x000010C0 | CFG_SYS_DDR_CLKSEL str r1, [r0, #CLKCTL_CBCMR] ldr r1, =0x13239145 str r1, [r0, #CLKCTL_CBCDR] @@ -215,7 +215,7 @@ setup_pll_func: ldr r0, =CCM_BASE_ADDR ldr r1, =0x19239145 str r1, [r0, #CLKCTL_CBCDR] - ldr r1, =0x000020C0 | CONFIG_SYS_DDR_CLKSEL + ldr r1, =0x000020C0 | CFG_SYS_DDR_CLKSEL str r1, [r0, #CLKCTL_CBCMR] setup_pll PLL3_BASE_ADDR, 216 @@ -240,10 +240,10 @@ setup_pll_func: /* setup the rest */ /* Use lp_apm (24MHz) source for perclk */ - ldr r1, =0x000020C2 | CONFIG_SYS_DDR_CLKSEL + ldr r1, =0x000020C2 | CFG_SYS_DDR_CLKSEL str r1, [r0, #CLKCTL_CBCMR] /* ddr clock from PLL 1, all perclk dividers are 1 since using 24MHz */ - ldr r1, =CONFIG_SYS_CLKTL_CBCDR + ldr r1, =CFG_SYS_CLKTL_CBCDR str r1, [r0, #CLKCTL_CBCDR] /* Restore the default values in the Gate registers */ @@ -378,7 +378,7 @@ ENTRY(lowlevel_init) mov r10, lr mov r4, #0 /* Fix R4 to 0 */ -#if defined(CONFIG_SYS_MAIN_PWR_ON) +#if defined(CFG_SYS_MAIN_PWR_ON) ldr r0, =GPIO1_BASE_ADDR ldr r1, [r0, #0x0] orr r1, r1, #1 << 23 diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig index 752c57f52d..7529b311f8 100644 --- a/arch/arm/mach-imx/mx6/Kconfig +++ b/arch/arm/mach-imx/mx6/Kconfig @@ -168,12 +168,12 @@ config TARGET_COLIBRI_IMX6ULL select BOARD_LATE_INIT select DM select DM_THERMAL + select IOMUX_LPSR config TARGET_DART_6UL bool "Variscite imx6ULL dart(DART-SOM-6ULL)" depends on MX6ULL select DM - select DM_ETH select DM_GPIO select DM_I2C select DM_MMC @@ -196,7 +196,6 @@ config TARGET_DISPLAY5 bool "LWN DISPLAY5 board" depends on MX6Q select DM - select DM_ETH select DM_I2C select DM_MMC select DM_SPI @@ -244,7 +243,6 @@ config TARGET_KONTRON_MX6UL config TARGET_KOSAGI_NOVENA bool "Kosagi Novena" select BOARD_LATE_INIT - select DM_ETH select DM_GPIO select DM_MMC select PCI @@ -260,7 +258,6 @@ config TARGET_MCCMON6 select SUPPORT_SPL select DM select DM_GPIO - select DM_ETH select DM_SERIAL select DM_I2C select DM_SPI @@ -279,7 +276,6 @@ config TARGET_MX6LOGICPD select BOARD_EARLY_INIT_F select BOARD_LATE_INIT select DM - select DM_ETH select DM_GPIO select DM_I2C select DM_MMC @@ -300,7 +296,6 @@ config TARGET_MX6DL_MAMOJ bool "Support BTicino Mamoj" depends on MX6QDL select DM - select DM_ETH select DM_GPIO select DM_I2C select DM_MMC @@ -333,7 +328,6 @@ config TARGET_MX6Q_ENGICAM depends on MX6QDL select BOARD_LATE_INIT select DM - select DM_ETH select DM_GPIO select DM_I2C select DM_MMC @@ -354,7 +348,6 @@ config TARGET_MX6Q_ACC select OF_CONTROL select SPL_OF_LIBFDT select DM - select DM_ETH select DM_GPIO select DM_I2C select DM_MMC @@ -396,6 +389,7 @@ config TARGET_MX6SLLEVK select BOARD_LATE_INIT select DM select DM_THERMAL + select IOMUX_LPSR imply CMD_DM config TARGET_MX6SXSABRESD @@ -445,7 +439,6 @@ config TARGET_MX6UL_ENGICAM depends on MX6UL select BOARD_LATE_INIT select DM - select DM_ETH select DM_GPIO select DM_I2C select DM_MMC @@ -464,6 +457,7 @@ config TARGET_MX6ULL_14X14_EVK select BOARD_LATE_INIT select DM select DM_THERMAL + select IOMUX_LPSR imply CMD_DM config TARGET_MX6ULZ_SMM_M2 @@ -481,7 +475,6 @@ config TARGET_MYS_6ULX bool "MYiR MYS-6ULX" depends on MX6ULL select DM - select DM_ETH select DM_GPIO select DM_I2C select DM_MMC @@ -501,7 +494,6 @@ config TARGET_NPI_IMX6ULL bool "Seeed NPI-IMX6ULL" depends on MX6ULL select DM - select DM_ETH select DM_MMC select DM_GPIO select DM_SERIAL @@ -549,7 +541,6 @@ config TARGET_PCL063 bool "PHYTEC PCL063 (phyCORE-i.MX6UL)" depends on MX6UL select DM - select DM_ETH select DM_GPIO select DM_I2C select DM_MMC @@ -561,7 +552,6 @@ config TARGET_PCL063_ULL bool "PHYTEC PCL063 (phyCORE-i.MX6ULL)" depends on MX6ULL select DM - select DM_ETH select DM_GPIO select DM_I2C select DM_MMC @@ -574,7 +564,6 @@ config TARGET_SOMLABS_VISIONSOM_6ULL depends on MX6ULL select BOARD_LATE_INIT select DM - select DM_ETH select DM_GPIO select DM_MMC select DM_SERIAL @@ -594,7 +583,6 @@ config TARGET_KP_IMX6Q_TPC select SPL_DM if SPL select DM_THERMAL select DM_MMC - select DM_ETH select DM_REGULATOR select SPL_DM_REGULATOR if SPL select DM_SERIAL @@ -658,7 +646,6 @@ config TARGET_BRPPT2 select OF_CONTROL select SPL_OF_LIBFDT select DM - select DM_ETH select DM_GPIO select DM_I2C select DM_MMC diff --git a/arch/arm/mach-imx/mx6/litesom.c b/arch/arm/mach-imx/mx6/litesom.c index 699a3dc317..2ba3245e22 100644 --- a/arch/arm/mach-imx/mx6/litesom.c +++ b/arch/arm/mach-imx/mx6/litesom.c @@ -172,7 +172,7 @@ static void spl_dram_init(void) * Get actual RAM size, so we can adjust DDR row size for <512M * memories */ - ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, SZ_512M); + ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, SZ_512M); if (ram_size < SZ_512M) { mem_ddr.rowaddr = 14; mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr); diff --git a/arch/arm/mach-imx/mx6/opos6ul.c b/arch/arm/mach-imx/mx6/opos6ul.c index e9d78740a1..38ead8ace2 100644 --- a/arch/arm/mach-imx/mx6/opos6ul.c +++ b/arch/arm/mach-imx/mx6/opos6ul.c @@ -44,7 +44,7 @@ static int setup_fec(void) int board_init(void) { /* Address of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; #ifdef CONFIG_FEC_MXC setup_fec(); diff --git a/arch/arm/mach-imx/mx7/Kconfig b/arch/arm/mach-imx/mx7/Kconfig index 3c388183bc..0bb18f6520 100644 --- a/arch/arm/mach-imx/mx7/Kconfig +++ b/arch/arm/mach-imx/mx7/Kconfig @@ -6,6 +6,7 @@ config MX7 select ARCH_SUPPORT_PSCI select CPU_V7_HAS_NONSEC select CPU_V7_HAS_VIRT + select IOMUX_LPSR select ROM_UNIFIED_SECTIONS select SYSCOUNTER_TIMER imply CMD_FUSE diff --git a/arch/arm/mach-imx/spl.c b/arch/arm/mach-imx/spl.c index 6b8f4115c4..cb9801b7a1 100644 --- a/arch/arm/mach-imx/spl.c +++ b/arch/arm/mach-imx/spl.c @@ -349,7 +349,7 @@ void *board_spl_fit_buffer_addr(ulong fit_size, int sectors, int bl_len) #if defined(CONFIG_MX6) && defined(CONFIG_SPL_OS_BOOT) int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; gd->bd->bi_dram[0].size = imx_ddr_size(); return 0; diff --git a/arch/arm/mach-imx/syscounter.c b/arch/arm/mach-imx/syscounter.c index df478a2326..129efac6fa 100644 --- a/arch/arm/mach-imx/syscounter.c +++ b/arch/arm/mach-imx/syscounter.c @@ -65,7 +65,7 @@ int timer_init(void) struct sctr_regs *sctr = (struct sctr_regs *)SCTR_BASE_ADDR; unsigned long val, freq; - freq = CONFIG_SC_TIMER_CLK; + freq = CFG_SC_TIMER_CLK; asm volatile("mcr p15, 0, %0, c14, c0, 0" : : "r" (freq)); writel(freq, &sctr->cntfid0); diff --git a/arch/arm/mach-k3/Kconfig b/arch/arm/mach-k3/Kconfig index 171a7f2f25..87da6b49ee 100644 --- a/arch/arm/mach-k3/Kconfig +++ b/arch/arm/mach-k3/Kconfig @@ -19,6 +19,9 @@ config SOC_K3_AM642 config SOC_K3_AM625 bool "TI's K3 based AM625 SoC Family Support" +config SOC_K3_AM62A7 + bool "TI's K3 based AM62A7 SoC Family Support" + endchoice config SYS_SOC @@ -29,7 +32,7 @@ config SYS_K3_NON_SECURE_MSRAM_SIZE default 0x80000 if SOC_K3_AM654 default 0x100000 if SOC_K3_J721E || SOC_K3_J721S2 default 0x1c0000 if SOC_K3_AM642 - default 0x3c000 if SOC_K3_AM625 + default 0x3c000 if SOC_K3_AM625 || SOC_K3_AM62A7 help Describes the total size of the MCU or OCMC MSRAM present on the SoC in use. This doesn't specify the total size of SPL as @@ -41,7 +44,7 @@ config SYS_K3_MAX_DOWNLODABLE_IMAGE_SIZE default 0x58000 if SOC_K3_AM654 default 0xc0000 if SOC_K3_J721E || SOC_K3_J721S2 default 0x180000 if SOC_K3_AM642 - default 0x38000 if SOC_K3_AM625 + default 0x38000 if SOC_K3_AM625 || SOC_K3_AM62A7 help Describes the maximum size of the image that ROM can download from any boot media. @@ -66,7 +69,7 @@ config SYS_K3_BOOT_PARAM_TABLE_INDEX default 0x41cffbfc if SOC_K3_J721E default 0x41cfdbfc if SOC_K3_J721S2 default 0x701bebfc if SOC_K3_AM642 - default 0x43c3f290 if SOC_K3_AM625 + default 0x43c3f290 if SOC_K3_AM625 || SOC_K3_AM62A7 help Address at which ROM stores the value which determines if SPL is booted up by primary boot media or secondary boot media. @@ -135,7 +138,7 @@ config K3_SYSFW_IMAGE_MMCSD_RAW_MODE_PART config K3_SYSFW_IMAGE_SIZE_MAX int "Amount of memory dynamically allocated for loading SYSFW blob" depends on K3_LOAD_SYSFW - default 163840 if SOC_K3_AM625 + default 163840 if SOC_K3_AM625 || SOC_K3_AM62A7 default 278000 help Amount of memory (in bytes) reserved through dynamic allocation at @@ -167,7 +170,7 @@ config K3_ATF_LOAD_ADDR config K3_DM_FW bool "Separate DM firmware image" - depends on SPL && CPU_V7R && (SOC_K3_J721E || SOC_K3_J721S2 || SOC_K3_AM625) && !CLK_TI_SCI && !TI_SCI_POWER_DOMAIN + depends on SPL && CPU_V7R && (SOC_K3_J721E || SOC_K3_J721S2 || SOC_K3_AM625 || SOC_K3_AM62A7) && !CLK_TI_SCI && !TI_SCI_POWER_DOMAIN default y help Enabling this will indicate that the system has separate DM @@ -185,6 +188,7 @@ config K3_X509_SWRV source "board/ti/am65x/Kconfig" source "board/ti/am64x/Kconfig" source "board/ti/am62x/Kconfig" +source "board/ti/am62ax/Kconfig" source "board/ti/j721e/Kconfig" source "board/siemens/iot2050/Kconfig" source "board/ti/j721s2/Kconfig" diff --git a/arch/arm/mach-k3/Makefile b/arch/arm/mach-k3/Makefile index 6ac2b61c3d..b5bc236781 100644 --- a/arch/arm/mach-k3/Makefile +++ b/arch/arm/mach-k3/Makefile @@ -6,6 +6,7 @@ obj-$(CONFIG_SOC_K3_J721E) += j721e/ j7200/ obj-$(CONFIG_SOC_K3_J721S2) += j721s2/ obj-$(CONFIG_SOC_K3_AM625) += am62x/ +obj-$(CONFIG_SOC_K3_AM62A7) += am62ax/ obj-$(CONFIG_ARM64) += arm64-mmu.o obj-$(CONFIG_CPU_V7R) += r5_mpu.o lowlevel_init.o obj-$(CONFIG_ARM64) += cache.o @@ -15,6 +16,7 @@ obj-$(CONFIG_SOC_K3_J721E) += j721e_init.o obj-$(CONFIG_SOC_K3_J721S2) += j721s2_init.o obj-$(CONFIG_SOC_K3_AM642) += am642_init.o obj-$(CONFIG_SOC_K3_AM625) += am625_init.o +obj-$(CONFIG_SOC_K3_AM62A7) += am62a7_init.o obj-$(CONFIG_K3_LOAD_SYSFW) += sysfw-loader.o endif obj-y += common.o security.o diff --git a/arch/arm/mach-k3/am62a7_init.c b/arch/arm/mach-k3/am62a7_init.c new file mode 100644 index 0000000000..e9569f0d26 --- /dev/null +++ b/arch/arm/mach-k3/am62a7_init.c @@ -0,0 +1,250 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * AM62A7: SoC specific initialization + * + * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#include <spl.h> +#include <asm/io.h> +#include <asm/arch/hardware.h> +#include <asm/arch/sysfw-loader.h> +#include "common.h" +#include <dm.h> +#include <dm/uclass-internal.h> +#include <dm/pinctrl.h> + +/* + * This uninitialized global variable would normal end up in the .bss section, + * but the .bss is cleared between writing and reading this variable, so move + * it to the .data section. + */ +u32 bootindex __section(".data"); +static struct rom_extended_boot_data bootdata __section(".data"); + +static void store_boot_info_from_rom(void) +{ + bootindex = *(u32 *)(CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX); + memcpy(&bootdata, (uintptr_t *)ROM_ENTENDED_BOOT_DATA_INFO, + sizeof(struct rom_extended_boot_data)); +} + +static void ctrl_mmr_unlock(void) +{ + /* Unlock all WKUP_CTRL_MMR0 module registers */ + mmr_unlock(WKUP_CTRL_MMR0_BASE, 0); + mmr_unlock(WKUP_CTRL_MMR0_BASE, 1); + mmr_unlock(WKUP_CTRL_MMR0_BASE, 2); + mmr_unlock(WKUP_CTRL_MMR0_BASE, 3); + mmr_unlock(WKUP_CTRL_MMR0_BASE, 4); + mmr_unlock(WKUP_CTRL_MMR0_BASE, 5); + mmr_unlock(WKUP_CTRL_MMR0_BASE, 6); + mmr_unlock(WKUP_CTRL_MMR0_BASE, 7); + + /* Unlock all CTRL_MMR0 module registers */ + mmr_unlock(CTRL_MMR0_BASE, 0); + mmr_unlock(CTRL_MMR0_BASE, 1); + mmr_unlock(CTRL_MMR0_BASE, 2); + mmr_unlock(CTRL_MMR0_BASE, 4); + mmr_unlock(CTRL_MMR0_BASE, 5); + mmr_unlock(CTRL_MMR0_BASE, 6); + + /* Unlock all MCU_CTRL_MMR0 module registers */ + mmr_unlock(MCU_CTRL_MMR0_BASE, 0); + mmr_unlock(MCU_CTRL_MMR0_BASE, 1); + mmr_unlock(MCU_CTRL_MMR0_BASE, 2); + mmr_unlock(MCU_CTRL_MMR0_BASE, 3); + mmr_unlock(MCU_CTRL_MMR0_BASE, 4); + mmr_unlock(MCU_CTRL_MMR0_BASE, 6); + + /* Unlock PADCFG_CTRL_MMR padconf registers */ + mmr_unlock(PADCFG_MMR0_BASE, 1); + mmr_unlock(PADCFG_MMR1_BASE, 1); +} + +void board_init_f(ulong dummy) +{ + struct udevice *dev; + int ret; + +#if defined(CONFIG_CPU_V7R) + setup_k3_mpu_regions(); +#endif + + /* + * Cannot delay this further as there is a chance that + * K3_BOOT_PARAM_TABLE_INDEX can be over written by SPL MALLOC section. + */ + store_boot_info_from_rom(); + + ctrl_mmr_unlock(); + + /* Init DM early */ + spl_early_init(); + + /* + * Process pinctrl for the serial0 and serial3, aka WKUP_UART0 and + * MAIN_UART1 modules and continue regardless of the result of pinctrl. + * Do this without probing the device, but instead by searching the + * device that would request the given sequence number if probed. The + * UARTs will be used by the DM firmware and TIFS firmware images + * respectively and the firmware depend on SPL to initialize the pin + * settings. + */ + ret = uclass_find_device_by_seq(UCLASS_SERIAL, 0, &dev); + if (!ret) + pinctrl_select_state(dev, "default"); + + ret = uclass_find_device_by_seq(UCLASS_SERIAL, 3, &dev); + if (!ret) + pinctrl_select_state(dev, "default"); + +#ifdef CONFIG_K3_EARLY_CONS + /* + * Allow establishing an early console as required for example when + * doing a UART-based boot. Note that this console may not "survive" + * through a SYSFW PM-init step and will need a re-init in some way + * due to changing module clock frequencies. + */ + early_console_init(); +#endif + +#if defined(CONFIG_K3_LOAD_SYSFW) + /* + * Configure and start up system controller firmware. Provide + * the U-Boot console init function to the SYSFW post-PM configuration + * callback hook, effectively switching on (or over) the console + * output. + */ + ret = is_rom_loaded_sysfw(&bootdata); + if (!ret) + panic("ROM has not loaded TIFS firmware\n"); + + k3_sysfw_loader(true, NULL, NULL); +#endif + + /* + * Force probe of clk_k3 driver here to ensure basic default clock + * configuration is always done. + */ + if (IS_ENABLED(CONFIG_SPL_CLK_K3)) { + ret = uclass_get_device_by_driver(UCLASS_CLK, + DM_DRIVER_GET(ti_clk), + &dev); + if (ret) + printf("Failed to initialize clk-k3!\n"); + } + + preloader_console_init(); + + /* Output System Firmware version info */ + k3_sysfw_print_ver(); + +#if defined(CONFIG_K3_AM62A_DDRSS) + ret = uclass_get_device(UCLASS_RAM, 0, &dev); + if (ret) + panic("DRAM init failed: %d\n", ret); +#endif + + printf("am62a_init: %s done\n", __func__); +} + +static u32 __get_backup_bootmedia(u32 devstat) +{ + u32 bkup_bootmode = (devstat & MAIN_DEVSTAT_BACKUP_BOOTMODE_MASK) >> + MAIN_DEVSTAT_BACKUP_BOOTMODE_SHIFT; + u32 bkup_bootmode_cfg = + (devstat & MAIN_DEVSTAT_BACKUP_BOOTMODE_CFG_MASK) >> + MAIN_DEVSTAT_BACKUP_BOOTMODE_CFG_SHIFT; + + switch (bkup_bootmode) { + case BACKUP_BOOT_DEVICE_UART: + return BOOT_DEVICE_UART; + + case BACKUP_BOOT_DEVICE_USB: + return BOOT_DEVICE_USB; + + case BACKUP_BOOT_DEVICE_ETHERNET: + return BOOT_DEVICE_ETHERNET; + + case BACKUP_BOOT_DEVICE_MMC: + if (bkup_bootmode_cfg) + return BOOT_DEVICE_MMC2; + return BOOT_DEVICE_MMC1; + + case BACKUP_BOOT_DEVICE_SPI: + return BOOT_DEVICE_SPI; + + case BACKUP_BOOT_DEVICE_I2C: + return BOOT_DEVICE_I2C; + + case BACKUP_BOOT_DEVICE_DFU: + if (bkup_bootmode_cfg & MAIN_DEVSTAT_BACKUP_USB_MODE_MASK) + return BOOT_DEVICE_USB; + return BOOT_DEVICE_DFU; + }; + + return BOOT_DEVICE_RAM; +} + +static u32 __get_primary_bootmedia(u32 devstat) +{ + u32 bootmode = (devstat & MAIN_DEVSTAT_PRIMARY_BOOTMODE_MASK) >> + MAIN_DEVSTAT_PRIMARY_BOOTMODE_SHIFT; + u32 bootmode_cfg = (devstat & MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_MASK) >> + MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_SHIFT; + + switch (bootmode) { + case BOOT_DEVICE_OSPI: + fallthrough; + case BOOT_DEVICE_QSPI: + fallthrough; + case BOOT_DEVICE_XSPI: + fallthrough; + case BOOT_DEVICE_SPI: + return BOOT_DEVICE_SPI; + + case BOOT_DEVICE_ETHERNET_RGMII: + fallthrough; + case BOOT_DEVICE_ETHERNET_RMII: + return BOOT_DEVICE_ETHERNET; + + case BOOT_DEVICE_EMMC: + return BOOT_DEVICE_MMC1; + + case BOOT_DEVICE_SPI_NAND: + return BOOT_DEVICE_SPINAND; + + case BOOT_DEVICE_MMC: + if ((bootmode_cfg & MAIN_DEVSTAT_PRIMARY_MMC_PORT_MASK) >> + MAIN_DEVSTAT_PRIMARY_MMC_PORT_SHIFT) + return BOOT_DEVICE_MMC2; + return BOOT_DEVICE_MMC1; + + case BOOT_DEVICE_DFU: + if ((bootmode_cfg & MAIN_DEVSTAT_PRIMARY_USB_MODE_MASK) >> + MAIN_DEVSTAT_PRIMARY_USB_MODE_SHIFT) + return BOOT_DEVICE_USB; + return BOOT_DEVICE_DFU; + + case BOOT_DEVICE_NOBOOT: + return BOOT_DEVICE_RAM; + } + + return bootmode; +} + +u32 spl_boot_device(void) +{ + u32 devstat = readl(CTRLMMR_MAIN_DEVSTAT); + u32 bootmedia; + + if (bootindex == K3_PRIMARY_BOOTMODE) + bootmedia = __get_primary_bootmedia(devstat); + else + bootmedia = __get_backup_bootmedia(devstat); + + printf("am62a_init: %s: devstat = 0x%x bootmedia = 0x%x bootindex = %d\n", + __func__, devstat, bootmedia, bootindex); + return bootmedia; +} diff --git a/arch/arm/mach-k3/am62ax/Makefile b/arch/arm/mach-k3/am62ax/Makefile new file mode 100644 index 0000000000..c58e52df1f --- /dev/null +++ b/arch/arm/mach-k3/am62ax/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ + +obj-y += clk-data.o +obj-y += dev-data.o diff --git a/arch/arm/mach-k3/am62ax/clk-data.c b/arch/arm/mach-k3/am62ax/clk-data.c new file mode 100644 index 0000000000..d950b35e0b --- /dev/null +++ b/arch/arm/mach-k3/am62ax/clk-data.c @@ -0,0 +1,317 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * AM62AX specific clock platform data + * + * This file is auto generated. Please do not hand edit and report any issues + * to Bryan Brattlof <bb@ti.com>. + * + * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#include <linux/clk-provider.h> +#include "k3-clk.h" + +static const char * const gluelogic_hfosc0_clkout_parents[] = { + NULL, + NULL, + "osc_24_mhz", + "osc_25_mhz", + "osc_26_mhz", + NULL, +}; + +static const char * const clk_32k_rc_sel_out0_parents[] = { + "gluelogic_rcosc_clk_1p0v_97p65k", + "gluelogic_hfosc0_clkout", + "gluelogic_rcosc_clk_1p0v_97p65k", + "gluelogic_lfosc0_clkout", +}; + +static const char * const main_emmcsd0_io_clklb_sel_out0_parents[] = { + "board_0_mmc0_clklb_out", + "board_0_mmc0_clk_out", +}; + +static const char * const main_emmcsd1_io_clklb_sel_out0_parents[] = { + "board_0_mmc1_clklb_out", + "board_0_mmc1_clk_out", +}; + +static const char * const main_ospi_loopback_clk_sel_out0_parents[] = { + "board_0_ospi0_dqs_out", + "board_0_ospi0_lbclko_out", +}; + +static const char * const main_usb0_refclk_sel_out0_parents[] = { + "gluelogic_hfosc0_clkout", + "postdiv4_16ff_main_0_hsdivout8_clk", +}; + +static const char * const main_usb1_refclk_sel_out0_parents[] = { + "gluelogic_hfosc0_clkout", + "postdiv4_16ff_main_0_hsdivout8_clk", +}; + +static const char * const sam62_pll_ctrl_wrap_main_0_sysclkout_clk_parents[] = { + "gluelogic_hfosc0_clkout", + "hsdiv4_16fft_main_0_hsdivout0_clk", +}; + +static const char * const sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk_parents[] = { + "gluelogic_hfosc0_clkout", + "hsdiv4_16fft_mcu_0_hsdivout0_clk", +}; + +static const char * const clkout0_ctrl_out0_parents[] = { + "hsdiv4_16fft_main_2_hsdivout1_clk", + "hsdiv4_16fft_main_2_hsdivout1_clk", +}; + +static const char * const main_emmcsd0_refclk_sel_out0_parents[] = { + "postdiv4_16ff_main_0_hsdivout5_clk", + "hsdiv4_16fft_main_2_hsdivout2_clk", +}; + +static const char * const main_emmcsd1_refclk_sel_out0_parents[] = { + "postdiv4_16ff_main_0_hsdivout5_clk", + "hsdiv4_16fft_main_2_hsdivout2_clk", +}; + +static const char * const main_gtcclk_sel_out0_parents[] = { + "postdiv4_16ff_main_2_hsdivout5_clk", + "postdiv4_16ff_main_0_hsdivout6_clk", + "board_0_cp_gemac_cpts0_rft_clk_out", + NULL, + "board_0_mcu_ext_refclk0_out", + "board_0_ext_refclk1_out", + "sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk", + "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk", +}; + +static const char * const main_ospi_ref_clk_sel_out0_parents[] = { + "hsdiv4_16fft_main_0_hsdivout1_clk", + "postdiv1_16fft_main_1_hsdivout5_clk", +}; + +static const char * const wkup_clkout_sel_out0_parents[] = { + NULL, + "gluelogic_lfosc0_clkout", + "hsdiv4_16fft_main_0_hsdivout2_clk", + "hsdiv4_16fft_main_1_hsdivout2_clk", + "postdiv4_16ff_main_2_hsdivout9_clk", + "clk_32k_rc_sel_out0", + "gluelogic_rcosc_clkout", + "gluelogic_hfosc0_clkout", +}; + +static const char * const wkup_clkout_sel_io_out0_parents[] = { + "wkup_clkout_sel_out0", + "gluelogic_hfosc0_clkout", +}; + +static const char * const wkup_clksel_out0_parents[] = { + "hsdiv2_16fft_main_15_hsdivout0_clk", + "hsdiv4_16fft_mcu_0_hsdivout0_clk", +}; + +static const char * const main_usart0_fclk_sel_out0_parents[] = { + "usart_programmable_clock_divider_out0", + "hsdiv4_16fft_main_1_hsdivout1_clk", +}; + +static const struct clk_data clk_list[] = { + CLK_FIXED_RATE("osc_26_mhz", 26000000, 0), + CLK_FIXED_RATE("osc_25_mhz", 25000000, 0), + CLK_FIXED_RATE("osc_24_mhz", 24000000, 0), + CLK_MUX("gluelogic_hfosc0_clkout", gluelogic_hfosc0_clkout_parents, 6, 0x43000030, 0, 3, 0), + CLK_FIXED_RATE("gluelogic_rcosc_clkout", 12500000, 0), + CLK_FIXED_RATE("gluelogic_rcosc_clk_1p0v_97p65k", 97656, 0), + CLK_FIXED_RATE("board_0_cp_gemac_cpts0_rft_clk_out", 0, 0), + CLK_FIXED_RATE("board_0_ddr0_ck0_out", 0, 0), + CLK_FIXED_RATE("board_0_ext_refclk1_out", 0, 0), + CLK_FIXED_RATE("board_0_i2c0_scl_out", 0, 0), + CLK_FIXED_RATE("board_0_mcu_ext_refclk0_out", 0, 0), + CLK_FIXED_RATE("board_0_mmc0_clklb_out", 0, 0), + CLK_FIXED_RATE("board_0_mmc0_clk_out", 0, 0), + CLK_FIXED_RATE("board_0_mmc1_clklb_out", 0, 0), + CLK_FIXED_RATE("board_0_mmc1_clk_out", 0, 0), + CLK_FIXED_RATE("board_0_ospi0_dqs_out", 0, 0), + CLK_FIXED_RATE("board_0_ospi0_lbclko_out", 0, 0), + CLK_FIXED_RATE("board_0_tck_out", 0, 0), + CLK_FIXED_RATE("emmcsd4ss_main_0_emmcsdss_io_clk_o", 0, 0), + CLK_FIXED_RATE("emmcsd8ss_main_0_emmcsdss_io_clk_o", 0, 0), + CLK_FIXED_RATE("fss_ul_main_0_ospi_0_ospi_oclk_clk", 0, 0), + CLK_FIXED_RATE("mshsi2c_main_0_porscl", 0, 0), + CLK_PLL("pllfracf_ssmod_16fft_main_0_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x680000, 0), + CLK_DIV("pllfracf_ssmod_16fft_main_0_foutpostdiv_clk_subdiv", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", 0x680038, 16, 3, 0, CLK_DIVIDER_ONE_BASED), + CLK_DIV("pllfracf_ssmod_16fft_main_0_foutpostdiv_clk", "pllfracf_ssmod_16fft_main_0_foutpostdiv_clk_subdiv", 0x680038, 24, 3, 0, CLK_DIVIDER_ONE_BASED), + CLK_PLL("pllfracf_ssmod_16fft_main_1_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x681000, 0), + CLK_DIV("pllfracf_ssmod_16fft_main_1_foutpostdiv_clk_subdiv", "pllfracf_ssmod_16fft_main_1_foutvcop_clk", 0x681038, 16, 3, 0, CLK_DIVIDER_ONE_BASED), + CLK_DIV("pllfracf_ssmod_16fft_main_1_foutpostdiv_clk", "pllfracf_ssmod_16fft_main_1_foutpostdiv_clk_subdiv", 0x681038, 24, 3, 0, CLK_DIVIDER_ONE_BASED), + CLK_PLL("pllfracf_ssmod_16fft_main_12_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x68c000, 0), + CLK_PLL("pllfracf_ssmod_16fft_main_15_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x68f000, 0), + CLK_PLL("pllfracf_ssmod_16fft_main_2_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x682000, 0), + CLK_DIV("pllfracf_ssmod_16fft_main_2_foutpostdiv_clk_subdiv", "pllfracf_ssmod_16fft_main_2_foutvcop_clk", 0x682038, 16, 3, 0, CLK_DIVIDER_ONE_BASED), + CLK_DIV("pllfracf_ssmod_16fft_main_2_foutpostdiv_clk", "pllfracf_ssmod_16fft_main_2_foutpostdiv_clk_subdiv", 0x682038, 24, 3, 0, CLK_DIVIDER_ONE_BASED), + CLK_PLL("pllfracf_ssmod_16fft_main_8_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x688000, 0), + CLK_PLL("pllfracf_ssmod_16fft_mcu_0_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x4040000, 0), + CLK_DIV("postdiv1_16fft_main_1_hsdivout5_clk", "pllfracf_ssmod_16fft_main_1_foutpostdiv_clk", 0x681094, 0, 7, 0, 0), + CLK_DIV("postdiv4_16ff_main_0_hsdivout5_clk", "pllfracf_ssmod_16fft_main_0_foutpostdiv_clk", 0x680094, 0, 7, 0, 0), + CLK_DIV("postdiv4_16ff_main_0_hsdivout6_clk", "pllfracf_ssmod_16fft_main_0_foutpostdiv_clk", 0x680098, 0, 7, 0, 0), + CLK_DIV("postdiv4_16ff_main_0_hsdivout8_clk", "pllfracf_ssmod_16fft_main_0_foutpostdiv_clk", 0x6800a0, 0, 7, 0, 0), + CLK_DIV("postdiv4_16ff_main_2_hsdivout5_clk", "pllfracf_ssmod_16fft_main_2_foutpostdiv_clk", 0x682094, 0, 7, 0, 0), + CLK_DIV("postdiv4_16ff_main_2_hsdivout8_clk", "pllfracf_ssmod_16fft_main_2_foutpostdiv_clk", 0x6820a0, 0, 7, 0, 0), + CLK_DIV("postdiv4_16ff_main_2_hsdivout9_clk", "pllfracf_ssmod_16fft_main_2_foutpostdiv_clk", 0x6820a4, 0, 7, 0, 0), + CLK_MUX("clk_32k_rc_sel_out0", clk_32k_rc_sel_out0_parents, 4, 0x4508058, 0, 2, 0), + CLK_MUX("main_emmcsd0_io_clklb_sel_out0", main_emmcsd0_io_clklb_sel_out0_parents, 2, 0x108160, 16, 1, 0), + CLK_MUX("main_emmcsd1_io_clklb_sel_out0", main_emmcsd1_io_clklb_sel_out0_parents, 2, 0x108168, 16, 1, 0), + CLK_MUX("main_ospi_loopback_clk_sel_out0", main_ospi_loopback_clk_sel_out0_parents, 2, 0x108500, 4, 1, 0), + CLK_MUX("main_usb0_refclk_sel_out0", main_usb0_refclk_sel_out0_parents, 2, 0x43008190, 0, 1, 0), + CLK_MUX("main_usb1_refclk_sel_out0", main_usb1_refclk_sel_out0_parents, 2, 0x43008194, 0, 1, 0), + CLK_DIV("hsdiv0_16fft_main_12_hsdivout0_clk", "pllfracf_ssmod_16fft_main_12_foutvcop_clk", 0x68c080, 0, 7, 0, 0), + CLK_DIV("hsdiv0_16fft_main_8_hsdivout0_clk", "pllfracf_ssmod_16fft_main_8_foutvcop_clk", 0x688080, 0, 7, 0, 0), + CLK_DIV("hsdiv2_16fft_main_15_hsdivout0_clk", "pllfracf_ssmod_16fft_main_15_foutvcop_clk", 0x68f080, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_main_0_hsdivout0_clk", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", 0x680080, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_main_0_hsdivout1_clk", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", 0x680084, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_main_0_hsdivout2_clk", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", 0x680088, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_main_0_hsdivout3_clk", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", 0x68008c, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_main_0_hsdivout4_clk", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", 0x680090, 0, 7, 0, 0), + CLK_DIV_DEFFREQ("hsdiv4_16fft_main_1_hsdivout0_clk", "pllfracf_ssmod_16fft_main_1_foutvcop_clk", 0x681080, 0, 7, 0, 0, 192000000), + CLK_DIV("hsdiv4_16fft_main_1_hsdivout1_clk", "pllfracf_ssmod_16fft_main_1_foutvcop_clk", 0x681084, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_main_1_hsdivout2_clk", "pllfracf_ssmod_16fft_main_1_foutvcop_clk", 0x681088, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_main_2_hsdivout1_clk", "pllfracf_ssmod_16fft_main_2_foutvcop_clk", 0x682084, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_main_2_hsdivout2_clk", "pllfracf_ssmod_16fft_main_2_foutvcop_clk", 0x682088, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_mcu_0_hsdivout0_clk", "pllfracf_ssmod_16fft_mcu_0_foutvcop_clk", 0x4040080, 0, 7, 0, 0), + CLK_MUX_PLLCTRL("sam62_pll_ctrl_wrap_main_0_sysclkout_clk", sam62_pll_ctrl_wrap_main_0_sysclkout_clk_parents, 2, 0x410000, 0), + CLK_DIV("sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk", "sam62_pll_ctrl_wrap_main_0_sysclkout_clk", 0x410118, 0, 5, 0, 0), + CLK_MUX_PLLCTRL("sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk", sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk_parents, 2, 0x4020000, 0), + CLK_DIV("sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk", "sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk", 0x4020118, 0, 5, 0, 0), + CLK_MUX("clkout0_ctrl_out0", clkout0_ctrl_out0_parents, 2, 0x108010, 0, 1, 0), + CLK_MUX("main_emmcsd0_refclk_sel_out0", main_emmcsd0_refclk_sel_out0_parents, 2, 0x108160, 0, 1, 0), + CLK_MUX("main_emmcsd1_refclk_sel_out0", main_emmcsd1_refclk_sel_out0_parents, 2, 0x108168, 0, 1, 0), + CLK_MUX("main_gtcclk_sel_out0", main_gtcclk_sel_out0_parents, 8, 0x43008030, 0, 3, 0), + CLK_MUX("main_ospi_ref_clk_sel_out0", main_ospi_ref_clk_sel_out0_parents, 2, 0x108500, 0, 1, 0), + CLK_DIV_DEFFREQ("usart_programmable_clock_divider_out0", "hsdiv4_16fft_main_1_hsdivout0_clk", 0x108240, 0, 2, 0, 0, 48000000), + CLK_MUX("wkup_clkout_sel_out0", wkup_clkout_sel_out0_parents, 8, 0x43008020, 0, 3, 0), + CLK_MUX("wkup_clkout_sel_io_out0", wkup_clkout_sel_io_out0_parents, 2, 0x43008020, 24, 1, 0), + CLK_MUX("wkup_clksel_out0", wkup_clksel_out0_parents, 2, 0x43008010, 0, 1, 0), + CLK_MUX("main_usart0_fclk_sel_out0", main_usart0_fclk_sel_out0_parents, 2, 0x108280, 0, 1, 0), + CLK_DIV("hsdiv4_16fft_mcu_0_hsdivout1_clk", "pllfracf_ssmod_16fft_mcu_0_foutvcop_clk", 0x4040084, 0, 7, 0, 0), + CLK_FIXED_RATE("mshsi2c_wkup_0_porscl", 0, 0), + CLK_DIV("sam62_pll_ctrl_wrap_main_0_chip_div24_clk_clk", "sam62_pll_ctrl_wrap_main_0_sysclkout_clk", 0x41011c, 0, 5, 0, 0), + CLK_DIV("sam62_pll_ctrl_wrap_mcu_0_chip_div24_clk_clk", "sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk", 0x402011c, 0, 5, 0, 0), +}; + +static const struct dev_clk soc_dev_clk_data[] = { + DEV_CLK(16, 0, "hsdiv4_16fft_main_0_hsdivout1_clk"), + DEV_CLK(16, 1, "hsdiv4_16fft_main_0_hsdivout2_clk"), + DEV_CLK(16, 2, "hsdiv4_16fft_main_0_hsdivout3_clk"), + DEV_CLK(16, 3, "hsdiv4_16fft_main_0_hsdivout4_clk"), + DEV_CLK(16, 4, "gluelogic_hfosc0_clkout"), + DEV_CLK(16, 5, "board_0_ext_refclk1_out"), + DEV_CLK(16, 6, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(16, 7, "postdiv4_16ff_main_2_hsdivout8_clk"), + DEV_CLK(16, 8, "gluelogic_hfosc0_clkout"), + DEV_CLK(16, 9, "board_0_ext_refclk1_out"), + DEV_CLK(16, 10, "gluelogic_rcosc_clkout"), + DEV_CLK(16, 11, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(16, 12, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(57, 0, "main_emmcsd0_io_clklb_sel_out0"), + DEV_CLK(57, 1, "board_0_mmc0_clklb_out"), + DEV_CLK(57, 2, "board_0_mmc0_clk_out"), + DEV_CLK(57, 5, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(57, 6, "main_emmcsd0_refclk_sel_out0"), + DEV_CLK(57, 7, "postdiv4_16ff_main_0_hsdivout5_clk"), + DEV_CLK(57, 8, "hsdiv4_16fft_main_2_hsdivout2_clk"), + DEV_CLK(58, 0, "main_emmcsd1_io_clklb_sel_out0"), + DEV_CLK(58, 1, "board_0_mmc1_clklb_out"), + DEV_CLK(58, 2, "board_0_mmc1_clk_out"), + DEV_CLK(58, 5, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(58, 6, "main_emmcsd1_refclk_sel_out0"), + DEV_CLK(58, 7, "postdiv4_16ff_main_0_hsdivout5_clk"), + DEV_CLK(58, 8, "hsdiv4_16fft_main_2_hsdivout2_clk"), + DEV_CLK(61, 0, "main_gtcclk_sel_out0"), + DEV_CLK(61, 1, "postdiv4_16ff_main_2_hsdivout5_clk"), + DEV_CLK(61, 2, "postdiv4_16ff_main_0_hsdivout6_clk"), + DEV_CLK(61, 3, "board_0_cp_gemac_cpts0_rft_clk_out"), + DEV_CLK(61, 5, "board_0_mcu_ext_refclk0_out"), + DEV_CLK(61, 6, "board_0_ext_refclk1_out"), + DEV_CLK(61, 7, "sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk"), + DEV_CLK(61, 8, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(61, 9, "wkup_clksel_out0"), + DEV_CLK(61, 10, "hsdiv2_16fft_main_15_hsdivout0_clk"), + DEV_CLK(61, 11, "hsdiv4_16fft_mcu_0_hsdivout0_clk"), + DEV_CLK(75, 0, "board_0_ospi0_dqs_out"), + DEV_CLK(75, 1, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(75, 2, "main_ospi_loopback_clk_sel_out0"), + DEV_CLK(75, 3, "board_0_ospi0_dqs_out"), + DEV_CLK(75, 4, "board_0_ospi0_lbclko_out"), + DEV_CLK(75, 6, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(75, 7, "main_ospi_ref_clk_sel_out0"), + DEV_CLK(75, 8, "hsdiv4_16fft_main_0_hsdivout1_clk"), + DEV_CLK(75, 9, "postdiv1_16fft_main_1_hsdivout5_clk"), + DEV_CLK(77, 0, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(95, 0, "gluelogic_rcosc_clkout"), + DEV_CLK(95, 1, "gluelogic_hfosc0_clkout"), + DEV_CLK(95, 2, "wkup_clksel_out0"), + DEV_CLK(95, 3, "hsdiv2_16fft_main_15_hsdivout0_clk"), + DEV_CLK(95, 4, "hsdiv4_16fft_mcu_0_hsdivout0_clk"), + DEV_CLK(102, 0, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(102, 1, "board_0_i2c0_scl_out"), + DEV_CLK(102, 2, "hsdiv4_16fft_main_1_hsdivout0_clk"), + DEV_CLK(107, 0, "wkup_clksel_out0"), + DEV_CLK(107, 1, "hsdiv2_16fft_main_15_hsdivout0_clk"), + DEV_CLK(107, 2, "hsdiv4_16fft_mcu_0_hsdivout0_clk"), + DEV_CLK(107, 4, "hsdiv4_16fft_mcu_0_hsdivout1_clk"), + DEV_CLK(135, 0, "hsdiv0_16fft_main_8_hsdivout0_clk"), + DEV_CLK(140, 0, "sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk"), + DEV_CLK(140, 1, "sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk"), + DEV_CLK(146, 0, "main_usart0_fclk_sel_out0"), + DEV_CLK(146, 1, "usart_programmable_clock_divider_out0"), + DEV_CLK(146, 2, "hsdiv4_16fft_main_1_hsdivout1_clk"), + DEV_CLK(146, 5, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(157, 20, "clkout0_ctrl_out0"), + DEV_CLK(157, 21, "hsdiv4_16fft_main_2_hsdivout1_clk"), + DEV_CLK(157, 22, "hsdiv4_16fft_main_2_hsdivout1_clk"), + DEV_CLK(157, 24, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(157, 25, "board_0_ddr0_ck0_out"), + DEV_CLK(157, 40, "mshsi2c_main_0_porscl"), + DEV_CLK(157, 77, "sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk"), + DEV_CLK(157, 83, "emmcsd8ss_main_0_emmcsdss_io_clk_o"), + DEV_CLK(157, 85, "emmcsd8ss_main_0_emmcsdss_io_clk_o"), + DEV_CLK(157, 87, "emmcsd4ss_main_0_emmcsdss_io_clk_o"), + DEV_CLK(157, 89, "emmcsd4ss_main_0_emmcsdss_io_clk_o"), + DEV_CLK(157, 130, "fss_ul_main_0_ospi_0_ospi_oclk_clk"), + DEV_CLK(157, 146, "sam62_pll_ctrl_wrap_main_0_sysclkout_clk"), + DEV_CLK(157, 159, "wkup_clkout_sel_io_out0"), + DEV_CLK(157, 160, "wkup_clkout_sel_out0"), + DEV_CLK(157, 161, "gluelogic_hfosc0_clkout"), + DEV_CLK(161, 0, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(161, 1, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(161, 2, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(161, 3, "main_usb0_refclk_sel_out0"), + DEV_CLK(161, 4, "gluelogic_hfosc0_clkout"), + DEV_CLK(161, 5, "postdiv4_16ff_main_0_hsdivout8_clk"), + DEV_CLK(161, 10, "board_0_tck_out"), + DEV_CLK(162, 0, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(162, 1, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(162, 2, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(162, 3, "main_usb1_refclk_sel_out0"), + DEV_CLK(162, 4, "gluelogic_hfosc0_clkout"), + DEV_CLK(162, 5, "postdiv4_16ff_main_0_hsdivout8_clk"), + DEV_CLK(162, 10, "board_0_tck_out"), + DEV_CLK(166, 3, "hsdiv0_16fft_main_8_hsdivout0_clk"), + DEV_CLK(166, 5, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(169, 0, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(169, 1, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(170, 1, "hsdiv0_16fft_main_12_hsdivout0_clk"), + DEV_CLK(170, 2, "board_0_tck_out"), + DEV_CLK(170, 3, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), +}; + +const struct ti_k3_clk_platdata am62ax_clk_platdata = { + .clk_list = clk_list, + .clk_list_cnt = 80, + .soc_dev_clk_data = soc_dev_clk_data, + .soc_dev_clk_data_cnt = 104, +}; diff --git a/arch/arm/mach-k3/am62ax/dev-data.c b/arch/arm/mach-k3/am62ax/dev-data.c new file mode 100644 index 0000000000..74739c6385 --- /dev/null +++ b/arch/arm/mach-k3/am62ax/dev-data.c @@ -0,0 +1,73 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * AM62AX specific device platform data + * + * This file is auto generated. Please do not hand edit and report any issues + * to Bryan Brattlof <bb@ti.com>. + * + * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#include "k3-dev.h" + +static struct ti_psc soc_psc_list[] = { + [0] = PSC(0, 0x04000000), + [1] = PSC(1, 0x00400000), +}; + +static struct ti_pd soc_pd_list[] = { + [0] = PSC_PD(0, &soc_psc_list[1], NULL), + [1] = PSC_PD(3, &soc_psc_list[1], &soc_pd_list[0]), + [2] = PSC_PD(4, &soc_psc_list[1], &soc_pd_list[1]), + [3] = PSC_PD(13, &soc_psc_list[1], &soc_pd_list[0]), +}; + +static struct ti_lpsc soc_lpsc_list[] = { + [0] = PSC_LPSC(0, &soc_psc_list[1], &soc_pd_list[0], NULL), + [1] = PSC_LPSC(12, &soc_psc_list[1], &soc_pd_list[0], &soc_lpsc_list[5]), + [2] = PSC_LPSC(13, &soc_psc_list[1], &soc_pd_list[0], &soc_lpsc_list[6]), + [3] = PSC_LPSC(20, &soc_psc_list[1], &soc_pd_list[0], &soc_lpsc_list[8]), + [4] = PSC_LPSC(21, &soc_psc_list[1], &soc_pd_list[0], &soc_lpsc_list[8]), + [5] = PSC_LPSC(23, &soc_psc_list[1], &soc_pd_list[0], &soc_lpsc_list[8]), + [6] = PSC_LPSC(24, &soc_psc_list[1], &soc_pd_list[0], &soc_lpsc_list[8]), + [7] = PSC_LPSC(28, &soc_psc_list[1], &soc_pd_list[0], &soc_lpsc_list[8]), + [8] = PSC_LPSC(34, &soc_psc_list[1], &soc_pd_list[0], &soc_lpsc_list[8]), + [9] = PSC_LPSC(43, &soc_psc_list[1], &soc_pd_list[1], &soc_lpsc_list[8]), + [10] = PSC_LPSC(46, &soc_psc_list[1], &soc_pd_list[2], &soc_lpsc_list[9]), + [11] = PSC_LPSC(60, &soc_psc_list[1], &soc_pd_list[3], &soc_lpsc_list[8]), + [12] = PSC_LPSC(61, &soc_psc_list[1], &soc_pd_list[3], &soc_lpsc_list[11]), + [13] = PSC_LPSC(62, &soc_psc_list[1], &soc_pd_list[3], &soc_lpsc_list[12]), +}; + +static struct ti_dev soc_dev_list[] = { + PSC_DEV(16, &soc_lpsc_list[0]), + PSC_DEV(77, &soc_lpsc_list[0]), + PSC_DEV(61, &soc_lpsc_list[0]), + PSC_DEV(95, &soc_lpsc_list[0]), + PSC_DEV(107, &soc_lpsc_list[0]), + PSC_DEV(178, &soc_lpsc_list[1]), + PSC_DEV(179, &soc_lpsc_list[2]), + PSC_DEV(57, &soc_lpsc_list[3]), + PSC_DEV(58, &soc_lpsc_list[4]), + PSC_DEV(161, &soc_lpsc_list[5]), + PSC_DEV(162, &soc_lpsc_list[6]), + PSC_DEV(75, &soc_lpsc_list[7]), + PSC_DEV(102, &soc_lpsc_list[8]), + PSC_DEV(146, &soc_lpsc_list[8]), + PSC_DEV(166, &soc_lpsc_list[9]), + PSC_DEV(135, &soc_lpsc_list[10]), + PSC_DEV(170, &soc_lpsc_list[11]), + PSC_DEV(177, &soc_lpsc_list[12]), + PSC_DEV(55, &soc_lpsc_list[13]), +}; + +const struct ti_k3_pd_platdata am62ax_pd_platdata = { + .psc = soc_psc_list, + .pd = soc_pd_list, + .lpsc = soc_lpsc_list, + .devs = soc_dev_list, + .num_psc = 2, + .num_pd = 4, + .num_lpsc = 14, + .num_devs = 19, +}; diff --git a/arch/arm/mach-k3/arm64-mmu.c b/arch/arm/mach-k3/arm64-mmu.c index b4d7ab1f16..88687c2d09 100644 --- a/arch/arm/mach-k3/arm64-mmu.c +++ b/arch/arm/mach-k3/arm64-mmu.c @@ -222,7 +222,9 @@ struct mm_region *mem_map = j721s2_mem_map; #endif /* CONFIG_SOC_K3_J721S2 */ -#if defined(CONFIG_SOC_K3_AM642) || defined(CONFIG_SOC_K3_AM625) +#if defined(CONFIG_SOC_K3_AM642) || defined(CONFIG_SOC_K3_AM625) || \ + defined(CONFIG_SOC_K3_AM62A7) + /* NR_DRAM_BANKS + 32bit IO + 64bit IO + terminator */ #define NR_MMU_REGIONS (CONFIG_NR_DRAM_BANKS + 3) @@ -261,4 +263,4 @@ struct mm_region am64_mem_map[NR_MMU_REGIONS] = { }; struct mm_region *mem_map = am64_mem_map; -#endif /* CONFIG_SOC_K3_AM642 || CONFIG_SOC_K3_AM625 */ +#endif /* CONFIG_SOC_K3_AM642 || CONFIG_SOC_K3_AM625 || CONFIG_SOC_K3_AM62A7 */ diff --git a/arch/arm/mach-k3/common.c b/arch/arm/mach-k3/common.c index 227706e8dc..d5e1f8e2e7 100644 --- a/arch/arm/mach-k3/common.c +++ b/arch/arm/mach-k3/common.c @@ -561,7 +561,7 @@ void remove_fwl_configs(struct fwl_data *fwl_data, size_t fwl_data_size) void spl_enable_dcache(void) { #if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF)) - phys_addr_t ram_top = CONFIG_SYS_SDRAM_BASE; + phys_addr_t ram_top = CFG_SYS_SDRAM_BASE; dram_init(); diff --git a/arch/arm/mach-k3/config_secure.mk b/arch/arm/mach-k3/config_secure.mk index 9cc1f9eb24..7bc8af813a 100644 --- a/arch/arm/mach-k3/config_secure.mk +++ b/arch/arm/mach-k3/config_secure.mk @@ -30,7 +30,7 @@ tispl.bin_HS: $(obj)/u-boot-spl-nodtb.bin_HS $(patsubst %,$(obj)/dts/%.dtb_HS,$( $(call if_changed,mkfitimage) MKIMAGEFLAGS_u-boot.img_HS = -f auto -A $(ARCH) -T firmware -C none -O u-boot \ - -a $(CONFIG_TEXT_BASE) -e $(CONFIG_SYS_UBOOT_START) \ + -a $(CONFIG_TEXT_BASE) -e $(CFG_SYS_UBOOT_START) \ -n "U-Boot $(UBOOTRELEASE) for $(BOARD) board" -E \ $(patsubst %,-b arch/$(ARCH)/dts/%.dtb_HS,$(subst ",,$(CONFIG_OF_LIST))) diff --git a/arch/arm/mach-k3/include/mach/am62a_hardware.h b/arch/arm/mach-k3/include/mach/am62a_hardware.h new file mode 100644 index 0000000000..52b0d9b3cb --- /dev/null +++ b/arch/arm/mach-k3/include/mach/am62a_hardware.h @@ -0,0 +1,74 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * K3: AM62A SoC definitions, structures etc. + * + * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#ifndef __ASM_ARCH_AM62A_HARDWARE_H +#define __ASM_ARCH_AM62A_HARDWARE_H + +#include <config.h> +#ifndef __ASSEMBLY__ +#include <linux/bitops.h> +#endif + +#define PADCFG_MMR0_BASE 0x04080000 +#define PADCFG_MMR1_BASE 0x000f0000 +#define CTRL_MMR0_BASE 0x00100000 +#define MCU_CTRL_MMR0_BASE 0x04500000 +#define WKUP_CTRL_MMR0_BASE 0x43000000 + +#define CTRLMMR_MAIN_DEVSTAT (WKUP_CTRL_MMR0_BASE + 0x30) +#define MAIN_DEVSTAT_PRIMARY_BOOTMODE_MASK GENMASK(6, 3) +#define MAIN_DEVSTAT_PRIMARY_BOOTMODE_SHIFT 3 +#define MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_MASK GENMASK(9, 7) +#define MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_SHIFT 7 +#define MAIN_DEVSTAT_BACKUP_BOOTMODE_MASK GENMASK(12, 10) +#define MAIN_DEVSTAT_BACKUP_BOOTMODE_SHIFT 10 +#define MAIN_DEVSTAT_BACKUP_BOOTMODE_CFG_MASK BIT(13) +#define MAIN_DEVSTAT_BACKUP_BOOTMODE_CFG_SHIFT 13 + +/* Primary Bootmode MMC Config macros */ +#define MAIN_DEVSTAT_PRIMARY_MMC_PORT_MASK 0x4 +#define MAIN_DEVSTAT_PRIMARY_MMC_PORT_SHIFT 2 +#define MAIN_DEVSTAT_PRIMARY_MMC_FS_RAW_MASK 0x1 +#define MAIN_DEVSTAT_PRIMARY_MMC_FS_RAW_SHIFT 0 + +/* Primary Bootmode USB Config macros */ +#define MAIN_DEVSTAT_PRIMARY_USB_MODE_SHIFT 1 +#define MAIN_DEVSTAT_PRIMARY_USB_MODE_MASK 0x02 + +/* Backup Bootmode USB Config macros */ +#define MAIN_DEVSTAT_BACKUP_USB_MODE_MASK 0x01 + +/* + * The CTRL_MMR0 memory space is divided into several equally-spaced + * partitions, so defining the partition size allows us to determine + * register addresses common to those partitions. + */ +#define CTRL_MMR0_PARTITION_SIZE 0x4000 + +/* + * CTRL_MMR0, WKUP_CTRL_MMR0, and MCU_CTRL_MMR0 lock/kick-mechanism + * shared register definitions. The same registers are also used for + * PADCFG_MMR lock/kick-mechanism. + */ +#define CTRLMMR_LOCK_KICK0 0x1008 +#define CTRLMMR_LOCK_KICK0_UNLOCK_VAL 0x68ef3490 +#define CTRLMMR_LOCK_KICK1 0x100c +#define CTRLMMR_LOCK_KICK1_UNLOCK_VAL 0xd172bc5a + +#define MCU_CTRL_LFXOSC_CTRL (MCU_CTRL_MMR0_BASE + 0x8038) +#define MCU_CTRL_LFXOSC_TRIM (MCU_CTRL_MMR0_BASE + 0x803c) +#define MCU_CTRL_LFXOSC_32K_DISABLE_VAL BIT(7) + +#define MCU_CTRL_DEVICE_CLKOUT_32K_CTRL (MCU_CTRL_MMR0_BASE + 0x8058) +#define MCU_CTRL_DEVICE_CLKOUT_LFOSC_SELECT_VAL (0x3) + +#define ROM_ENTENDED_BOOT_DATA_INFO 0x43c3f1e0 + +/* Use Last 2K as Scratch pad */ +#define TI_SRAM_SCRATCH_BOARD_EEPROM_START 0x70000001 + +#endif /* __ASM_ARCH_AM62A_HARDWARE_H */ diff --git a/arch/arm/mach-k3/include/mach/am62a_spl.h b/arch/arm/mach-k3/include/mach/am62a_spl.h new file mode 100644 index 0000000000..dd0f57714f --- /dev/null +++ b/arch/arm/mach-k3/include/mach/am62a_spl.h @@ -0,0 +1,49 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#ifndef _ASM_ARCH_AM62A_SPL_H_ +#define _ASM_ARCH_AM62A_SPL_H_ + +/* Primary BootMode devices */ +#define BOOT_DEVICE_SPI_NAND 0x00 +#define BOOT_DEVICE_RAM 0xFF +#define BOOT_DEVICE_OSPI 0x01 +#define BOOT_DEVICE_QSPI 0x02 +#define BOOT_DEVICE_SPI 0x03 +#define BOOT_DEVICE_CPGMAC 0x04 +#define BOOT_DEVICE_ETHERNET_RGMII 0x04 +#define BOOT_DEVICE_ETHERNET_RMII 0x05 +#define BOOT_DEVICE_I2C 0x06 +#define BOOT_DEVICE_UART 0x07 +#define BOOT_DEVICE_MMC 0x08 +#define BOOT_DEVICE_EMMC 0x09 + +#define BOOT_DEVICE_USB 0x2A +#define BOOT_DEVICE_DFU 0x0A +#define BOOT_DEVICE_GPMC_NAND 0x0B +#define BOOT_DEVICE_GPMC_NOR 0x0C +#define BOOT_DEVICE_XSPI 0x0E +#define BOOT_DEVICE_NOBOOT 0x0F + +/* U-Boot used aliases */ +#define BOOT_DEVICE_ETHERNET 0x04 +#define BOOT_DEVICE_SPINAND 0x10 +#define BOOT_DEVICE_MMC2 0x08 +#define BOOT_DEVICE_MMC1 0x09 +/* Invalid */ +#define BOOT_DEVICE_MMC2_2 0x1F + +/* Backup BootMode devices */ +#define BACKUP_BOOT_DEVICE_DFU 0x01 +#define BACKUP_BOOT_DEVICE_UART 0x03 +#define BACKUP_BOOT_DEVICE_ETHERNET 0x04 +#define BACKUP_BOOT_DEVICE_MMC 0x05 +#define BACKUP_BOOT_DEVICE_SPI 0x06 +#define BACKUP_BOOT_DEVICE_I2C 0x07 +#define BACKUP_BOOT_DEVICE_USB 0x09 + +#define K3_PRIMARY_BOOTMODE 0x0 + +#endif /* _ASM_ARCH_AM62A_SPL_H_ */ diff --git a/arch/arm/mach-k3/include/mach/hardware.h b/arch/arm/mach-k3/include/mach/hardware.h index d6d2cf6dc2..2c60ef8543 100644 --- a/arch/arm/mach-k3/include/mach/hardware.h +++ b/arch/arm/mach-k3/include/mach/hardware.h @@ -26,6 +26,10 @@ #include "am62_hardware.h" #endif +#ifdef CONFIG_SOC_K3_AM62A7 +#include "am62a_hardware.h" +#endif + /* Assuming these addresses and definitions stay common across K3 devices */ #define CTRLMMR_WKUP_JTAG_ID (WKUP_CTRL_MMR0_BASE + 0x14) #define JTAG_ID_VARIANT_SHIFT 28 diff --git a/arch/arm/mach-k3/include/mach/spl.h b/arch/arm/mach-k3/include/mach/spl.h index c9a324a5f0..356cd89210 100644 --- a/arch/arm/mach-k3/include/mach/spl.h +++ b/arch/arm/mach-k3/include/mach/spl.h @@ -26,4 +26,8 @@ #include "am62_spl.h" #endif +#ifdef CONFIG_SOC_K3_AM62A7 +#include "am62a_spl.h" +#endif + #endif /* _ASM_ARCH_SPL_H_ */ diff --git a/arch/arm/mach-k3/r5_mpu.c b/arch/arm/mach-k3/r5_mpu.c index 3d2ff6775a..2aec96277e 100644 --- a/arch/arm/mach-k3/r5_mpu.c +++ b/arch/arm/mach-k3/r5_mpu.c @@ -24,7 +24,7 @@ struct mpu_region_config k3_mpu_regions[16] = { O_I_WB_RD_WR_ALLOC, REGION_8MB}, /* U-Boot's code area marking it as WB and Write allocate */ - {CONFIG_SYS_SDRAM_BASE, REGION_2, XN_DIS, PRIV_RW_USR_RW, + {CFG_SYS_SDRAM_BASE, REGION_2, XN_DIS, PRIV_RW_USR_RW, O_I_WB_RD_WR_ALLOC, REGION_2GB}, /* mcu_r5fss0_core0 BTCM area marking it as WB and Write allocate. */ {0x41010000, 3, XN_DIS, PRIV_RW_USR_RW, O_I_WB_RD_WR_ALLOC, diff --git a/arch/arm/mach-keystone/cmd_mon.c b/arch/arm/mach-keystone/cmd_mon.c index 4734e4c714..dc97bac855 100644 --- a/arch/arm/mach-keystone/cmd_mon.c +++ b/arch/arm/mach-keystone/cmd_mon.c @@ -23,7 +23,7 @@ static int do_mon_install(struct cmd_tbl *cmdtp, int flag, int argc, if (argc < 2) return CMD_RET_USAGE; - freq = CONFIG_SYS_HZ_CLOCK; + freq = CFG_SYS_HZ_CLOCK; addr = hextoul(argv[1], NULL); diff --git a/arch/arm/mach-keystone/ddr3.c b/arch/arm/mach-keystone/ddr3.c index 53117c2695..ea7d0b903c 100644 --- a/arch/arm/mach-keystone/ddr3.c +++ b/arch/arm/mach-keystone/ddr3.c @@ -318,7 +318,7 @@ void ddr3_init_ecc(u32 base, u32 ddr3_size) } ddr3_ecc_init_range(base); - ddr3_reset_data(CONFIG_SYS_SDRAM_BASE, ddr3_size); + ddr3_reset_data(CFG_SYS_SDRAM_BASE, ddr3_size); /* mapping DDR3 ECC system interrupt from CIC2 to GIC */ #if defined(CONFIG_SOC_K2HK) || defined(CONFIG_SOC_K2L) diff --git a/arch/arm/mach-keystone/include/mach/hardware.h b/arch/arm/mach-keystone/include/mach/hardware.h index 98a8f058df..424c32a4be 100644 --- a/arch/arm/mach-keystone/include/mach/hardware.h +++ b/arch/arm/mach-keystone/include/mach/hardware.h @@ -263,7 +263,7 @@ typedef volatile unsigned int *dv_reg_p; /* MSMC segment size shift bits */ #define KS2_MSMC_SEG_SIZE_SHIFT 12 #define KS2_MSMC_MAP_SEG_NUM (2 << (30 - KS2_MSMC_SEG_SIZE_SHIFT)) -#define KS2_MSMC_DST_SEG_BASE (CONFIG_SYS_LPAE_SDRAM_BASE >> \ +#define KS2_MSMC_DST_SEG_BASE (CFG_SYS_LPAE_SDRAM_BASE >> \ KS2_MSMC_SEG_SIZE_SHIFT) /* Device speed */ diff --git a/arch/arm/mach-keystone/init.c b/arch/arm/mach-keystone/init.c index 5b95f60500..1954e69e9f 100644 --- a/arch/arm/mach-keystone/init.c +++ b/arch/arm/mach-keystone/init.c @@ -185,8 +185,8 @@ int arch_cpu_init(void) * driver doesn't handle this. */ #ifndef CONFIG_DM_SERIAL - ns16550_init((struct ns16550 *)(CONFIG_SYS_NS16550_COM2), - CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE); + ns16550_init((struct ns16550 *)(CFG_SYS_NS16550_COM2), + CFG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE); #endif return 0; diff --git a/arch/arm/mach-kirkwood/include/mach/config.h b/arch/arm/mach-kirkwood/include/mach/config.h index d877be119f..fbef9c99b1 100644 --- a/arch/arm/mach-kirkwood/include/mach/config.h +++ b/arch/arm/mach-kirkwood/include/mach/config.h @@ -24,7 +24,7 @@ #include <asm/arch/soc.h> -#define CONFIG_I2C_MVTWSI_BASE0 KW_TWSI_BASE +#define CFG_I2C_MVTWSI_BASE0 KW_TWSI_BASE #define MV_UART_CONSOLE_BASE KW_UART0_BASE #define MV_SATA_BASE KW_SATA_BASE #define MV_SATA_PORT0_OFFSET KW_SATA_PORT0_OFFSET @@ -34,8 +34,7 @@ * NAND configuration */ #ifdef CONFIG_CMD_NAND -#define CONFIG_NAND_KIRKWOOD -#define CONFIG_SYS_NAND_BASE 0xD8000000 /* MV_DEFADR_NANDF */ +#define CFG_SYS_NAND_BASE 0xD8000000 /* MV_DEFADR_NANDF */ #define NAND_ALLOW_ERASE_ALL 1 #endif @@ -52,9 +51,8 @@ /* Use common timer */ #ifndef CONFIG_TIMER -#define CONFIG_SYS_TIMER_COUNTS_DOWN -#define CONFIG_SYS_TIMER_COUNTER (MVEBU_TIMER_BASE + 0x14) -#define CONFIG_SYS_TIMER_RATE CONFIG_SYS_TCLK +#define CFG_SYS_TIMER_COUNTER (MVEBU_TIMER_BASE + 0x14) +#define CFG_SYS_TIMER_RATE CFG_SYS_TCLK #endif #endif /* _KW_CONFIG_H */ diff --git a/arch/arm/mach-kirkwood/include/mach/kw88f6192.h b/arch/arm/mach-kirkwood/include/mach/kw88f6192.h index c44eacfc1b..d3a3a83657 100644 --- a/arch/arm/mach-kirkwood/include/mach/kw88f6192.h +++ b/arch/arm/mach-kirkwood/include/mach/kw88f6192.h @@ -15,6 +15,6 @@ #define KW_REGS_PHY_BASE KW88F6192_REGS_PHYS_BASE /* TCLK Core Clock defination */ -#define CONFIG_SYS_TCLK 166000000 /* 166MHz */ +#define CFG_SYS_TCLK 166000000 /* 166MHz */ #endif /* _CONFIG_KW88F6192_H */ diff --git a/arch/arm/mach-kirkwood/include/mach/kw88f6281.h b/arch/arm/mach-kirkwood/include/mach/kw88f6281.h index f86cd0bb60..67f0b3ec67 100644 --- a/arch/arm/mach-kirkwood/include/mach/kw88f6281.h +++ b/arch/arm/mach-kirkwood/include/mach/kw88f6281.h @@ -15,7 +15,7 @@ #define KW_REGS_PHY_BASE KW88F6281_REGS_PHYS_BASE /* TCLK Core Clock definition */ -#define CONFIG_SYS_TCLK ((readl(CONFIG_SAR_REG) & BIT(21)) ? \ +#define CFG_SYS_TCLK ((readl(CFG_SAR_REG) & BIT(21)) ? \ 166666667 : 200000000) #endif /* _ASM_ARCH_KW88F6281_H */ diff --git a/arch/arm/mach-kirkwood/include/mach/soc.h b/arch/arm/mach-kirkwood/include/mach/soc.h index 5f545c6f43..4a7efc50f6 100644 --- a/arch/arm/mach-kirkwood/include/mach/soc.h +++ b/arch/arm/mach-kirkwood/include/mach/soc.h @@ -62,7 +62,7 @@ #define MVCPU_WIN_ENABLE KWCPU_WIN_ENABLE #define MVCPU_WIN_DISABLE KWCPU_WIN_DISABLE -#define CONFIG_SAR_REG (KW_MPP_BASE + 0x0030) +#define CFG_SAR_REG (KW_MPP_BASE + 0x0030) #if defined (CONFIG_KW88F6281) #include <asm/arch/kw88f6281.h> diff --git a/arch/arm/mach-lpc32xx/devices.c b/arch/arm/mach-lpc32xx/devices.c index 0a4fef295a..6a67a3591a 100644 --- a/arch/arm/mach-lpc32xx/devices.c +++ b/arch/arm/mach-lpc32xx/devices.c @@ -6,7 +6,6 @@ #include <common.h> #include <dm.h> #include <ns16550.h> -#include <dm/platform_data/lpc32xx_hsuart.h> #include <asm/arch/clk.h> #include <asm/arch/uart.h> @@ -44,35 +43,20 @@ void lpc32xx_uart_init(unsigned int uart_id) #if !CONFIG_IS_ENABLED(OF_CONTROL) static const struct ns16550_plat lpc32xx_uart[] = { { .base = UART3_BASE, .reg_shift = 2, - .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, }, + .clock = CFG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, }, { .base = UART4_BASE, .reg_shift = 2, - .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, }, + .clock = CFG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, }, { .base = UART5_BASE, .reg_shift = 2, - .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, }, + .clock = CFG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, }, { .base = UART6_BASE, .reg_shift = 2, - .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, }, + .clock = CFG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, }, }; -#if defined(CONFIG_LPC32XX_HSUART) -static const struct lpc32xx_hsuart_plat lpc32xx_hsuart[] = { - { HS_UART1_BASE, }, - { HS_UART2_BASE, }, - { HS_UART7_BASE, }, -}; -#endif - U_BOOT_DRVINFOS(lpc32xx_uarts) = { -#if defined(CONFIG_LPC32XX_HSUART) - { "lpc32xx_hsuart", &lpc32xx_hsuart[0], }, - { "lpc32xx_hsuart", &lpc32xx_hsuart[1], }, -#endif { "ns16550_serial", &lpc32xx_uart[0], }, { "ns16550_serial", &lpc32xx_uart[1], }, { "ns16550_serial", &lpc32xx_uart[2], }, { "ns16550_serial", &lpc32xx_uart[3], }, -#if defined(CONFIG_LPC32XX_HSUART) - { "lpc32xx_hsuart", &lpc32xx_hsuart[2], }, -#endif }; #endif diff --git a/arch/arm/mach-mediatek/mt7623/init.c b/arch/arm/mach-mediatek/mt7623/init.c index 5d837e0597..988b057e59 100644 --- a/arch/arm/mach-mediatek/mt7623/init.c +++ b/arch/arm/mach-mediatek/mt7623/init.c @@ -25,7 +25,7 @@ int dram_init(void) { u32 i; - if (((size_t)preloader_param >= CONFIG_SYS_SDRAM_BASE) && + if (((size_t)preloader_param >= CFG_SYS_SDRAM_BASE) && ((size_t)preloader_param % sizeof(size_t) == 0) && preloader_param->magic == BOOT_ARGUMENT_MAGIC && preloader_param->dram_rank_num <= @@ -35,7 +35,7 @@ int dram_init(void) for (i = 0; i < preloader_param->dram_rank_num; i++) gd->ram_size += preloader_param->dram_rank_size[i]; } else { - gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, + gd->ram_size = get_ram_size((long *)CFG_SYS_SDRAM_BASE, SZ_2G); } diff --git a/arch/arm/mach-mediatek/mt7981/init.c b/arch/arm/mach-mediatek/mt7981/init.c index a8955064e0..d8b10f0358 100644 --- a/arch/arm/mach-mediatek/mt7981/init.c +++ b/arch/arm/mach-mediatek/mt7981/init.c @@ -14,7 +14,7 @@ DECLARE_GLOBAL_DATA_PTR; int dram_init(void) { - gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, SZ_2G); + gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, SZ_2G); return 0; } diff --git a/arch/arm/mach-mediatek/mt7986/init.c b/arch/arm/mach-mediatek/mt7986/init.c index cf89e63e80..fb74b2f34d 100644 --- a/arch/arm/mach-mediatek/mt7986/init.c +++ b/arch/arm/mach-mediatek/mt7986/init.c @@ -14,7 +14,7 @@ DECLARE_GLOBAL_DATA_PTR; int dram_init(void) { - gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, SZ_2G); + gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, SZ_2G); return 0; } diff --git a/arch/arm/mach-mvebu/alleycat5/cpu.c b/arch/arm/mach-mvebu/alleycat5/cpu.c index cc7f9794c5..8204d96275 100644 --- a/arch/arm/mach-mvebu/alleycat5/cpu.c +++ b/arch/arm/mach-mvebu/alleycat5/cpu.c @@ -21,8 +21,8 @@ DECLARE_GLOBAL_DATA_PTR; static struct mm_region ac5_mem_map[] = { { /* RAM */ - .phys = CONFIG_SYS_SDRAM_BASE, - .virt = CONFIG_SYS_SDRAM_BASE, + .phys = CFG_SYS_SDRAM_BASE, + .virt = CFG_SYS_SDRAM_BASE, .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_INNER_SHARE }, @@ -102,7 +102,7 @@ int alleycat5_dram_init_banksize(void) /* * Config single DRAM bank */ - gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; gd->bd->bi_dram[0].size = gd->ram_size; return 0; diff --git a/arch/arm/mach-mvebu/arm64-common.c b/arch/arm/mach-mvebu/arm64-common.c index e3098a7ca8..2c94f899f3 100644 --- a/arch/arm/mach-mvebu/arm64-common.c +++ b/arch/arm/mach-mvebu/arm64-common.c @@ -32,7 +32,7 @@ DECLARE_GLOBAL_DATA_PTR; phys_size_t board_get_usable_ram_top(phys_size_t total_size) { - unsigned long top = CONFIG_SYS_SDRAM_BASE + min(gd->ram_size, USABLE_RAM_SIZE); + unsigned long top = CFG_SYS_SDRAM_BASE + min(gd->ram_size, USABLE_RAM_SIZE); return (gd->ram_top > top) ? top : gd->ram_top; } diff --git a/arch/arm/mach-mvebu/armada8k/dram.c b/arch/arm/mach-mvebu/armada8k/dram.c index bab375e18a..6c801bfa1d 100644 --- a/arch/arm/mach-mvebu/armada8k/dram.c +++ b/arch/arm/mach-mvebu/armada8k/dram.c @@ -38,7 +38,7 @@ int a8k_dram_init_banksize(void) */ phys_size_t max_bank0_size = SZ_4G - SZ_1G; - gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; if (gd->ram_size <= max_bank0_size) { gd->bd->bi_dram[0].size = gd->ram_size; return 0; diff --git a/arch/arm/mach-mvebu/cpu.c b/arch/arm/mach-mvebu/cpu.c index 1f8cdf8744..329d13691f 100644 --- a/arch/arm/mach-mvebu/cpu.c +++ b/arch/arm/mach-mvebu/cpu.c @@ -83,7 +83,7 @@ u32 get_boot_device(void) /* * Now check the SAR register for the strapped boot-device */ - val = readl(CONFIG_SAR_REG); /* SAR - Sample At Reset */ + val = readl(CFG_SAR_REG); /* SAR - Sample At Reset */ boot_device = (val & BOOT_DEV_SEL_MASK) >> BOOT_DEV_SEL_OFFS; debug("SAR_REG=0x%08x boot_device=0x%x\n", val, boot_device); switch (boot_device) { @@ -195,9 +195,9 @@ void get_sar_freq(struct sar_freq_modes *sar_freq) int i; #if defined(CONFIG_ARMADA_375) || defined(CONFIG_ARMADA_MSYS) - val = readl(CONFIG_SAR2_REG); /* SAR - Sample At Reset */ + val = readl(CFG_SAR2_REG); /* SAR - Sample At Reset */ #else - val = readl(CONFIG_SAR_REG); /* SAR - Sample At Reset */ + val = readl(CFG_SAR_REG); /* SAR - Sample At Reset */ #endif freq = (val & SAR_CPU_FREQ_MASK) >> SAR_CPU_FREQ_OFFS; #if defined(SAR2_CPU_FREQ_MASK) @@ -205,7 +205,7 @@ void get_sar_freq(struct sar_freq_modes *sar_freq) * Shift CPU0 clock frequency select bit from SAR2 register * into correct position */ - freq |= ((readl(CONFIG_SAR2_REG) & SAR2_CPU_FREQ_MASK) + freq |= ((readl(CFG_SAR2_REG) & SAR2_CPU_FREQ_MASK) >> SAR2_CPU_FREQ_OFFS) << 3; #endif for (i = 0; sar_freq_tab[i].val != 0xff; i++) { @@ -659,7 +659,7 @@ void enable_caches(void) void v7_outer_cache_enable(void) { struct pl310_regs *const pl310 = - (struct pl310_regs *)CONFIG_SYS_PL310_BASE; + (struct pl310_regs *)CFG_SYS_PL310_BASE; /* The L2 cache is already disabled at this point */ @@ -691,7 +691,7 @@ void v7_outer_cache_enable(void) void v7_outer_cache_disable(void) { struct pl310_regs *const pl310 = - (struct pl310_regs *)CONFIG_SYS_PL310_BASE; + (struct pl310_regs *)CFG_SYS_PL310_BASE; clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); } diff --git a/arch/arm/mach-mvebu/include/mach/config.h b/arch/arm/mach-mvebu/include/mach/config.h index 2e06f2bdae..6102747548 100644 --- a/arch/arm/mach-mvebu/include/mach/config.h +++ b/arch/arm/mach-mvebu/include/mach/config.h @@ -27,16 +27,4 @@ #define MV_UART_CONSOLE_BASE MVEBU_UART0_BASE -/* Needed for SPI NOR booting in SPL */ -#define CONFIG_DM_SEQ_ALIAS 1 - -/* - * I2C related stuff - */ -#ifdef CONFIG_CMD_I2C -#ifndef CONFIG_SYS_I2C_SOFT -#define CONFIG_I2C_MVTWSI -#endif -#endif - #endif /* __MVEBU_CONFIG_H */ diff --git a/arch/arm/mach-mvebu/include/mach/soc.h b/arch/arm/mach-mvebu/include/mach/soc.h index 3b9618852c..6edd2e2d79 100644 --- a/arch/arm/mach-mvebu/include/mach/soc.h +++ b/arch/arm/mach-mvebu/include/mach/soc.h @@ -54,7 +54,7 @@ #define MVEBU_SDRAM_SCRATCH (MVEBU_REGISTER(0x01504)) #define MVEBU_L2_CACHE_BASE (MVEBU_REGISTER(0x08000)) -#define CONFIG_SYS_PL310_BASE MVEBU_L2_CACHE_BASE +#define CFG_SYS_PL310_BASE MVEBU_L2_CACHE_BASE #define MVEBU_TWSI_BASE (MVEBU_REGISTER(0x11000)) #define MVEBU_TWSI1_BASE (MVEBU_REGISTER(0x11100)) #define MVEBU_MPP_BASE (MVEBU_REGISTER(0x18000)) @@ -134,8 +134,8 @@ #if defined(CONFIG_ARMADA_375) /* SAR values for Armada 375 */ -#define CONFIG_SAR_REG (MVEBU_REGISTER(0xe8200)) -#define CONFIG_SAR2_REG (MVEBU_REGISTER(0xe8204)) +#define CFG_SAR_REG (MVEBU_REGISTER(0xe8200)) +#define CFG_SAR2_REG (MVEBU_REGISTER(0xe8204)) #define SAR_CPU_FREQ_OFFS 17 #define SAR_CPU_FREQ_MASK (0x1f << SAR_CPU_FREQ_OFFS) @@ -146,11 +146,11 @@ #define BOOT_FROM_UART 0x30 #define BOOT_FROM_SPI 0x38 -#define CONFIG_SYS_TCLK ((readl(CONFIG_SAR_REG) & BIT(20)) ? \ +#define CFG_SYS_TCLK ((readl(CFG_SAR_REG) & BIT(20)) ? \ 200000000 : 166000000) #elif defined(CONFIG_ARMADA_38X) /* SAR values for Armada 38x */ -#define CONFIG_SAR_REG (MVEBU_REGISTER(0x18600)) +#define CFG_SAR_REG (MVEBU_REGISTER(0x18600)) #define SAR_CPU_FREQ_OFFS 10 #define SAR_CPU_FREQ_MASK (0x1f << SAR_CPU_FREQ_OFFS) @@ -169,12 +169,12 @@ #define BOOT_FROM_MMC 0x30 #define BOOT_FROM_MMC_ALT 0x31 -#define CONFIG_SYS_TCLK ((readl(CONFIG_SAR_REG) & BIT(15)) ? \ +#define CFG_SYS_TCLK ((readl(CFG_SAR_REG) & BIT(15)) ? \ 200000000 : 250000000) #elif defined(CONFIG_ARMADA_MSYS) /* SAR values for MSYS */ -#define CONFIG_SAR_REG (MBUS_DFX_BASE + 0xf8200) -#define CONFIG_SAR2_REG (MBUS_DFX_BASE + 0xf8204) +#define CFG_SAR_REG (MBUS_DFX_BASE + 0xf8200) +#define CFG_SAR2_REG (MBUS_DFX_BASE + 0xf8204) #define SAR_CPU_FREQ_OFFS 18 #define SAR_CPU_FREQ_MASK (0x7 << SAR_CPU_FREQ_OFFS) @@ -188,11 +188,11 @@ #define BOOT_FROM_UART 0x2 #define BOOT_FROM_SPI 0x3 -#define CONFIG_SYS_TCLK 200000000 /* 200MHz */ +#define CFG_SYS_TCLK 200000000 /* 200MHz */ #elif defined(CONFIG_ARMADA_XP) /* SAR values for Armada XP */ -#define CONFIG_SAR_REG (MVEBU_REGISTER(0x18230)) -#define CONFIG_SAR2_REG (MVEBU_REGISTER(0x18234)) +#define CFG_SAR_REG (MVEBU_REGISTER(0x18230)) +#define CFG_SAR2_REG (MVEBU_REGISTER(0x18234)) #define SAR_CPU_FREQ_OFFS 21 #define SAR_CPU_FREQ_MASK (0x7 << SAR_CPU_FREQ_OFFS) @@ -209,7 +209,7 @@ #define BOOT_FROM_UART 0x2 #define BOOT_FROM_SPI 0x3 -#define CONFIG_SYS_TCLK 250000000 /* 250MHz */ +#define CFG_SYS_TCLK 250000000 /* 250MHz */ #endif #endif /* _MVEBU_SOC_H */ diff --git a/arch/arm/mach-mvebu/lowlevel.S b/arch/arm/mach-mvebu/lowlevel.S index 60c2072c35..6c9783aa63 100644 --- a/arch/arm/mach-mvebu/lowlevel.S +++ b/arch/arm/mach-mvebu/lowlevel.S @@ -35,10 +35,10 @@ ENTRY(arch_very_early_init) * Disable L2 cache * * NOTE: Internal registers are still at address INTREG_BASE_ADDR_REG - * but CONFIG_SYS_PL310_BASE is already calculated from base + * but CFG_SYS_PL310_BASE is already calculated from base * address SOC_REGS_PHY_BASE. */ - ldr r1, =(CONFIG_SYS_PL310_BASE - SOC_REGS_PHY_BASE + INTREG_BASE_ADDR_REG) + ldr r1, =(CFG_SYS_PL310_BASE - SOC_REGS_PHY_BASE + INTREG_BASE_ADDR_REG) ldr r0, [r1, #L2X0_CTRL_OFF] bic r0, #L2X0_CTRL_EN str r0, [r1, #L2X0_CTRL_OFF] diff --git a/arch/arm/mach-nexell/Kconfig b/arch/arm/mach-nexell/Kconfig index 86a2398637..16324e1520 100644 --- a/arch/arm/mach-nexell/Kconfig +++ b/arch/arm/mach-nexell/Kconfig @@ -6,8 +6,8 @@ config ARCH_S5P4418 select OF_CONTROL select OF_SEPARATE select NX_GPIO - select PL011_SERIAL - select PL011_SERIAL_FLUSH_ON_INIT + select DM_SERIAL + select PL01X_SERIAL help Enable support for Nexell S5P4418 SoC. diff --git a/arch/arm/mach-nexell/clock.c b/arch/arm/mach-nexell/clock.c index 24fa204ccd..59ffa26255 100644 --- a/arch/arm/mach-nexell/clock.c +++ b/arch/arm/mach-nexell/clock.c @@ -856,7 +856,7 @@ void __init clk_init(void) } /* prevent uart clock disable for low step debug message */ - #ifndef CONFIG_DEBUG_NX_UART + #ifndef CONFIG_DEBUG_UART if (peri->dev_name) { #ifdef CONFIG_BACKLIGHT_PWM if (!strcmp(peri->dev_name, DEV_NAME_PWM)) diff --git a/arch/arm/mach-nexell/include/mach/pwm.h b/arch/arm/mach-nexell/include/mach/pwm.h index 08a287d308..1e12058dd5 100644 --- a/arch/arm/mach-nexell/include/mach/pwm.h +++ b/arch/arm/mach-nexell/include/mach/pwm.h @@ -49,6 +49,11 @@ struct s5p_timer { unsigned int tcnto4; unsigned int tintcstat; }; + +int s5p_pwm_init (int pwm_id, int div, int invert); +int s5p_pwm_config (int pwm_id, int duty_ns, int period_ns); +int s5p_pwm_enable (int pwm_id); +void s5p_pwm_disable (int pwm_id); #endif /* __ASSEMBLY__ */ #endif diff --git a/arch/arm/mach-npcm/npcm7xx/l2_cache_pl310.c b/arch/arm/mach-npcm/npcm7xx/l2_cache_pl310.c index cba2e342dc..ed4b1ca5c9 100644 --- a/arch/arm/mach-npcm/npcm7xx/l2_cache_pl310.c +++ b/arch/arm/mach-npcm/npcm7xx/l2_cache_pl310.c @@ -11,7 +11,7 @@ void l2_pl310_init(void); void set_pl310_ctrl(u32 enable) { - struct pl310_regs *const pl310 = (struct pl310_regs *)CONFIG_SYS_PL310_BASE; + struct pl310_regs *const pl310 = (struct pl310_regs *)CFG_SYS_PL310_BASE; writel(enable, &pl310->pl310_ctrl); } diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig index 78317e474d..1db71df272 100644 --- a/arch/arm/mach-omap2/Kconfig +++ b/arch/arm/mach-omap2/Kconfig @@ -75,14 +75,6 @@ config OMAP54XX imply SPL_SERIAL imply SYS_I2C_OMAP24XX -config TI814X - bool "TI814X SoC" - select SPECIFY_CONSOLE_INDEX - help - Support for AM335x SOC from Texas Instruments. - The AM335x high performance SOC features a Cortex-A8 - ARM core and more. - config TI816X bool "TI816X SoC" select SPECIFY_CONSOLE_INDEX @@ -144,6 +136,9 @@ config SYS_MPUCLK help Defines the MPU clock speed (in MHz). +config SYS_OMAP_ABE_SYSCK + bool + config TI_SECURE_EMIF_REGION_START hex "Reserved EMIF region start address" depends on TI_SECURE_DEVICE diff --git a/arch/arm/mach-omap2/am33xx/Kconfig b/arch/arm/mach-omap2/am33xx/Kconfig index 6c2d46abc4..1299aec055 100644 --- a/arch/arm/mach-omap2/am33xx/Kconfig +++ b/arch/arm/mach-omap2/am33xx/Kconfig @@ -8,16 +8,6 @@ config TARGET_TI816X_EVM endif -if TI814X - -config TARGET_TI814X_EVM - bool "Support ti814x_evm" - help - This option specifies support for the TI8148 - EVM development platform. - -endif - if AM33XX config AM33XX_CHILISOM @@ -230,7 +220,6 @@ config TARGET_AM43XX_EVM bool "Support am43xx_evm" select BOARD_LATE_INIT select TI_I2C_BOARD_DETECT - imply DM_ETH imply DM_I2C imply DM_SPI imply DM_SPI_FLASH diff --git a/arch/arm/mach-omap2/am33xx/Makefile b/arch/arm/mach-omap2/am33xx/Makefile index 4e4f98ea90..bf94d345da 100644 --- a/arch/arm/mach-omap2/am33xx/Makefile +++ b/arch/arm/mach-omap2/am33xx/Makefile @@ -3,7 +3,6 @@ # Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ obj-$(CONFIG_AM33XX) += clock_am33xx.o -obj-$(CONFIG_TI814X) += clock_ti814x.o obj-$(CONFIG_AM43XX) += clock_am43xx.o ifneq ($(CONFIG_AM43XX)$(CONFIG_AM33XX),) diff --git a/arch/arm/mach-omap2/am33xx/board.c b/arch/arm/mach-omap2/am33xx/board.c index f393ff9144..a52d04d85c 100644 --- a/arch/arm/mach-omap2/am33xx/board.c +++ b/arch/arm/mach-omap2/am33xx/board.c @@ -72,14 +72,14 @@ int dram_init(void) /* dram_init must store complete ramsize in gd->ram_size */ gd->ram_size = get_ram_size( - (void *)CONFIG_SYS_SDRAM_BASE, - CONFIG_MAX_RAM_BANK_SIZE); + (void *)CFG_SYS_SDRAM_BASE, + CFG_MAX_RAM_BANK_SIZE); return 0; } int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; gd->bd->bi_dram[0].size = gd->ram_size; return 0; @@ -87,29 +87,29 @@ int dram_init_banksize(void) #if !CONFIG_IS_ENABLED(OF_CONTROL) static const struct ns16550_plat am33xx_serial[] = { - { .base = CONFIG_SYS_NS16550_COM1, .reg_shift = 2, - .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, }, -# ifdef CONFIG_SYS_NS16550_COM2 - { .base = CONFIG_SYS_NS16550_COM2, .reg_shift = 2, - .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, }, -# ifdef CONFIG_SYS_NS16550_COM3 - { .base = CONFIG_SYS_NS16550_COM3, .reg_shift = 2, - .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, }, - { .base = CONFIG_SYS_NS16550_COM4, .reg_shift = 2, - .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, }, - { .base = CONFIG_SYS_NS16550_COM5, .reg_shift = 2, - .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, }, - { .base = CONFIG_SYS_NS16550_COM6, .reg_shift = 2, - .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, }, + { .base = CFG_SYS_NS16550_COM1, .reg_shift = 2, + .clock = CFG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, }, +# ifdef CFG_SYS_NS16550_COM2 + { .base = CFG_SYS_NS16550_COM2, .reg_shift = 2, + .clock = CFG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, }, +# ifdef CFG_SYS_NS16550_COM3 + { .base = CFG_SYS_NS16550_COM3, .reg_shift = 2, + .clock = CFG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, }, + { .base = CFG_SYS_NS16550_COM4, .reg_shift = 2, + .clock = CFG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, }, + { .base = CFG_SYS_NS16550_COM5, .reg_shift = 2, + .clock = CFG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, }, + { .base = CFG_SYS_NS16550_COM6, .reg_shift = 2, + .clock = CFG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, }, # endif # endif }; U_BOOT_DRVINFOS(am33xx_uarts) = { { "ns16550_serial", &am33xx_serial[0] }, -# ifdef CONFIG_SYS_NS16550_COM2 +# ifdef CFG_SYS_NS16550_COM2 { "ns16550_serial", &am33xx_serial[1] }, -# ifdef CONFIG_SYS_NS16550_COM3 +# ifdef CFG_SYS_NS16550_COM3 { "ns16550_serial", &am33xx_serial[2] }, { "ns16550_serial", &am33xx_serial[3] }, { "ns16550_serial", &am33xx_serial[4] }, @@ -520,8 +520,8 @@ void board_init_f(ulong dummy) sdram_init(); /* dram_init must store complete ramsize in gd->ram_size */ gd->ram_size = get_ram_size( - (void *)CONFIG_SYS_SDRAM_BASE, - CONFIG_MAX_RAM_BANK_SIZE); + (void *)CFG_SYS_SDRAM_BASE, + CFG_MAX_RAM_BANK_SIZE); } #endif diff --git a/arch/arm/mach-omap2/am33xx/clock_ti814x.c b/arch/arm/mach-omap2/am33xx/clock_ti814x.c deleted file mode 100644 index 27abaff48f..0000000000 --- a/arch/arm/mach-omap2/am33xx/clock_ti814x.c +++ /dev/null @@ -1,410 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * clock_ti814x.c - * - * Clocks for TI814X based boards - * - * Copyright (C) 2013, Texas Instruments, Incorporated - */ - -#include <common.h> -#include <asm/arch/cpu.h> -#include <asm/arch/clock.h> -#include <asm/arch/hardware.h> -#include <asm/io.h> -#include <linux/delay.h> - -/* PRCM */ -#define PRCM_MOD_EN 0x2 - -/* CLK_SRC */ -#define OSC_SRC0 0 -#define OSC_SRC1 1 - -#define L3_OSC_SRC OSC_SRC0 - -#define OSC_0_FREQ 20 - -#define DCO_HS2_MIN 500 -#define DCO_HS2_MAX 1000 -#define DCO_HS1_MIN 1000 -#define DCO_HS1_MAX 2000 - -#define SELFREQDCO_HS2 0x00000801 -#define SELFREQDCO_HS1 0x00001001 - -#define MPU_N 0x1 -#define MPU_M 0x3C -#define MPU_M2 1 -#define MPU_CLKCTRL 0x1 - -#define L3_N 19 -#define L3_M 880 -#define L3_M2 4 -#define L3_CLKCTRL 0x801 - -#define DDR_N 19 -#define DDR_M 666 -#define DDR_M2 2 -#define DDR_CLKCTRL 0x801 - -/* ADPLLJ register values */ -#define ADPLLJ_CLKCTRL_HS2 0x00000801 /* HS2 mode, TINT2 = 1 */ -#define ADPLLJ_CLKCTRL_HS1 0x00001001 /* HS1 mode, TINT2 = 1 */ -#define ADPLLJ_CLKCTRL_CLKDCOLDOEN (1 << 29) -#define ADPLLJ_CLKCTRL_IDLE (1 << 23) -#define ADPLLJ_CLKCTRL_CLKOUTEN (1 << 20) -#define ADPLLJ_CLKCTRL_CLKOUTLDOEN (1 << 19) -#define ADPLLJ_CLKCTRL_CLKDCOLDOPWDNZ (1 << 17) -#define ADPLLJ_CLKCTRL_LPMODE (1 << 12) -#define ADPLLJ_CLKCTRL_DRIFTGUARDIAN (1 << 11) -#define ADPLLJ_CLKCTRL_REGM4XEN (1 << 10) -#define ADPLLJ_CLKCTRL_TINITZ (1 << 0) -#define ADPLLJ_CLKCTRL_CLKDCO (ADPLLJ_CLKCTRL_CLKDCOLDOEN | \ - ADPLLJ_CLKCTRL_CLKOUTEN | \ - ADPLLJ_CLKCTRL_CLKOUTLDOEN | \ - ADPLLJ_CLKCTRL_CLKDCOLDOPWDNZ) - -#define ADPLLJ_STATUS_PHASELOCK (1 << 10) -#define ADPLLJ_STATUS_FREQLOCK (1 << 9) -#define ADPLLJ_STATUS_PHSFRQLOCK (ADPLLJ_STATUS_PHASELOCK | \ - ADPLLJ_STATUS_FREQLOCK) -#define ADPLLJ_STATUS_BYPASSACK (1 << 8) -#define ADPLLJ_STATUS_BYPASS (1 << 0) -#define ADPLLJ_STATUS_BYPASSANDACK (ADPLLJ_STATUS_BYPASSACK | \ - ADPLLJ_STATUS_BYPASS) - -#define ADPLLJ_TENABLE_ENB (1 << 0) -#define ADPLLJ_TENABLEDIV_ENB (1 << 0) - -#define ADPLLJ_M2NDIV_M2SHIFT 16 - -#define MPU_PLL_BASE (PLL_SUBSYS_BASE + 0x048) -#define L3_PLL_BASE (PLL_SUBSYS_BASE + 0x110) -#define DDR_PLL_BASE (PLL_SUBSYS_BASE + 0x290) - -struct ad_pll { - unsigned int pwrctrl; - unsigned int clkctrl; - unsigned int tenable; - unsigned int tenablediv; - unsigned int m2ndiv; - unsigned int mn2div; - unsigned int fracdiv; - unsigned int bwctrl; - unsigned int fracctrl; - unsigned int status; - unsigned int m3div; - unsigned int rampctrl; -}; - -#define OSC_SRC_CTRL (PLL_SUBSYS_BASE + 0x2C0) - -#define ENET_CLKCTRL_CMPL 0x30000 - -#define SATA_PLL_BASE (CTRL_BASE + 0x0720) - -struct sata_pll { - unsigned int pllcfg0; - unsigned int pllcfg1; - unsigned int pllcfg2; - unsigned int pllcfg3; - unsigned int pllcfg4; - unsigned int pllstatus; - unsigned int rxstatus; - unsigned int txstatus; - unsigned int testcfg; -}; - -#define SEL_IN_FREQ (0x1 << 31) -#define DIGCLRZ (0x1 << 30) -#define ENDIGLDO (0x1 << 4) -#define APLL_CP_CURR (0x1 << 3) -#define ENBGSC_REF (0x1 << 2) -#define ENPLLLDO (0x1 << 1) -#define ENPLL (0x1 << 0) - -#define SATA_PLLCFG0_1 (SEL_IN_FREQ | ENBGSC_REF) -#define SATA_PLLCFG0_2 (SEL_IN_FREQ | ENDIGLDO | ENBGSC_REF) -#define SATA_PLLCFG0_3 (SEL_IN_FREQ | ENDIGLDO | ENBGSC_REF | ENPLLLDO) -#define SATA_PLLCFG0_4 (SEL_IN_FREQ | DIGCLRZ | ENDIGLDO | ENBGSC_REF | \ - ENPLLLDO | ENPLL) - -#define PLL_LOCK (0x1 << 0) - -#define ENSATAMODE (0x1 << 31) -#define PLLREFSEL (0x1 << 30) -#define MDIVINT (0x4b << 18) -#define EN_CLKAUX (0x1 << 5) -#define EN_CLK125M (0x1 << 4) -#define EN_CLK100M (0x1 << 3) -#define EN_CLK50M (0x1 << 2) - -#define SATA_PLLCFG1 (ENSATAMODE | \ - PLLREFSEL | \ - MDIVINT | \ - EN_CLKAUX | \ - EN_CLK125M | \ - EN_CLK100M | \ - EN_CLK50M) - -#define DIGLDO_EN_CAPLESSMODE (0x1 << 22) -#define PLLDO_EN_LDO_STABLE (0x1 << 11) -#define PLLDO_EN_BUF_CUR (0x1 << 7) -#define PLLDO_EN_LP (0x1 << 6) -#define PLLDO_CTRL_TRIM_1_4V (0x10 << 1) - -#define SATA_PLLCFG3 (DIGLDO_EN_CAPLESSMODE | \ - PLLDO_EN_LDO_STABLE | \ - PLLDO_EN_BUF_CUR | \ - PLLDO_EN_LP | \ - PLLDO_CTRL_TRIM_1_4V) - -const struct cm_alwon *cmalwon = (struct cm_alwon *)CM_ALWON_BASE; -const struct cm_def *cmdef = (struct cm_def *)CM_DEFAULT_BASE; -const struct sata_pll *spll = (struct sata_pll *)SATA_PLL_BASE; - -/* - * Enable the peripheral clock for required peripherals - */ -static void enable_per_clocks(void) -{ - /* HSMMC1 */ - writel(PRCM_MOD_EN, &cmalwon->mmchs1clkctrl); - while (readl(&cmalwon->mmchs1clkctrl) != PRCM_MOD_EN) - ; - - /* Ethernet */ - writel(PRCM_MOD_EN, &cmalwon->ethclkstctrl); - writel(PRCM_MOD_EN, &cmalwon->ethernet0clkctrl); - while ((readl(&cmalwon->ethernet0clkctrl) & ENET_CLKCTRL_CMPL) != 0) - ; - writel(PRCM_MOD_EN, &cmalwon->ethernet1clkctrl); - while ((readl(&cmalwon->ethernet1clkctrl) & ENET_CLKCTRL_CMPL) != 0) - ; - - /* RTC clocks */ - writel(PRCM_MOD_EN, &cmalwon->rtcclkstctrl); - writel(PRCM_MOD_EN, &cmalwon->rtcclkctrl); - while (readl(&cmalwon->rtcclkctrl) != PRCM_MOD_EN) - ; -} - -/* - * select the HS1 or HS2 for DCO Freq - * return : CLKCTRL - */ -static u32 pll_dco_freq_sel(u32 clkout_dco) -{ - if (clkout_dco >= DCO_HS2_MIN && clkout_dco < DCO_HS2_MAX) - return SELFREQDCO_HS2; - else if (clkout_dco >= DCO_HS1_MIN && clkout_dco < DCO_HS1_MAX) - return SELFREQDCO_HS1; - else - return -1; -} - -/* - * select the sigma delta config - * return: sigma delta val - */ -static u32 pll_sigma_delta_val(u32 clkout_dco) -{ - u32 sig_val = 0; - - sig_val = (clkout_dco + 225) / 250; - sig_val = sig_val << 24; - - return sig_val; -} - -/* - * configure individual ADPLLJ - */ -static void pll_config(u32 base, u32 n, u32 m, u32 m2, - u32 clkctrl_val, int adpllj) -{ - const struct ad_pll *adpll = (struct ad_pll *)base; - u32 m2nval, mn2val, read_clkctrl = 0, clkout_dco = 0; - u32 sig_val = 0, hs_mod = 0; - - m2nval = (m2 << ADPLLJ_M2NDIV_M2SHIFT) | n; - mn2val = m; - - /* calculate clkout_dco */ - clkout_dco = ((OSC_0_FREQ / (n+1)) * m); - - /* sigma delta & Hs mode selection skip for ADPLLS*/ - if (adpllj) { - sig_val = pll_sigma_delta_val(clkout_dco); - hs_mod = pll_dco_freq_sel(clkout_dco); - } - - /* by-pass pll */ - read_clkctrl = readl(&adpll->clkctrl); - writel((read_clkctrl | ADPLLJ_CLKCTRL_IDLE), &adpll->clkctrl); - while ((readl(&adpll->status) & ADPLLJ_STATUS_BYPASSANDACK) - != ADPLLJ_STATUS_BYPASSANDACK) - ; - - /* clear TINITZ */ - read_clkctrl = readl(&adpll->clkctrl); - writel((read_clkctrl & ~ADPLLJ_CLKCTRL_TINITZ), &adpll->clkctrl); - - /* - * ref_clk = 20/(n + 1); - * clkout_dco = ref_clk * m; - * clk_out = clkout_dco/m2; - */ - read_clkctrl = readl(&adpll->clkctrl) & - ~(ADPLLJ_CLKCTRL_LPMODE | - ADPLLJ_CLKCTRL_DRIFTGUARDIAN | - ADPLLJ_CLKCTRL_REGM4XEN); - writel(m2nval, &adpll->m2ndiv); - writel(mn2val, &adpll->mn2div); - - /* Skip for modena(ADPLLS) */ - if (adpllj) { - writel(sig_val, &adpll->fracdiv); - writel((read_clkctrl | hs_mod), &adpll->clkctrl); - } - - /* Load M2, N2 dividers of ADPLL */ - writel(ADPLLJ_TENABLEDIV_ENB, &adpll->tenablediv); - writel(~ADPLLJ_TENABLEDIV_ENB, &adpll->tenablediv); - - /* Load M, N dividers of ADPLL */ - writel(ADPLLJ_TENABLE_ENB, &adpll->tenable); - writel(~ADPLLJ_TENABLE_ENB, &adpll->tenable); - - /* Configure CLKDCOLDOEN,CLKOUTLDOEN,CLKOUT Enable BITS */ - read_clkctrl = readl(&adpll->clkctrl) & ~ADPLLJ_CLKCTRL_CLKDCO; - if (adpllj) - writel((read_clkctrl | ADPLLJ_CLKCTRL_CLKDCO), - &adpll->clkctrl); - - /* Enable TINTZ and disable IDLE(PLL in Active & Locked Mode */ - read_clkctrl = readl(&adpll->clkctrl) & ~ADPLLJ_CLKCTRL_IDLE; - writel((read_clkctrl | ADPLLJ_CLKCTRL_TINITZ), &adpll->clkctrl); - - /* Wait for phase and freq lock */ - while ((readl(&adpll->status) & ADPLLJ_STATUS_PHSFRQLOCK) != - ADPLLJ_STATUS_PHSFRQLOCK) - ; -} - -static void unlock_pll_control_mmr(void) -{ - /* TRM 2.10.1.4 and 3.2.7-3.2.11 */ - writel(0x1EDA4C3D, 0x481C5040); - writel(0x2FF1AC2B, 0x48140060); - writel(0xF757FDC0, 0x48140064); - writel(0xE2BC3A6D, 0x48140068); - writel(0x1EBF131D, 0x4814006c); - writel(0x6F361E05, 0x48140070); -} - -static void mpu_pll_config(void) -{ - pll_config(MPU_PLL_BASE, MPU_N, MPU_M, MPU_M2, MPU_CLKCTRL, 0); -} - -static void l3_pll_config(void) -{ - u32 l3_osc_src, rd_osc_src = 0; - - l3_osc_src = L3_OSC_SRC; - rd_osc_src = readl(OSC_SRC_CTRL); - - if (OSC_SRC0 == l3_osc_src) - writel((rd_osc_src & 0xfffffffe)|0x0, OSC_SRC_CTRL); - else - writel((rd_osc_src & 0xfffffffe)|0x1, OSC_SRC_CTRL); - - pll_config(L3_PLL_BASE, L3_N, L3_M, L3_M2, L3_CLKCTRL, 1); -} - -void ddr_pll_config(unsigned int ddrpll_m) -{ - pll_config(DDR_PLL_BASE, DDR_N, DDR_M, DDR_M2, DDR_CLKCTRL, 1); -} - -void sata_pll_config(void) -{ - /* - * This sequence for configuring the SATA PLL - * resident in the control module is documented - * in TI8148 TRM section 21.3.1 - */ - writel(SATA_PLLCFG1, &spll->pllcfg1); - udelay(50); - - writel(SATA_PLLCFG3, &spll->pllcfg3); - udelay(50); - - writel(SATA_PLLCFG0_1, &spll->pllcfg0); - udelay(50); - - writel(SATA_PLLCFG0_2, &spll->pllcfg0); - udelay(50); - - writel(SATA_PLLCFG0_3, &spll->pllcfg0); - udelay(50); - - writel(SATA_PLLCFG0_4, &spll->pllcfg0); - udelay(50); - - while (((readl(&spll->pllstatus) & PLL_LOCK) == 0)) - ; -} - -void enable_dmm_clocks(void) -{ - writel(PRCM_MOD_EN, &cmdef->fwclkctrl); - writel(PRCM_MOD_EN, &cmdef->l3fastclkstctrl); - writel(PRCM_MOD_EN, &cmdef->emif0clkctrl); - while ((readl(&cmdef->emif0clkctrl)) != PRCM_MOD_EN) - ; - writel(PRCM_MOD_EN, &cmdef->emif1clkctrl); - while ((readl(&cmdef->emif1clkctrl)) != PRCM_MOD_EN) - ; - while ((readl(&cmdef->l3fastclkstctrl) & 0x300) != 0x300) - ; - writel(PRCM_MOD_EN, &cmdef->dmmclkctrl); - while ((readl(&cmdef->dmmclkctrl)) != PRCM_MOD_EN) - ; - writel(PRCM_MOD_EN, &cmalwon->l3slowclkstctrl); - while ((readl(&cmalwon->l3slowclkstctrl) & 0x2100) != 0x2100) - ; -} - -void setup_clocks_for_console(void) -{ - unlock_pll_control_mmr(); - /* UART0 */ - writel(PRCM_MOD_EN, &cmalwon->uart0clkctrl); - while (readl(&cmalwon->uart0clkctrl) != PRCM_MOD_EN) - ; -} - -void setup_early_clocks(void) -{ - setup_clocks_for_console(); -} - -/* - * Configure the PLL/PRCM for necessary peripherals - */ -void prcm_init(void) -{ - /* Enable the control module */ - writel(PRCM_MOD_EN, &cmalwon->controlclkctrl); - - /* Configure PLLs */ - mpu_pll_config(); - l3_pll_config(); - sata_pll_config(); - - /* Enable the required peripherals */ - enable_per_clocks(); -} diff --git a/arch/arm/mach-omap2/am33xx/emif4.c b/arch/arm/mach-omap2/am33xx/emif4.c index a5fdb0433d..bf3da43ed9 100644 --- a/arch/arm/mach-omap2/am33xx/emif4.c +++ b/arch/arm/mach-omap2/am33xx/emif4.c @@ -28,26 +28,6 @@ static struct cm_device_inst *cm_device = (struct cm_device_inst *)CM_DEVICE_INST; #endif -#ifdef CONFIG_TI814X -void config_dmm(const struct dmm_lisa_map_regs *regs) -{ - struct dmm_lisa_map_regs *hw_lisa_map_regs = - (struct dmm_lisa_map_regs *)DMM_BASE; - - enable_dmm_clocks(); - - writel(0, &hw_lisa_map_regs->dmm_lisa_map_3); - writel(0, &hw_lisa_map_regs->dmm_lisa_map_2); - writel(0, &hw_lisa_map_regs->dmm_lisa_map_1); - writel(0, &hw_lisa_map_regs->dmm_lisa_map_0); - - writel(regs->dmm_lisa_map_3, &hw_lisa_map_regs->dmm_lisa_map_3); - writel(regs->dmm_lisa_map_2, &hw_lisa_map_regs->dmm_lisa_map_2); - writel(regs->dmm_lisa_map_1, &hw_lisa_map_regs->dmm_lisa_map_1); - writel(regs->dmm_lisa_map_0, &hw_lisa_map_regs->dmm_lisa_map_0); -} -#endif - static void config_vtp(int nr) { writel(readl(&vtpreg[nr]->vtp0ctrlreg) | VTP_CTRL_ENABLE, diff --git a/arch/arm/mach-omap2/boot-common.c b/arch/arm/mach-omap2/boot-common.c index c463c96c74..d104f23b3e 100644 --- a/arch/arm/mach-omap2/boot-common.c +++ b/arch/arm/mach-omap2/boot-common.c @@ -15,6 +15,7 @@ #include <spl.h> #include <asm/global_data.h> #include <asm/omap_common.h> +#include <asm/omap_sec_common.h> #include <asm/arch/omap.h> #include <asm/arch/mmc_host_def.h> #include <asm/arch/sys_proto.h> @@ -22,6 +23,7 @@ #include <scsi.h> #include <i2c.h> #include <remoteproc.h> +#include <image.h> DECLARE_GLOBAL_DATA_PTR; @@ -181,7 +183,7 @@ void save_omap_boot_params(void) gd->arch.omap_boot_mode = boot_mode; -#if !defined(CONFIG_TI814X) && !defined(CONFIG_TI816X) && \ +#if !defined(CONFIG_TI816X) && \ !defined(CONFIG_AM33XX) && !defined(CONFIG_AM43XX) /* CH flags */ @@ -331,3 +333,17 @@ void arch_preboot_os(void) ahci_reset((void __iomem *)DWC_AHSATA_BASE); } #endif + +#ifdef CONFIG_TI_SECURE_DEVICE +void board_fit_image_post_process(const void *fit, int node, void **p_image, + size_t *p_size) +{ + secure_boot_verify_image(p_image, p_size); +} + +static void tee_image_process(ulong tee_image, size_t tee_size) +{ + secure_tee_install((u32)tee_image); +} +U_BOOT_FIT_LOADABLE_HANDLER(IH_TYPE_TEE, tee_image_process); +#endif diff --git a/arch/arm/mach-omap2/config_secure.mk b/arch/arm/mach-omap2/config_secure.mk index f76262bb0c..24ddcdb961 100644 --- a/arch/arm/mach-omap2/config_secure.mk +++ b/arch/arm/mach-omap2/config_secure.mk @@ -102,7 +102,7 @@ u-boot_HS_XIP_X-LOADER: $(obj)/u-boot.bin FORCE ifdef CONFIG_SPL_LOAD_FIT MKIMAGEFLAGS_u-boot_HS.img = -f auto -A $(ARCH) -T firmware -C none -O u-boot \ - -a $(CONFIG_TEXT_BASE) -e $(CONFIG_SYS_UBOOT_START) \ + -a $(CONFIG_TEXT_BASE) -e $(CFG_SYS_UBOOT_START) \ -n "U-Boot $(UBOOTRELEASE) for $(BOARD) board" -E \ $(patsubst %,-b arch/$(ARCH)/dts/%.dtb_HS,$(subst ",,$(CONFIG_OF_LIST))) diff --git a/arch/arm/mach-omap2/emif-common.c b/arch/arm/mach-omap2/emif-common.c index 312f868fbc..a6a97af37d 100644 --- a/arch/arm/mach-omap2/emif-common.c +++ b/arch/arm/mach-omap2/emif-common.c @@ -389,7 +389,7 @@ static void dra7_enable_ecc(u32 base, const struct emif_regs *regs) /* Set region1 memory with 0 */ rgn_start = (regs->emif_ecc_address_range_1 & EMIF_ECC_REG_ECC_START_ADDR_MASK) << 16; - rgn = rgn_start + CONFIG_SYS_SDRAM_BASE; + rgn = rgn_start + CFG_SYS_SDRAM_BASE; size = (regs->emif_ecc_address_range_1 & EMIF_ECC_REG_ECC_END_ADDR_MASK) + 0x10000 - rgn_start; @@ -400,7 +400,7 @@ static void dra7_enable_ecc(u32 base, const struct emif_regs *regs) /* Set region2 memory with 0 */ rgn_start = (regs->emif_ecc_address_range_2 & EMIF_ECC_REG_ECC_START_ADDR_MASK) << 16; - rgn = rgn_start + CONFIG_SYS_SDRAM_BASE; + rgn = rgn_start + CFG_SYS_SDRAM_BASE; size = (regs->emif_ecc_address_range_2 & EMIF_ECC_REG_ECC_END_ADDR_MASK) + 0x10000 - rgn_start; @@ -1340,7 +1340,7 @@ void dmm_init(u32 base) mapped_size = 0; section_cnt = 3; - sys_addr = CONFIG_SYS_SDRAM_BASE; + sys_addr = CFG_SYS_SDRAM_BASE; emif1_size = get_emif_mem_size(EMIF1_BASE); emif2_size = get_emif_mem_size(EMIF2_BASE); debug("emif1_size 0x%x emif2_size 0x%x\n", emif1_size, emif2_size); @@ -1568,7 +1568,7 @@ void sdram_init(void) size_prog = log_2_n_round_down(size_prog); size_prog = (1 << size_prog); - size_detect = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, + size_detect = get_ram_size((long *)CFG_SYS_SDRAM_BASE, size_prog); /* Compare with the size programmed */ if (size_detect != size_prog) { diff --git a/arch/arm/mach-omap2/mem-common.c b/arch/arm/mach-omap2/mem-common.c index 2dcf0cf9c3..19197482aa 100644 --- a/arch/arm/mach-omap2/mem-common.c +++ b/arch/arm/mach-omap2/mem-common.c @@ -124,25 +124,25 @@ void set_gpmc_cs0(int flash_type) #if defined(CONFIG_NOR) case MTD_DEV_TYPE_NOR: gpmc_regs = gpmc_regs_nor; - base = CONFIG_SYS_FLASH_BASE; - size = (CONFIG_SYS_FLASH_SIZE > 0x08000000) ? GPMC_SIZE_256M : - ((CONFIG_SYS_FLASH_SIZE > 0x04000000) ? GPMC_SIZE_128M : - ((CONFIG_SYS_FLASH_SIZE > 0x02000000) ? GPMC_SIZE_64M : - ((CONFIG_SYS_FLASH_SIZE > 0x01000000) ? GPMC_SIZE_32M : + base = CFG_SYS_FLASH_BASE; + size = (CFG_SYS_FLASH_SIZE > 0x08000000) ? GPMC_SIZE_256M : + ((CFG_SYS_FLASH_SIZE > 0x04000000) ? GPMC_SIZE_128M : + ((CFG_SYS_FLASH_SIZE > 0x02000000) ? GPMC_SIZE_64M : + ((CFG_SYS_FLASH_SIZE > 0x01000000) ? GPMC_SIZE_32M : GPMC_SIZE_16M))); break; #endif #if defined(CONFIG_MTD_RAW_NAND) || defined(CONFIG_CMD_NAND) case MTD_DEV_TYPE_NAND: gpmc_regs = gpmc_regs_nand; - base = CONFIG_SYS_NAND_BASE; + base = CFG_SYS_NAND_BASE; size = GPMC_SIZE_16M; break; #endif #if defined(CONFIG_CMD_ONENAND) case MTD_DEV_TYPE_ONENAND: gpmc_regs = gpmc_regs_onenand; - base = CONFIG_SYS_ONENAND_BASE; + base = CFG_SYS_ONENAND_BASE; size = GPMC_SIZE_128M; break; #endif diff --git a/arch/arm/mach-omap2/omap5/Kconfig b/arch/arm/mach-omap2/omap5/Kconfig index 4c2f990b28..0787d192b6 100644 --- a/arch/arm/mach-omap2/omap5/Kconfig +++ b/arch/arm/mach-omap2/omap5/Kconfig @@ -1,7 +1,12 @@ if OMAP54XX +config IODELAY_RECALIBRATION + bool + config DRA7XX bool + select IODELAY_RECALIBRATION + select SYS_OMAP_ABE_SYSCK help DRA7xx is an OMAP based SOC with Dual Core A-15s. diff --git a/arch/arm/mach-omap2/sec-common.c b/arch/arm/mach-omap2/sec-common.c index 0551bc125e..64560b21e3 100644 --- a/arch/arm/mach-omap2/sec-common.c +++ b/arch/arm/mach-omap2/sec-common.c @@ -198,12 +198,12 @@ u32 get_sec_mem_start(void) */ if (sec_mem_start == 0) sec_mem_start = - (CONFIG_SYS_SDRAM_BASE + ( + (CFG_SYS_SDRAM_BASE + ( #if defined(CONFIG_OMAP54XX) omap_sdram_size() #else - get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, - CONFIG_MAX_RAM_BANK_SIZE) + get_ram_size((void *)CFG_SYS_SDRAM_BASE, + CFG_MAX_RAM_BANK_SIZE) #endif - sec_mem_size)); return sec_mem_start; diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c index 00d91c1013..71fdf5bf48 100644 --- a/arch/arm/mach-omap2/timer.c +++ b/arch/arm/mach-omap2/timer.c @@ -27,7 +27,7 @@ DECLARE_GLOBAL_DATA_PTR; -static struct gptimer *timer_base = (struct gptimer *)CONFIG_SYS_TIMERBASE; +static struct gptimer *timer_base = (struct gptimer *)CFG_SYS_TIMERBASE; static ulong get_timer_masked(void); /* diff --git a/arch/arm/mach-orion5x/dram.c b/arch/arm/mach-orion5x/dram.c index c9a3750e48..5647f847d7 100644 --- a/arch/arm/mach-orion5x/dram.c +++ b/arch/arm/mach-orion5x/dram.c @@ -39,7 +39,7 @@ int dram_init (void) /* dram_init must store complete ramsize in gd->ram_size */ gd->ram_size = get_ram_size( (long *) orion5x_sdram_bar(0), - CONFIG_MAX_RAM_BANK_SIZE); + CFG_MAX_RAM_BANK_SIZE); return 0; } @@ -51,7 +51,7 @@ int dram_init_banksize(void) gd->bd->bi_dram[i].start = orion5x_sdram_bar(i); gd->bd->bi_dram[i].size = get_ram_size( (long *) (gd->bd->bi_dram[i].start), - CONFIG_MAX_RAM_BANK_SIZE); + CFG_MAX_RAM_BANK_SIZE); } return 0; diff --git a/arch/arm/mach-orion5x/include/mach/mv88f5182.h b/arch/arm/mach-orion5x/include/mach/mv88f5182.h index 0e9fe0dc51..ee0aa94bf2 100644 --- a/arch/arm/mach-orion5x/include/mach/mv88f5182.h +++ b/arch/arm/mach-orion5x/include/mach/mv88f5182.h @@ -18,6 +18,6 @@ #define ORION5X_REGS_PHY_BASE F88F5182_REGS_PHYS_BASE /* TCLK Core Clock defination */ -#define CONFIG_SYS_TCLK 166000000 /* 166MHz */ +#define CFG_SYS_TCLK 166000000 /* 166MHz */ #endif /* _CONFIG_88F5182_H */ diff --git a/arch/arm/mach-orion5x/include/mach/orion5x.h b/arch/arm/mach-orion5x/include/mach/orion5x.h index 4b1b0b0f37..e41d07e18c 100644 --- a/arch/arm/mach-orion5x/include/mach/orion5x.h +++ b/arch/arm/mach-orion5x/include/mach/orion5x.h @@ -53,7 +53,7 @@ #define MVCPU_WIN_ENABLE ORION5X_WIN_ENABLE #define MVCPU_WIN_DISABLE ORION5X_WIN_DISABLE -#define CONFIG_MAX_RAM_BANK_SIZE (64*1024*1024) +#define CFG_MAX_RAM_BANK_SIZE (64*1024*1024) /* include here SoC variants. 5181, 5281, 6183 should go here when adding support for them, and this comment should then be updated. */ diff --git a/arch/arm/mach-orion5x/timer.c b/arch/arm/mach-orion5x/timer.c index d7ea2e3943..b373e59e6f 100644 --- a/arch/arm/mach-orion5x/timer.c +++ b/arch/arm/mach-orion5x/timer.c @@ -74,7 +74,7 @@ struct orion5x_tmr_registers *orion5x_tmr_regs = static inline ulong read_timer(void) { return readl(CNTMR_VAL_REG(UBOOT_CNTR)) - / (CONFIG_SYS_TCLK / 1000); + / (CFG_SYS_TCLK / 1000); } DECLARE_GLOBAL_DATA_PTR; @@ -92,7 +92,7 @@ static ulong get_timer_masked(void) } else { /* we have an overflow ... */ timestamp += lastdec + - (TIMER_LOAD_VAL / (CONFIG_SYS_TCLK / 1000)) - now; + (TIMER_LOAD_VAL / (CFG_SYS_TCLK / 1000)) - now; } lastdec = now; @@ -115,7 +115,7 @@ void __udelay(unsigned long usec) ulong delayticks; current = uboot_cntr_val(); - delayticks = (usec * (CONFIG_SYS_TCLK / 1000000)); + delayticks = (usec * (CFG_SYS_TCLK / 1000000)); if (current < delayticks) { delayticks -= current; diff --git a/arch/arm/mach-owl/soc.c b/arch/arm/mach-owl/soc.c index 4baef2eed3..f0f46f2dcb 100644 --- a/arch/arm/mach-owl/soc.c +++ b/arch/arm/mach-owl/soc.c @@ -50,7 +50,7 @@ int dram_init(void) /* This is called after dram_init() so use get_ram_size result */ int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; gd->bd->bi_dram[0].size = gd->ram_size; return 0; diff --git a/arch/arm/mach-rmobile/Kconfig.32 b/arch/arm/mach-rmobile/Kconfig.32 index a07eff71df..31badc5a47 100644 --- a/arch/arm/mach-rmobile/Kconfig.32 +++ b/arch/arm/mach-rmobile/Kconfig.32 @@ -8,6 +8,7 @@ config RCAR_GEN2 bool "Renesas RCar Gen2" select PHY select PHY_RCAR_GEN2 + select TMU_TIMER config R8A7740 bool "Renesas SoC R8A7740" @@ -121,6 +122,9 @@ config TARGET_STOUT endchoice +config TMU_TIMER + bool + config SYS_SOC default "rmobile" diff --git a/arch/arm/mach-rmobile/include/mach/r8a7790.h b/arch/arm/mach-rmobile/include/mach/r8a7790.h index ef74d59fed..485ea7e28d 100644 --- a/arch/arm/mach-rmobile/include/mach/r8a7790.h +++ b/arch/arm/mach-rmobile/include/mach/r8a7790.h @@ -24,10 +24,7 @@ #define MSTP11_BITS 0x00000000 /* SDHI */ -#define CONFIG_SYS_SH_SDHI1_BASE 0xEE120000 -#define CONFIG_SYS_SH_SDHI2_BASE 0xEE140000 -#define CONFIG_SYS_SH_SDHI3_BASE 0xEE160000 -#define CONFIG_SYS_SH_SDHI_NR_CHANNEL 4 +#define CFG_SYS_SH_SDHI_NR_CHANNEL 4 #define R8A7790_CUT_ES2X 2 #define IS_R8A7790_ES2() \ diff --git a/arch/arm/mach-rmobile/include/mach/r8a7791.h b/arch/arm/mach-rmobile/include/mach/r8a7791.h index 681d1ea524..2006ad58a5 100644 --- a/arch/arm/mach-rmobile/include/mach/r8a7791.h +++ b/arch/arm/mach-rmobile/include/mach/r8a7791.h @@ -14,9 +14,7 @@ */ /* SDHI */ -#define CONFIG_SYS_SH_SDHI1_BASE 0xEE140000 -#define CONFIG_SYS_SH_SDHI2_BASE 0xEE160000 -#define CONFIG_SYS_SH_SDHI_NR_CHANNEL 3 +#define CFG_SYS_SH_SDHI_NR_CHANNEL 3 #define DBSC3_1_QOS_R0_BASE 0xE67A1000 #define DBSC3_1_QOS_R1_BASE 0xE67A1100 diff --git a/arch/arm/mach-rmobile/include/mach/r8a7792.h b/arch/arm/mach-rmobile/include/mach/r8a7792.h index 06db64af6c..cc1b00db33 100644 --- a/arch/arm/mach-rmobile/include/mach/r8a7792.h +++ b/arch/arm/mach-rmobile/include/mach/r8a7792.h @@ -24,6 +24,6 @@ #define MSTP11_BITS 0x00000008 /* SDHI */ -#define CONFIG_SYS_SH_SDHI_NR_CHANNEL 1 +#define CFG_SYS_SH_SDHI_NR_CHANNEL 1 #endif /* __ASM_ARCH_R8A7792_H */ diff --git a/arch/arm/mach-rmobile/include/mach/r8a7793.h b/arch/arm/mach-rmobile/include/mach/r8a7793.h index 31433c3693..02f4286ef1 100644 --- a/arch/arm/mach-rmobile/include/mach/r8a7793.h +++ b/arch/arm/mach-rmobile/include/mach/r8a7793.h @@ -15,9 +15,7 @@ */ /* SDHI */ -#define CONFIG_SYS_SH_SDHI1_BASE 0xEE140000 -#define CONFIG_SYS_SH_SDHI2_BASE 0xEE160000 -#define CONFIG_SYS_SH_SDHI_NR_CHANNEL 3 +#define CFG_SYS_SH_SDHI_NR_CHANNEL 3 #define DBSC3_1_QOS_R0_BASE 0xE67A1000 #define DBSC3_1_QOS_R1_BASE 0xE67A1100 diff --git a/arch/arm/mach-rmobile/include/mach/r8a7794.h b/arch/arm/mach-rmobile/include/mach/r8a7794.h index 3baa4237c2..a2a949d4d6 100644 --- a/arch/arm/mach-rmobile/include/mach/r8a7794.h +++ b/arch/arm/mach-rmobile/include/mach/r8a7794.h @@ -24,9 +24,7 @@ #define MSTP11_BITS 0x000001C0 /* SDHI */ -#define CONFIG_SYS_SH_SDHI1_BASE 0xEE140000 -#define CONFIG_SYS_SH_SDHI2_BASE 0xEE160000 -#define CONFIG_SYS_SH_SDHI_NR_CHANNEL 3 +#define CFG_SYS_SH_SDHI_NR_CHANNEL 3 #define R8A7794_CUT_ES2 2 #define IS_R8A7794_ES2() \ diff --git a/arch/arm/mach-rmobile/include/mach/rcar-base.h b/arch/arm/mach-rmobile/include/mach/rcar-base.h index 4c98dffa07..e422e9100a 100644 --- a/arch/arm/mach-rmobile/include/mach/rcar-base.h +++ b/arch/arm/mach-rmobile/include/mach/rcar-base.h @@ -70,15 +70,6 @@ #define SMSTPCR10 0xE6150998 #define SMSTPCR11 0xE615099C -/* RCAR-I2C */ -#define CONFIG_SYS_RCAR_I2C0_BASE 0xE6508000 -#define CONFIG_SYS_RCAR_I2C1_BASE 0xE6518000 -#define CONFIG_SYS_RCAR_I2C2_BASE 0xE6530000 -#define CONFIG_SYS_RCAR_I2C3_BASE 0xE6540000 - -/* SDHI */ -#define CONFIG_SYS_SH_SDHI0_BASE 0xEE100000 - #define S3C_BASE 0xE6784000 #define S3C_INT_BASE 0xE6784A00 #define S3C_MEDIA_BASE 0xE6784B00 diff --git a/arch/arm/mach-rmobile/timer.c b/arch/arm/mach-rmobile/timer.c index ba06535e4c..293c23b5e2 100644 --- a/arch/arm/mach-rmobile/timer.c +++ b/arch/arm/mach-rmobile/timer.c @@ -40,8 +40,8 @@ static u64 get_time_us(void) { u64 timer = get_cpu_global_timer(); - timer = ((timer << 2) + (CLK2MHZ(CONFIG_SYS_CPU_CLK) >> 1)); - do_div(timer, CLK2MHZ(CONFIG_SYS_CPU_CLK)); + timer = ((timer << 2) + (CLK2MHZ(CFG_SYS_CPU_CLK) >> 1)); + do_div(timer, CLK2MHZ(CFG_SYS_CPU_CLK)); return timer; } @@ -65,7 +65,7 @@ void __udelay(unsigned long usec) u64 wait; start = get_cpu_global_timer(); - wait = (u64)((usec * CLK2MHZ(CONFIG_SYS_CPU_CLK)) >> 2); + wait = (u64)((usec * CLK2MHZ(CFG_SYS_CPU_CLK)) >> 2); do { current = get_cpu_global_timer(); } while ((current - start) < wait); @@ -83,5 +83,5 @@ unsigned long long get_ticks(void) ulong get_tbclk(void) { - return (ulong)(CONFIG_SYS_CPU_CLK >> 2); + return (ulong)(CFG_SYS_CPU_CLK >> 2); } diff --git a/arch/arm/mach-rockchip/rk3288/Kconfig b/arch/arm/mach-rockchip/rk3288/Kconfig index 1be2b58521..ea94ad1142 100644 --- a/arch/arm/mach-rockchip/rk3288/Kconfig +++ b/arch/arm/mach-rockchip/rk3288/Kconfig @@ -168,9 +168,6 @@ config SPL_LIBGENERIC_SUPPORT config SPL_SERIAL default y -config TPL_LDSCRIPT - default "arch/arm/mach-rockchip/u-boot-tpl.lds" - config TPL_STACK default 0xff718000 diff --git a/arch/arm/mach-rockchip/sdram.c b/arch/arm/mach-rockchip/sdram.c index 12f1d7ee56..e086c47f3c 100644 --- a/arch/arm/mach-rockchip/sdram.c +++ b/arch/arm/mach-rockchip/sdram.c @@ -37,7 +37,7 @@ struct tos_parameter_t { int dram_init_banksize(void) { - size_t top = min((unsigned long)(gd->ram_size + CONFIG_SYS_SDRAM_BASE), + size_t top = min((unsigned long)(gd->ram_size + CFG_SYS_SDRAM_BASE), (unsigned long)(gd->ram_top)); #ifdef CONFIG_ARM64 @@ -48,26 +48,26 @@ int dram_init_banksize(void) #ifdef CONFIG_SPL_OPTEE_IMAGE struct tos_parameter_t *tos_parameter; - tos_parameter = (struct tos_parameter_t *)(CONFIG_SYS_SDRAM_BASE + + tos_parameter = (struct tos_parameter_t *)(CFG_SYS_SDRAM_BASE + TRUST_PARAMETER_OFFSET); if (tos_parameter->tee_mem.flags == 1) { - gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; gd->bd->bi_dram[0].size = tos_parameter->tee_mem.phy_addr - - CONFIG_SYS_SDRAM_BASE; + - CFG_SYS_SDRAM_BASE; gd->bd->bi_dram[1].start = tos_parameter->tee_mem.phy_addr + tos_parameter->tee_mem.size; gd->bd->bi_dram[1].size = top - gd->bd->bi_dram[1].start; } else { - gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; gd->bd->bi_dram[0].size = 0x8400000; /* Reserve 32M for OPTEE with TA */ - gd->bd->bi_dram[1].start = CONFIG_SYS_SDRAM_BASE + gd->bd->bi_dram[1].start = CFG_SYS_SDRAM_BASE + gd->bd->bi_dram[0].size + 0x2000000; gd->bd->bi_dram[1].size = top - gd->bd->bi_dram[1].start; } #else - gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; gd->bd->bi_dram[0].size = top - gd->bd->bi_dram[0].start; #endif #endif @@ -207,7 +207,7 @@ int dram_init(void) phys_size_t board_get_usable_ram_top(phys_size_t total_size) { - unsigned long top = CONFIG_SYS_SDRAM_BASE + SDRAM_MAX_SIZE; + unsigned long top = CFG_SYS_SDRAM_BASE + SDRAM_MAX_SIZE; return (gd->ram_top > top) ? top : gd->ram_top; } diff --git a/arch/arm/mach-rockchip/u-boot-tpl.lds b/arch/arm/mach-rockchip/u-boot-tpl.lds deleted file mode 100644 index f5a89721ce..0000000000 --- a/arch/arm/mach-rockchip/u-boot-tpl.lds +++ /dev/null @@ -1,12 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2019 Rockchip Electronic Co.,Ltd - */ - -#undef CONFIG_SPL_TEXT_BASE -#define CONFIG_SPL_TEXT_BASE CONFIG_TPL_TEXT_BASE - -#undef CONFIG_SPL_MAX_SIZE -#define CONFIG_SPL_MAX_SIZE CONFIG_TPL_MAX_SIZE - -#include "../cpu/u-boot-spl.lds" diff --git a/arch/arm/mach-s5pc1xx/Kconfig b/arch/arm/mach-s5pc1xx/Kconfig index 8cffced551..b6a4b0b653 100644 --- a/arch/arm/mach-s5pc1xx/Kconfig +++ b/arch/arm/mach-s5pc1xx/Kconfig @@ -9,6 +9,7 @@ config TARGET_S5P_GONI select OF_CONTROL select BLK select DM_MMC + select MISC_COMMON config TARGET_SMDKC100 bool "Support smdkc100 board" diff --git a/arch/arm/mach-s5pc1xx/include/mach/pwm.h b/arch/arm/mach-s5pc1xx/include/mach/pwm.h index 1a531beddc..6d53e52f64 100644 --- a/arch/arm/mach-s5pc1xx/include/mach/pwm.h +++ b/arch/arm/mach-s5pc1xx/include/mach/pwm.h @@ -49,6 +49,11 @@ struct s5p_timer { unsigned int tcnto4; unsigned int tintcstat; }; + +int s5p_pwm_init (int pwm_id, int div, int invert); +int s5p_pwm_config (int pwm_id, int duty_ns, int period_ns); +int s5p_pwm_enable (int pwm_id); +void s5p_pwm_disable (int pwm_id); #endif /* __ASSEMBLY__ */ #endif diff --git a/arch/arm/mach-snapdragon/Kconfig b/arch/arm/mach-snapdragon/Kconfig index 0927333306..914f4d9605 100644 --- a/arch/arm/mach-snapdragon/Kconfig +++ b/arch/arm/mach-snapdragon/Kconfig @@ -55,7 +55,6 @@ config TARGET_DRAGONBOARD845C - 64GiB UFS drive select MISC_INIT_R select SDM845 - select DM_ETH if NET config TARGET_STARQLTECHN bool "Samsung S9 SM-G9600(starqltechn)" @@ -67,7 +66,6 @@ config TARGET_STARQLTECHN - 64GiB UFS drive select MISC_INIT_R select SDM845 - select DM_ETH if NET config TARGET_QCS404EVB bool "Qualcomm Technologies, Inc. QCS404 EVB" diff --git a/arch/arm/mach-socfpga/board.c b/arch/arm/mach-socfpga/board.c index b49006c6c8..09e09192fb 100644 --- a/arch/arm/mach-socfpga/board.c +++ b/arch/arm/mach-socfpga/board.c @@ -46,7 +46,7 @@ void s_init(void) { int board_init(void) { /* Address of boot parameters for ATAG (if ATAG is used) */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; return 0; } diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c index 9c19157de7..5b5a81a255 100644 --- a/arch/arm/mach-socfpga/misc.c +++ b/arch/arm/mach-socfpga/misc.c @@ -34,7 +34,7 @@ phys_addr_t socfpga_sysmgr_base __section(".data"); #ifdef CONFIG_SYS_L2_PL310 static const struct pl310_regs *const pl310 = - (struct pl310_regs *)CONFIG_SYS_PL310_BASE; + (struct pl310_regs *)CFG_SYS_PL310_BASE; #endif struct bsel bsel_str[] = { diff --git a/arch/arm/mach-socfpga/misc_arria10.c b/arch/arm/mach-socfpga/misc_arria10.c index 7ce888d197..93c9e8b0fb 100644 --- a/arch/arm/mach-socfpga/misc_arria10.c +++ b/arch/arm/mach-socfpga/misc_arria10.c @@ -60,7 +60,7 @@ static Altera_desc altera_fpga[] = { #if defined(CONFIG_SPL_BUILD) static struct pl310_regs *const pl310 = - (struct pl310_regs *)CONFIG_SYS_PL310_BASE; + (struct pl310_regs *)CFG_SYS_PL310_BASE; static const struct socfpga_noc_fw_ocram *noc_fw_ocram_base = (void *)SOCFPGA_SDR_FIREWALL_OCRAM_ADDRESS; @@ -256,7 +256,7 @@ void dram_bank_mmu_setup(int bank) /* If we're still in OCRAM, don't set the XN bit on it */ if (!(gd->flags & GD_FLG_RELOC)) { set_section_dcache( - CONFIG_SYS_INIT_RAM_ADDR >> MMU_SECTION_SHIFT, + CFG_SYS_INIT_RAM_ADDR >> MMU_SECTION_SHIFT, DCACHE_WRITETHROUGH); } diff --git a/arch/arm/mach-socfpga/misc_gen5.c b/arch/arm/mach-socfpga/misc_gen5.c index 4edf4f9b5c..e7500c16f7 100644 --- a/arch/arm/mach-socfpga/misc_gen5.c +++ b/arch/arm/mach-socfpga/misc_gen5.c @@ -31,7 +31,7 @@ DECLARE_GLOBAL_DATA_PTR; static struct pl310_regs *const pl310 = - (struct pl310_regs *)CONFIG_SYS_PL310_BASE; + (struct pl310_regs *)CFG_SYS_PL310_BASE; static struct nic301_registers *nic301_regs = (struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS; static struct scu_registers *scu_regs = diff --git a/arch/arm/mach-socfpga/spl_a10.c b/arch/arm/mach-socfpga/spl_a10.c index 2c567edd50..9edbbf4a29 100644 --- a/arch/arm/mach-socfpga/spl_a10.c +++ b/arch/arm/mach-socfpga/spl_a10.c @@ -41,7 +41,7 @@ DECLARE_GLOBAL_DATA_PTR; #define BOOTROM_SHARED_MEM_SIZE 0x800 /* 2KB */ -#define BOOTROM_SHARED_MEM_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ +#define BOOTROM_SHARED_MEM_ADDR (CFG_SYS_INIT_RAM_ADDR + \ SOCFPGA_PHYS_OCRAM_SIZE - \ BOOTROM_SHARED_MEM_SIZE) #define RST_STATUS_SHARED_ADDR (BOOTROM_SHARED_MEM_ADDR + 0x438) diff --git a/arch/arm/mach-socfpga/timer.c b/arch/arm/mach-socfpga/timer.c index a58f1cf9d3..d9e8c84bfc 100644 --- a/arch/arm/mach-socfpga/timer.c +++ b/arch/arm/mach-socfpga/timer.c @@ -10,7 +10,7 @@ #define TIMER_LOAD_VAL 0xFFFFFFFF -static const struct socfpga_timer *timer_base = (void *)CONFIG_SYS_TIMERBASE; +static const struct socfpga_timer *timer_base = (void *)CFG_SYS_TIMERBASE; /* * Timer initialization diff --git a/arch/arm/mach-stm32mp/cmd_stm32prog/cmd_stm32prog.c b/arch/arm/mach-stm32mp/cmd_stm32prog/cmd_stm32prog.c index 007f713130..cb13a14d82 100644 --- a/arch/arm/mach-stm32mp/cmd_stm32prog/cmd_stm32prog.c +++ b/arch/arm/mach-stm32mp/cmd_stm32prog/cmd_stm32prog.c @@ -154,7 +154,7 @@ static int do_stm32prog(struct cmd_tbl *cmdtp, int flag, int argc, do_bootz(cmdtp, 0, 4, bootm_argv); } if (data->script) - image_source_script(data->script, "script@stm32prog"); + image_source_script(data->script, NULL, NULL); if (reset) { puts("Reset...\n"); diff --git a/arch/arm/mach-sunxi/dram_helpers.c b/arch/arm/mach-sunxi/dram_helpers.c index 2c873192e6..cdf2750f1c 100644 --- a/arch/arm/mach-sunxi/dram_helpers.c +++ b/arch/arm/mach-sunxi/dram_helpers.c @@ -33,11 +33,11 @@ void mctl_await_completion(u32 *reg, u32 mask, u32 val) bool mctl_mem_matches(u32 offset) { /* Try to write different values to RAM at two addresses */ - writel(0, CONFIG_SYS_SDRAM_BASE); - writel(0xaa55aa55, (ulong)CONFIG_SYS_SDRAM_BASE + offset); + writel(0, CFG_SYS_SDRAM_BASE); + writel(0xaa55aa55, (ulong)CFG_SYS_SDRAM_BASE + offset); dsb(); /* Check if the same value is actually observed when reading back */ - return readl(CONFIG_SYS_SDRAM_BASE) == - readl((ulong)CONFIG_SYS_SDRAM_BASE + offset); + return readl(CFG_SYS_SDRAM_BASE) == + readl((ulong)CFG_SYS_SDRAM_BASE + offset); } #endif diff --git a/arch/arm/mach-sunxi/dram_suniv.c b/arch/arm/mach-sunxi/dram_suniv.c index 56c2d557ff..3aa3ce7627 100644 --- a/arch/arm/mach-sunxi/dram_suniv.c +++ b/arch/arm/mach-sunxi/dram_suniv.c @@ -175,9 +175,9 @@ static int sdr_readpipe_scan(void) u32 k = 0; for (k = 0; k < 32; k++) - writel(k, CONFIG_SYS_SDRAM_BASE + 4 * k); + writel(k, CFG_SYS_SDRAM_BASE + 4 * k); for (k = 0; k < 32; k++) { - if (readl(CONFIG_SYS_SDRAM_BASE + 4 * k) != k) + if (readl(CFG_SYS_SDRAM_BASE + 4 * k) != k) return 0; } return 1; @@ -266,11 +266,11 @@ static u32 dram_get_dram_size(struct dram_para *para) dram_para_setup(para); dram_scan_readpipe(para); for (i = 0; i < 32; i++) { - *((u8 *)(CONFIG_SYS_SDRAM_BASE + 0x200 + i)) = 0x11; - *((u8 *)(CONFIG_SYS_SDRAM_BASE + 0x600 + i)) = 0x22; + *((u8 *)(CFG_SYS_SDRAM_BASE + 0x200 + i)) = 0x11; + *((u8 *)(CFG_SYS_SDRAM_BASE + 0x600 + i)) = 0x22; } for (i = 0; i < 32; i++) { - val1 = *((u8 *)(CONFIG_SYS_SDRAM_BASE + 0x200 + i)); + val1 = *((u8 *)(CFG_SYS_SDRAM_BASE + 0x200 + i)); if (val1 == 0x22) count++; } @@ -283,11 +283,11 @@ static u32 dram_get_dram_size(struct dram_para *para) para->row_width = rowflag; dram_para_setup(para); if (colflag == 10) { - addr1 = CONFIG_SYS_SDRAM_BASE + 0x400000; - addr2 = CONFIG_SYS_SDRAM_BASE + 0xc00000; + addr1 = CFG_SYS_SDRAM_BASE + 0x400000; + addr2 = CFG_SYS_SDRAM_BASE + 0xc00000; } else { - addr1 = CONFIG_SYS_SDRAM_BASE + 0x200000; - addr2 = CONFIG_SYS_SDRAM_BASE + 0x600000; + addr1 = CFG_SYS_SDRAM_BASE + 0x200000; + addr2 = CFG_SYS_SDRAM_BASE + 0x600000; } for (i = 0; i < 32; i++) { *((u8 *)(addr1 + i)) = 0x33; @@ -319,7 +319,7 @@ static u32 dram_get_dram_size(struct dram_para *para) static void simple_dram_check(void) { - volatile u32 *dram = (u32 *)CONFIG_SYS_SDRAM_BASE; + volatile u32 *dram = (u32 *)CFG_SYS_SDRAM_BASE; int i; for (i = 0; i < 0x40; i++) diff --git a/arch/arm/mach-sunxi/dram_sunxi_dw.c b/arch/arm/mach-sunxi/dram_sunxi_dw.c index 9107b114df..4af5922f33 100644 --- a/arch/arm/mach-sunxi/dram_sunxi_dw.c +++ b/arch/arm/mach-sunxi/dram_sunxi_dw.c @@ -711,7 +711,7 @@ static unsigned long mctl_calc_rank_size(struct rank_para *rank) */ static void mctl_r40_detect_rank_count(struct dram_para *para) { - ulong rank1_base = (ulong) CONFIG_SYS_SDRAM_BASE + + ulong rank1_base = (ulong) CFG_SYS_SDRAM_BASE + mctl_calc_rank_size(¶->ranks[0]); struct sunxi_mctl_ctl_reg * const mctl_ctl = (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; @@ -744,10 +744,10 @@ static void mctl_r40_detect_rank_count(struct dram_para *para) static void mctl_auto_detect_dram_size(uint16_t socid, struct dram_para *para) { - mctl_auto_detect_dram_size_rank(socid, para, (ulong)CONFIG_SYS_SDRAM_BASE, ¶->ranks[0]); + mctl_auto_detect_dram_size_rank(socid, para, (ulong)CFG_SYS_SDRAM_BASE, ¶->ranks[0]); if ((socid == SOCID_A64 || socid == SOCID_R40) && para->dual_rank) { - mctl_auto_detect_dram_size_rank(socid, para, (ulong)CONFIG_SYS_SDRAM_BASE + mctl_calc_rank_size(¶->ranks[0]), ¶->ranks[1]); + mctl_auto_detect_dram_size_rank(socid, para, (ulong)CFG_SYS_SDRAM_BASE + mctl_calc_rank_size(¶->ranks[0]), ¶->ranks[1]); } } diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig index 09ad2d6f5a..1b575cc0f4 100644 --- a/arch/arm/mach-tegra/Kconfig +++ b/arch/arm/mach-tegra/Kconfig @@ -44,7 +44,6 @@ config TEGRA_COMMON select BOARD_EARLY_INIT_F select CLK select DM - select DM_ETH select DM_GPIO select DM_I2C select DM_KEYBOARD @@ -178,6 +177,29 @@ source "arch/arm/mach-tegra/tegra124/Kconfig" source "arch/arm/mach-tegra/tegra210/Kconfig" source "arch/arm/mach-tegra/tegra186/Kconfig" +config TEGRA_SPI + def_bool y + depends on TEGRA20_SFLASH || TEGRA20_SLINK || TEGRA114_SPI + +choice + prompt "UART to use for console" + depends on TEGRA_PINCTRL + default TEGRA_ENABLE_UARTA + +config TEGRA_ENABLE_UARTA + bool "Use UARTA" + +config TEGRA_ENABLE_UARTB + bool "Use UARTB" + +config TEGRA_ENABLE_UARTC + bool "Use UARTC" + +config TEGRA_ENABLE_UARTD + bool "Use UARTD" + +endchoice + config TEGRA_GPU bool "Enable setting up the GPU" depends on TEGRA124 || TEGRA210 diff --git a/arch/arm/mach-tegra/board.c b/arch/arm/mach-tegra/board.c index 95d6555a0d..f8b61a2b3e 100644 --- a/arch/arm/mach-tegra/board.c +++ b/arch/arm/mach-tegra/board.c @@ -259,9 +259,9 @@ void board_init_uart_f(void) #if !CONFIG_IS_ENABLED(OF_CONTROL) static struct ns16550_plat ns16550_com1_pdata = { - .base = CONFIG_SYS_NS16550_COM1, + .base = CFG_SYS_NS16550_COM1, .reg_shift = 2, - .clock = CONFIG_SYS_NS16550_CLK, + .clock = CFG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, }; diff --git a/arch/arm/mach-tegra/board2.c b/arch/arm/mach-tegra/board2.c index 82d3d33502..c7a45f4ff8 100644 --- a/arch/arm/mach-tegra/board2.c +++ b/arch/arm/mach-tegra/board2.c @@ -89,7 +89,7 @@ int checkboard(void) { int board_id = tegra_board_id(); - printf("Board: %s", CONFIG_TEGRA_BOARD_STRING); + printf("Board: %s", CFG_TEGRA_BOARD_STRING); if (board_id != -1) printf(", ID: %d\n", board_id); printf("\n"); @@ -370,7 +370,7 @@ int dram_init_banksize(void) /* fall back to default DRAM bank size computation */ - gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; gd->bd->bi_dram[0].size = usable_ram_size_below_4g(); #ifdef CONFIG_PCI @@ -412,5 +412,5 @@ phys_size_t board_get_usable_ram_top(phys_size_t total_size) /* fall back to default usable RAM computation */ - return CONFIG_SYS_SDRAM_BASE + usable_ram_size_below_4g(); + return CFG_SYS_SDRAM_BASE + usable_ram_size_below_4g(); } diff --git a/arch/arm/mach-tegra/tegra20/Kconfig b/arch/arm/mach-tegra/tegra20/Kconfig index 5c4d35b567..955786c0c4 100644 --- a/arch/arm/mach-tegra/tegra20/Kconfig +++ b/arch/arm/mach-tegra/tegra20/Kconfig @@ -1,5 +1,21 @@ if TEGRA20 +config TEGRA_LP0 + bool + select TEGRA_CLOCK_SCALING + +config TEGRA_PMU + bool + +config TEGRA_CLOCK_SCALING + bool + +config TEGRA_UARTA_GPU + bool + +config TEGRA_UARTA_SDIO1 + bool + choice prompt "Tegra20 board select" optional @@ -23,6 +39,8 @@ config TARGET_PLUTUX config TARGET_SEABOARD bool "NVIDIA Seaboard" select BOARD_LATE_INIT + select TEGRA_LP0 + select TEGRA_PMU config TARGET_TEC bool "Avionic Design Tamonten Evaluation Carrier" @@ -31,6 +49,7 @@ config TARGET_TEC config TARGET_TRIMSLICE bool "Compulab TrimSlice board" select BOARD_LATE_INIT + select TEGRA_UARTA_GPU config TARGET_VENTANA bool "NVIDIA Tegra20 Ventana evaluation board" @@ -39,6 +58,7 @@ config TARGET_VENTANA config TARGET_COLIBRI_T20 bool "Toradex Colibri T20 board" select BOARD_LATE_INIT + select TEGRA_UARTA_SDIO1 endchoice diff --git a/arch/arm/mach-tegra/tegra20/warmboot.c b/arch/arm/mach-tegra/tegra20/warmboot.c index 3d3758f6e6..5e3a9ebace 100644 --- a/arch/arm/mach-tegra/tegra20/warmboot.c +++ b/arch/arm/mach-tegra/tegra20/warmboot.c @@ -23,10 +23,6 @@ DECLARE_GLOBAL_DATA_PTR; -#ifndef CONFIG_TEGRA_CLOCK_SCALING -#error "You must enable CONFIG_TEGRA_CLOCK_SCALING to use CONFIG_TEGRA_LP0" -#endif - /* * This is the place in SRAM where the SDRAM parameters are stored. There * are 4 blocks, one for each RAM code diff --git a/arch/arm/mach-tegra/tegra30/Kconfig b/arch/arm/mach-tegra/tegra30/Kconfig index 85b8ce294f..5619d1cd42 100644 --- a/arch/arm/mach-tegra/tegra30/Kconfig +++ b/arch/arm/mach-tegra/tegra30/Kconfig @@ -1,5 +1,11 @@ if TEGRA30 +config TEGRA_VDD_CORE_TPS62361B_SET3 + bool + +config TEGRA_VDD_CORE_TPS62366A_SET1 + bool + choice prompt "Tegra30 board select" optional @@ -11,10 +17,12 @@ config TARGET_APALIS_T30 config TARGET_BEAVER bool "NVIDIA Tegra30 Beaver evaluation board" select BOARD_LATE_INIT + select TEGRA_VDD_CORE_TPS62366A_SET1 config TARGET_CARDHU bool "NVIDIA Tegra30 Cardhu evaluation board" select BOARD_LATE_INIT + select TEGRA_VDD_CORE_TPS62361B_SET3 config TARGET_COLIBRI_T30 bool "Toradex Colibri T30 board" diff --git a/arch/arm/mach-u8500/cache.c b/arch/arm/mach-u8500/cache.c index f9fd4fe7d3..05a91346a8 100644 --- a/arch/arm/mach-u8500/cache.c +++ b/arch/arm/mach-u8500/cache.c @@ -22,7 +22,7 @@ void enable_caches(void) #ifdef CONFIG_SYS_L2_PL310 void v7_outer_cache_disable(void) { - struct pl310_regs *const pl310 = (struct pl310_regs *)CONFIG_SYS_PL310_BASE; + struct pl310_regs *const pl310 = (struct pl310_regs *)CFG_SYS_PL310_BASE; /* * Linux expects the L2 cache to be turned off by the bootloader. diff --git a/arch/arm/mach-uniphier/Kconfig b/arch/arm/mach-uniphier/Kconfig index 3a8eee7b84..c570fb3294 100644 --- a/arch/arm/mach-uniphier/Kconfig +++ b/arch/arm/mach-uniphier/Kconfig @@ -12,6 +12,7 @@ config ARCH_UNIPHIER_V7_MULTI select ARMV7_NONSEC select CPU_V7A select CPU_V7_HAS_NONSEC + select ARM_GLOBAL_TIMER if TIMER config ARCH_UNIPHIER_V8_MULTI bool "UniPhier V8 SoCs" diff --git a/arch/arm/mach-uniphier/arm32/Makefile b/arch/arm/mach-uniphier/arm32/Makefile index 3cd00b7e5e..b41aba7e29 100644 --- a/arch/arm/mach-uniphier/arm32/Makefile +++ b/arch/arm/mach-uniphier/arm32/Makefile @@ -8,5 +8,3 @@ obj-y += late_lowlevel_init.o obj-y += cache-uniphier.o obj-$(CONFIG_ARMV7_PSCI) += psci.o psci_smp.o endif - -obj-y += timer.o diff --git a/arch/arm/mach-uniphier/arm32/timer.c b/arch/arm/mach-uniphier/arm32/timer.c deleted file mode 100644 index a40bdf1705..0000000000 --- a/arch/arm/mach-uniphier/arm32/timer.c +++ /dev/null @@ -1,39 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2012-2015 Masahiro Yamada <yamada.masahiro@socionext.com> - */ - -#include <config.h> -#include <init.h> -#include <linux/io.h> - -#include "arm-mpcore.h" - -#define PERIPHCLK (50 * 1000 * 1000) /* 50 MHz */ -#define PRESCALER ((PERIPHCLK) / (CONFIG_SYS_TIMER_RATE) - 1) - -static void *get_global_timer_base(void) -{ - void *val; - - asm("mrc p15, 4, %0, c15, c0, 0" : "=r" (val) : : "memory"); - - return val + GLOBAL_TIMER_OFFSET; -} - -unsigned long timer_read_counter(void) -{ - /* - * ARM 64bit Global Timer is too much for our purpose. - * We use only lower 32 bit of the timer counter. - */ - return readl(get_global_timer_base() + GTIMER_CNT_L); -} - -int timer_init(void) -{ - /* enable timer */ - writel(PRESCALER << 8 | 1, get_global_timer_base() + GTIMER_CTRL); - - return 0; -} diff --git a/arch/arm/mach-versatile/timer.c b/arch/arm/mach-versatile/timer.c index 739cb2997a..b471412186 100644 --- a/arch/arm/mach-versatile/timer.c +++ b/arch/arm/mach-versatile/timer.c @@ -36,9 +36,9 @@ int timer_init (void) ulong tmr_ctrl_val; /* 1st disable the Timer */ - tmr_ctrl_val = *(volatile ulong *)(CONFIG_SYS_TIMERBASE + 8); + tmr_ctrl_val = *(volatile ulong *)(CFG_SYS_TIMERBASE + 8); tmr_ctrl_val &= ~TIMER_ENABLE; - *(volatile ulong *)(CONFIG_SYS_TIMERBASE + 8) = tmr_ctrl_val; + *(volatile ulong *)(CFG_SYS_TIMERBASE + 8) = tmr_ctrl_val; /* * The Timer Control Register has one Undefined/Shouldn't Use Bit @@ -52,11 +52,11 @@ int timer_init (void) * Tmr Siz : 16 Bit Counter * Tmr in Wrapping Mode */ - tmr_ctrl_val = *(volatile ulong *)(CONFIG_SYS_TIMERBASE + 8); + tmr_ctrl_val = *(volatile ulong *)(CFG_SYS_TIMERBASE + 8); tmr_ctrl_val &= ~(TIMER_MODE_MSK | TIMER_INT_EN | TIMER_PRS_MSK | TIMER_SIZE_MSK | TIMER_ONE_SHT ); tmr_ctrl_val |= (TIMER_ENABLE | TIMER_PRS_8S); - *(volatile ulong *)(CONFIG_SYS_TIMERBASE + 8) = tmr_ctrl_val; + *(volatile ulong *)(CFG_SYS_TIMERBASE + 8) = tmr_ctrl_val; return 0; } diff --git a/arch/arm/mach-zynq/cpu.c b/arch/arm/mach-zynq/cpu.c index ac595ee0a2..3b6518c71c 100644 --- a/arch/arm/mach-zynq/cpu.c +++ b/arch/arm/mach-zynq/cpu.c @@ -54,7 +54,7 @@ int arch_cpu_init(void) writel(0x757BDF0D, &devcfg_base->unlock); writel(0xFFFFFFFF, &devcfg_base->rom_shadow); -#if (CONFIG_SYS_SDRAM_BASE == 0) +#if (CFG_SYS_SDRAM_BASE == 0) /* remap DDR to zero, FILTERSTART */ writel(0, &scu_base->filter_start); diff --git a/arch/m68k/config.mk b/arch/m68k/config.mk index ed592334af..3ccbe49220 100644 --- a/arch/m68k/config.mk +++ b/arch/m68k/config.mk @@ -3,8 +3,6 @@ # (C) Copyright 2000-2002 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. -CONFIG_STANDALONE_LOAD_ADDR ?= 0x20000 - PLATFORM_CPPFLAGS += -D__M68K__ KBUILD_LDFLAGS += -n PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections diff --git a/arch/m68k/cpu/mcf523x/cpu.c b/arch/m68k/cpu/mcf523x/cpu.c index e44656db5f..ba2c228911 100644 --- a/arch/m68k/cpu/mcf523x/cpu.c +++ b/arch/m68k/cpu/mcf523x/cpu.c @@ -92,7 +92,7 @@ int watchdog_init(void) u32 wdog_module = 0; /* set timeout and enable watchdog */ - wdog_module = ((CONFIG_SYS_CLK / CONFIG_SYS_HZ) * CONFIG_WATCHDOG_TIMEOUT); + wdog_module = ((CFG_SYS_CLK / CONFIG_SYS_HZ) * CONFIG_WATCHDOG_TIMEOUT_MSECS); wdog_module |= (wdog_module / 8192); out_be16(&wdp->mr, wdog_module); diff --git a/arch/m68k/cpu/mcf523x/cpu_init.c b/arch/m68k/cpu/mcf523x/cpu_init.c index 87effa71dc..10be73822f 100644 --- a/arch/m68k/cpu/mcf523x/cpu_init.c +++ b/arch/m68k/cpu/mcf523x/cpu_init.c @@ -47,36 +47,36 @@ void cpu_init_f(void) out_be16(&wdog->cr, 0); #endif - out_be32(&scm->rambar, CONFIG_SYS_INIT_RAM_ADDR | SCM_RAMBAR_BDE); + out_be32(&scm->rambar, CFG_SYS_INIT_RAM_ADDR | SCM_RAMBAR_BDE); /* Port configuration */ out_8(&gpio->par_cs, 0); -#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) && defined(CONFIG_SYS_CS0_CTRL)) - out_be_fbcs_reg(&fbcs->csar0, CONFIG_SYS_CS0_BASE); - out_be_fbcs_reg(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL); - out_be32(&fbcs->csmr0, CONFIG_SYS_CS0_MASK); +#if (defined(CFG_SYS_CS0_BASE) && defined(CFG_SYS_CS0_MASK) && defined(CFG_SYS_CS0_CTRL)) + out_be_fbcs_reg(&fbcs->csar0, CFG_SYS_CS0_BASE); + out_be_fbcs_reg(&fbcs->cscr0, CFG_SYS_CS0_CTRL); + out_be32(&fbcs->csmr0, CFG_SYS_CS0_MASK); #endif -#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) && defined(CONFIG_SYS_CS1_CTRL)) +#if (defined(CFG_SYS_CS1_BASE) && defined(CFG_SYS_CS1_MASK) && defined(CFG_SYS_CS1_CTRL)) setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS1); - out_be_fbcs_reg(&fbcs->csar1, CONFIG_SYS_CS1_BASE); - out_be_fbcs_reg(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL); - out_be32(&fbcs->csmr1, CONFIG_SYS_CS1_MASK); + out_be_fbcs_reg(&fbcs->csar1, CFG_SYS_CS1_BASE); + out_be_fbcs_reg(&fbcs->cscr1, CFG_SYS_CS1_CTRL); + out_be32(&fbcs->csmr1, CFG_SYS_CS1_MASK); #endif -#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) && defined(CONFIG_SYS_CS2_CTRL)) +#if (defined(CFG_SYS_CS2_BASE) && defined(CFG_SYS_CS2_MASK) && defined(CFG_SYS_CS2_CTRL)) setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS2); - out_be_fbcs_reg(&fbcs->csar2, CONFIG_SYS_CS2_BASE); - out_be_fbcs_reg(&fbcs->cscr2, CONFIG_SYS_CS2_CTRL); - out_be32(&fbcs->csmr2, CONFIG_SYS_CS2_MASK); + out_be_fbcs_reg(&fbcs->csar2, CFG_SYS_CS2_BASE); + out_be_fbcs_reg(&fbcs->cscr2, CFG_SYS_CS2_CTRL); + out_be32(&fbcs->csmr2, CFG_SYS_CS2_MASK); #endif -#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) && defined(CONFIG_SYS_CS3_CTRL)) +#if (defined(CFG_SYS_CS3_BASE) && defined(CFG_SYS_CS3_MASK) && defined(CFG_SYS_CS3_CTRL)) setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS3); - out_be_fbcs_reg(&fbcs->csar3, CONFIG_SYS_CS3_BASE); - out_be_fbcs_reg(&fbcs->cscr3, CONFIG_SYS_CS3_CTRL); - out_be32(&fbcs->csmr3, CONFIG_SYS_CS3_MASK); + out_be_fbcs_reg(&fbcs->csar3, CFG_SYS_CS3_BASE); + out_be_fbcs_reg(&fbcs->cscr3, CFG_SYS_CS3_CTRL); + out_be32(&fbcs->csmr3, CFG_SYS_CS3_MASK); #endif #if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) && defined(CONFIG_SYS_CS4_CTRL)) @@ -108,8 +108,8 @@ void cpu_init_f(void) #endif #ifdef CONFIG_SYS_I2C_FSL - CONFIG_SYS_I2C_PINMUX_REG &= CONFIG_SYS_I2C_PINMUX_CLR; - CONFIG_SYS_I2C_PINMUX_REG |= CONFIG_SYS_I2C_PINMUX_SET; + CFG_SYS_I2C_PINMUX_REG &= CFG_SYS_I2C_PINMUX_CLR; + CFG_SYS_I2C_PINMUX_REG |= CFG_SYS_I2C_PINMUX_SET; #endif icache_enable(); diff --git a/arch/m68k/cpu/mcf523x/speed.c b/arch/m68k/cpu/mcf523x/speed.c index f41f977d7f..6b08a12af0 100644 --- a/arch/m68k/cpu/mcf523x/speed.c +++ b/arch/m68k/cpu/mcf523x/speed.c @@ -29,7 +29,7 @@ int get_clocks(void) while (!(in_be32(&pll->synsr) & PLL_SYNSR_LOCK)) ; - gd->bus_clk = CONFIG_SYS_CLK; + gd->bus_clk = CFG_SYS_CLK; gd->cpu_clk = (gd->bus_clk * 2); #ifdef CONFIG_SYS_I2C_FSL diff --git a/arch/m68k/cpu/mcf523x/start.S b/arch/m68k/cpu/mcf523x/start.S index 4c9c96d783..d2a21c3279 100644 --- a/arch/m68k/cpu/mcf523x/start.S +++ b/arch/m68k/cpu/mcf523x/start.S @@ -91,10 +91,10 @@ _start: move.w #0x2700,%sr /* Mask off Interrupt */ /* Set vector base register at the beginning of the Flash */ - move.l #CONFIG_SYS_FLASH_BASE, %d0 + move.l #CFG_SYS_FLASH_BASE, %d0 movec %d0, %VBR - move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0 + move.l #(CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_RAM_CTRL), %d0 movec %d0, %RAMBAR1 /* invalidate and disable cache */ @@ -116,7 +116,7 @@ _start: move.l #__got_start, %a5 /* setup stack initially on top of internal static ram */ - move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE), %sp + move.l #(CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_RAM_SIZE), %sp /* * if configured, malloc_f arena will be reserved first, diff --git a/arch/m68k/cpu/mcf52x2/cpu.c b/arch/m68k/cpu/mcf52x2/cpu.c index 8f72ef567f..d7cbf11e25 100644 --- a/arch/m68k/cpu/mcf52x2/cpu.c +++ b/arch/m68k/cpu/mcf52x2/cpu.c @@ -87,7 +87,7 @@ int watchdog_init(void) /* set timeout and enable watchdog */ out_be16(&wdt->mr, - (CONFIG_WATCHDOG_TIMEOUT * CONFIG_SYS_HZ) / (32768 * 1000) - 1); + (CONFIG_WATCHDOG_TIMEOUT_MSECS * CONFIG_SYS_HZ) / (32768 * 1000) - 1); /* reset watchdog counter */ out_be16(&wdt->sr, 0x5555); @@ -132,11 +132,11 @@ int print_cpuinfo(void) if (cpu_model) printf("CPU: Freescale ColdFire MCF%s rev. %hu, at %s MHz\n", - cpu_model, prn, strmhz(buf, CONFIG_SYS_CLK)); + cpu_model, prn, strmhz(buf, CFG_SYS_CLK)); else printf("CPU: Unknown - Freescale ColdFire MCF5271 family" " (PIN: 0x%x) rev. %hu, at %s MHz\n", - pin, prn, strmhz(buf, CONFIG_SYS_CLK)); + pin, prn, strmhz(buf, CFG_SYS_CLK)); return 0; } @@ -253,7 +253,7 @@ int watchdog_init(void) /* set timeout and enable watchdog */ out_be16(&wdt->wdog_wrrr, - (CONFIG_WATCHDOG_TIMEOUT * CONFIG_SYS_HZ) / (32768 * 1000) - 1); + (CONFIG_WATCHDOG_TIMEOUT_MSECS * CONFIG_SYS_HZ) / (32768 * 1000) - 1); /* reset watchdog counter */ out_be16(&wdt->wdog_wcr, 0); @@ -284,7 +284,7 @@ int print_cpuinfo(void) char buf[32]; printf("CPU: Freescale Coldfire MCF5275 at %s MHz\n", - strmhz(buf, CONFIG_SYS_CLK)); + strmhz(buf, CFG_SYS_CLK)); return 0; }; #endif /* CONFIG_DISPLAY_CPUINFO */ @@ -323,7 +323,7 @@ int watchdog_init(void) /* set timeout and enable watchdog */ out_be16(&wdt->wmr, - (CONFIG_WATCHDOG_TIMEOUT * CONFIG_SYS_HZ) / (32768 * 1000) - 1); + (CONFIG_WATCHDOG_TIMEOUT_MSECS * CONFIG_SYS_HZ) / (32768 * 1000) - 1); /* reset watchdog counter */ out_be16(&wdt->wsr, 0x5555); @@ -370,7 +370,7 @@ int print_cpuinfo(void) char buf[32]; printf("CPU: Freescale Coldfire MCF5249 at %s MHz\n", - strmhz(buf, CONFIG_SYS_CLK)); + strmhz(buf, CFG_SYS_CLK)); return 0; } #endif /* CONFIG_DISPLAY_CPUINFO */ @@ -394,7 +394,7 @@ int print_cpuinfo(void) unsigned char resetsource = mbar_readLong(SIM_RSR); printf("CPU: Freescale Coldfire MCF5253 at %s MHz\n", - strmhz(buf, CONFIG_SYS_CLK)); + strmhz(buf, CFG_SYS_CLK)); if ((resetsource & SIM_RSR_HRST) || (resetsource & SIM_RSR_SWTR)) { printf("Reset:%s%s\n", diff --git a/arch/m68k/cpu/mcf52x2/cpu_init.c b/arch/m68k/cpu/mcf52x2/cpu_init.c index 9d4a10f028..99eb61f167 100644 --- a/arch/m68k/cpu/mcf52x2/cpu_init.c +++ b/arch/m68k/cpu/mcf52x2/cpu_init.c @@ -36,31 +36,31 @@ void init_fbcs(void) { fbcs_t *fbcs = (fbcs_t *) (MMAP_FBCS); -#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) \ - && defined(CONFIG_SYS_CS0_CTRL)) - out_be32(&fbcs->csar0, CONFIG_SYS_CS0_BASE); - out_be32(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL); - out_be32(&fbcs->csmr0, CONFIG_SYS_CS0_MASK); +#if (defined(CFG_SYS_CS0_BASE) && defined(CFG_SYS_CS0_MASK) \ + && defined(CFG_SYS_CS0_CTRL)) + out_be32(&fbcs->csar0, CFG_SYS_CS0_BASE); + out_be32(&fbcs->cscr0, CFG_SYS_CS0_CTRL); + out_be32(&fbcs->csmr0, CFG_SYS_CS0_MASK); #else #warning "Chip Select 0 are not initialized/used" #endif -#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) \ - && defined(CONFIG_SYS_CS1_CTRL)) - out_be32(&fbcs->csar1, CONFIG_SYS_CS1_BASE); - out_be32(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL); - out_be32(&fbcs->csmr1, CONFIG_SYS_CS1_MASK); +#if (defined(CFG_SYS_CS1_BASE) && defined(CFG_SYS_CS1_MASK) \ + && defined(CFG_SYS_CS1_CTRL)) + out_be32(&fbcs->csar1, CFG_SYS_CS1_BASE); + out_be32(&fbcs->cscr1, CFG_SYS_CS1_CTRL); + out_be32(&fbcs->csmr1, CFG_SYS_CS1_MASK); #endif -#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) \ - && defined(CONFIG_SYS_CS2_CTRL)) - out_be32(&fbcs->csar2, CONFIG_SYS_CS2_BASE); - out_be32(&fbcs->cscr2, CONFIG_SYS_CS2_CTRL); - out_be32(&fbcs->csmr2, CONFIG_SYS_CS2_MASK); +#if (defined(CFG_SYS_CS2_BASE) && defined(CFG_SYS_CS2_MASK) \ + && defined(CFG_SYS_CS2_CTRL)) + out_be32(&fbcs->csar2, CFG_SYS_CS2_BASE); + out_be32(&fbcs->cscr2, CFG_SYS_CS2_CTRL); + out_be32(&fbcs->csmr2, CFG_SYS_CS2_MASK); #endif -#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) \ - && defined(CONFIG_SYS_CS3_CTRL)) - out_be32(&fbcs->csar3, CONFIG_SYS_CS3_BASE); - out_be32(&fbcs->cscr3, CONFIG_SYS_CS3_CTRL); - out_be32(&fbcs->csmr3, CONFIG_SYS_CS3_MASK); +#if (defined(CFG_SYS_CS3_BASE) && defined(CFG_SYS_CS3_MASK) \ + && defined(CFG_SYS_CS3_CTRL)) + out_be32(&fbcs->csar3, CFG_SYS_CS3_BASE); + out_be32(&fbcs->cscr3, CFG_SYS_CS3_CTRL); + out_be32(&fbcs->csmr3, CFG_SYS_CS3_MASK); #endif #if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) \ && defined(CONFIG_SYS_CS4_CTRL)) @@ -214,9 +214,9 @@ void cpu_init_f(void) init_fbcs(); #ifdef CONFIG_SYS_I2C_FSL - CONFIG_SYS_I2C_PINMUX_REG = - CONFIG_SYS_I2C_PINMUX_REG & CONFIG_SYS_I2C_PINMUX_CLR; - CONFIG_SYS_I2C_PINMUX_REG |= CONFIG_SYS_I2C_PINMUX_SET; + CFG_SYS_I2C_PINMUX_REG = + CFG_SYS_I2C_PINMUX_REG & CFG_SYS_I2C_PINMUX_CLR; + CFG_SYS_I2C_PINMUX_REG |= CFG_SYS_I2C_PINMUX_SET; #ifdef CONFIG_SYS_I2C2_OFFSET CONFIG_SYS_I2C2_PINMUX_REG &= CONFIG_SYS_I2C2_PINMUX_CLR; CONFIG_SYS_I2C2_PINMUX_REG |= CONFIG_SYS_I2C2_PINMUX_SET; @@ -335,21 +335,21 @@ void cpu_init_f(void) * already initialized. */ #ifndef CONFIG_MONITOR_IS_IN_RAM - sysctrl_t *sysctrl = (sysctrl_t *) (CONFIG_SYS_MBAR); + sysctrl_t *sysctrl = (sysctrl_t *) (CFG_SYS_MBAR); gpio_t *gpio = (gpio_t *) (MMAP_GPIO); csctrl_t *csctrl = (csctrl_t *) (MMAP_FBCS); - out_be16(&sysctrl->sc_scr, CONFIG_SYS_SCR); - out_be16(&sysctrl->sc_spr, CONFIG_SYS_SPR); + out_be16(&sysctrl->sc_scr, CFG_SYS_SCR); + out_be16(&sysctrl->sc_spr, CFG_SYS_SPR); /* Setup Ports: */ - out_be32(&gpio->gpio_pacnt, CONFIG_SYS_PACNT); - out_be16(&gpio->gpio_paddr, CONFIG_SYS_PADDR); - out_be16(&gpio->gpio_padat, CONFIG_SYS_PADAT); - out_be32(&gpio->gpio_pbcnt, CONFIG_SYS_PBCNT); - out_be16(&gpio->gpio_pbddr, CONFIG_SYS_PBDDR); - out_be16(&gpio->gpio_pbdat, CONFIG_SYS_PBDAT); - out_be32(&gpio->gpio_pdcnt, CONFIG_SYS_PDCNT); + out_be32(&gpio->gpio_pacnt, CFG_SYS_PACNT); + out_be16(&gpio->gpio_paddr, CFG_SYS_PADDR); + out_be16(&gpio->gpio_padat, CFG_SYS_PADAT); + out_be32(&gpio->gpio_pbcnt, CFG_SYS_PBCNT); + out_be16(&gpio->gpio_pbddr, CFG_SYS_PBDDR); + out_be16(&gpio->gpio_pbdat, CFG_SYS_PBDAT); + out_be32(&gpio->gpio_pdcnt, CFG_SYS_PDCNT); /* Memory Controller: */ out_be32(&csctrl->cs_br0, CONFIG_SYS_BR0_PRELIM); @@ -472,8 +472,8 @@ void cpu_init_f(void) #endif /* #ifndef CONFIG_MONITOR_IS_IN_RAM */ #ifdef CONFIG_SYS_I2C_FSL - CONFIG_SYS_I2C_PINMUX_REG &= CONFIG_SYS_I2C_PINMUX_CLR; - CONFIG_SYS_I2C_PINMUX_REG |= CONFIG_SYS_I2C_PINMUX_SET; + CFG_SYS_I2C_PINMUX_REG &= CFG_SYS_I2C_PINMUX_CLR; + CFG_SYS_I2C_PINMUX_REG |= CFG_SYS_I2C_PINMUX_SET; #endif /* enable instruction cache now */ @@ -560,8 +560,8 @@ void cpu_init_f(void) #ifndef CONFIG_MONITOR_IS_IN_RAM /* Set speed /PLL */ MCFCLOCK_SYNCR = - MCFCLOCK_SYNCR_MFD(CONFIG_SYS_MFD) | - MCFCLOCK_SYNCR_RFD(CONFIG_SYS_RFD); + MCFCLOCK_SYNCR_MFD(CFG_SYS_MFD) | + MCFCLOCK_SYNCR_RFD(CFG_SYS_RFD); while (!(MCFCLOCK_SYNSR & MCFCLOCK_SYNSR_LOCK)) ; MCFGPIO_PBCDPAR = 0xc0; @@ -573,17 +573,17 @@ void cpu_init_f(void) #ifdef CONFIG_SYS_PFPAR MCFGPIO_PFPAR = CONFIG_SYS_PFPAR; #endif -#ifdef CONFIG_SYS_PJPAR - MCFGPIO_PJPAR = CONFIG_SYS_PJPAR; +#ifdef CFG_SYS_PJPAR + MCFGPIO_PJPAR = CFG_SYS_PJPAR; #endif #ifdef CONFIG_SYS_PSDPAR MCFGPIO_PSDPAR = CONFIG_SYS_PSDPAR; #endif -#ifdef CONFIG_SYS_PASPAR - MCFGPIO_PASPAR = CONFIG_SYS_PASPAR; +#ifdef CFG_SYS_PASPAR + MCFGPIO_PASPAR = CFG_SYS_PASPAR; #endif -#ifdef CONFIG_SYS_PEHLPAR - MCFGPIO_PEHLPAR = CONFIG_SYS_PEHLPAR; +#ifdef CFG_SYS_PEHLPAR + MCFGPIO_PEHLPAR = CFG_SYS_PEHLPAR; #endif #ifdef CONFIG_SYS_PQSPAR MCFGPIO_PQSPAR = CONFIG_SYS_PQSPAR; @@ -600,15 +600,15 @@ void cpu_init_f(void) #ifdef CONFIG_SYS_PTDPAR MCFGPIO_PTDPAR = CONFIG_SYS_PTDPAR; #endif -#ifdef CONFIG_SYS_PUAPAR - MCFGPIO_PUAPAR = CONFIG_SYS_PUAPAR; +#ifdef CFG_SYS_PUAPAR + MCFGPIO_PUAPAR = CFG_SYS_PUAPAR; #endif #if defined(CONFIG_SYS_DDRD) MCFGPIO_DDRD = CONFIG_SYS_DDRD; #endif -#ifdef CONFIG_SYS_DDRUA - MCFGPIO_DDRUA = CONFIG_SYS_DDRUA; +#ifdef CFG_SYS_DDRUA + MCFGPIO_DDRUA = CFG_SYS_DDRUA; #endif /* FlexBus Chipselect */ @@ -652,10 +652,10 @@ int fecpin_setclear(fec_info_t *info, int setclear) { if (setclear) { MCFGPIO_PASPAR |= 0x0F00; - MCFGPIO_PEHLPAR = CONFIG_SYS_PEHLPAR; + MCFGPIO_PEHLPAR = CFG_SYS_PEHLPAR; } else { MCFGPIO_PASPAR &= 0xF0FF; - MCFGPIO_PEHLPAR &= ~CONFIG_SYS_PEHLPAR; + MCFGPIO_PEHLPAR &= ~CFG_SYS_PEHLPAR; } return 0; } @@ -678,12 +678,12 @@ void cpu_init_f(void) * which is their primary function. * ~Jeremy */ - mbar2_writeLong(MCFSIM_GPIO_FUNC, CONFIG_SYS_GPIO_FUNC); - mbar2_writeLong(MCFSIM_GPIO1_FUNC, CONFIG_SYS_GPIO1_FUNC); - mbar2_writeLong(MCFSIM_GPIO_EN, CONFIG_SYS_GPIO_EN); - mbar2_writeLong(MCFSIM_GPIO1_EN, CONFIG_SYS_GPIO1_EN); - mbar2_writeLong(MCFSIM_GPIO_OUT, CONFIG_SYS_GPIO_OUT); - mbar2_writeLong(MCFSIM_GPIO1_OUT, CONFIG_SYS_GPIO1_OUT); + mbar2_writeLong(MCFSIM_GPIO_FUNC, CFG_SYS_GPIO_FUNC); + mbar2_writeLong(MCFSIM_GPIO1_FUNC, CFG_SYS_GPIO1_FUNC); + mbar2_writeLong(MCFSIM_GPIO_EN, CFG_SYS_GPIO_EN); + mbar2_writeLong(MCFSIM_GPIO1_EN, CFG_SYS_GPIO1_EN); + mbar2_writeLong(MCFSIM_GPIO_OUT, CFG_SYS_GPIO_OUT); + mbar2_writeLong(MCFSIM_GPIO1_OUT, CFG_SYS_GPIO1_OUT); /* * dBug Compliance: diff --git a/arch/m68k/cpu/mcf52x2/speed.c b/arch/m68k/cpu/mcf52x2/speed.c index 045908a13d..6c7628252b 100644 --- a/arch/m68k/cpu/mcf52x2/speed.c +++ b/arch/m68k/cpu/mcf52x2/speed.c @@ -23,19 +23,19 @@ int get_clocks(void) #if defined(CONFIG_M5208) pll_t *pll = (pll_t *) MMAP_PLL; - out_8(&pll->odr, CONFIG_SYS_PLL_ODR); - out_8(&pll->fdr, CONFIG_SYS_PLL_FDR); + out_8(&pll->odr, CFG_SYS_PLL_ODR); + out_8(&pll->fdr, CFG_SYS_PLL_FDR); #endif #if defined(CONFIG_M5249) || defined(CONFIG_M5253) volatile unsigned long cpll = mbar2_readLong(MCFSIM_PLLCR); unsigned long pllcr; -#ifndef CONFIG_SYS_PLL_BYPASS +#ifndef CFG_SYS_PLL_BYPASS #ifdef CONFIG_M5249 /* Setup the PLL to run at the specified speed */ -#ifdef CONFIG_SYS_FAST_CLK +#ifdef CFG_SYS_FAST_CLK pllcr = 0x925a3100; /* ~140MHz clock (PLL bypass = 0) */ #else pllcr = 0x135a4140; /* ~72MHz clock (PLL bypass = 0) */ @@ -43,7 +43,7 @@ int get_clocks(void) #endif /* CONFIG_M5249 */ #ifdef CONFIG_M5253 - pllcr = CONFIG_SYS_PLLCR; + pllcr = CFG_SYS_PLLCR; #endif /* CONFIG_M5253 */ cpll = cpll & 0xfffffffe; /* Set PLL bypass mode = 0 (PSTCLK = crystal) */ @@ -52,7 +52,7 @@ int get_clocks(void) pllcr ^= 0x00000001; /* Set pll bypass to 1 */ mbar2_writeLong(MCFSIM_PLLCR, pllcr); /* Start locking (pll bypass = 1) */ udelay(0x20); /* Wait for a lock ... */ -#endif /* #ifndef CONFIG_SYS_PLL_BYPASS */ +#endif /* #ifndef CFG_SYS_PLL_BYPASS */ #endif /* CONFIG_M5249 || CONFIG_M5253 */ @@ -68,7 +68,7 @@ int get_clocks(void) ; #endif - gd->cpu_clk = CONFIG_SYS_CLK; + gd->cpu_clk = CFG_SYS_CLK; #if defined(CONFIG_M5208) || defined(CONFIG_M5249) || defined(CONFIG_M5253) || \ defined(CONFIG_M5271) || defined(CONFIG_M5275) gd->bus_clk = gd->cpu_clk / 2; diff --git a/arch/m68k/cpu/mcf52x2/start.S b/arch/m68k/cpu/mcf52x2/start.S index 6dddbe76f3..d48d0192ee 100644 --- a/arch/m68k/cpu/mcf52x2/start.S +++ b/arch/m68k/cpu/mcf52x2/start.S @@ -35,7 +35,7 @@ */ _vectors: .long 0x00000000 /* Flash offset is 0 until we setup CS0 */ -#if defined(CONFIG_M5282) && (CONFIG_TEXT_BASE == CONFIG_SYS_INT_FLASH_BASE) +#if defined(CONFIG_M5282) && (CONFIG_TEXT_BASE == CFG_SYS_INT_FLASH_BASE) .long _start - CONFIG_TEXT_BASE #else .long _START @@ -81,9 +81,9 @@ _vectors: .text -#if defined(CONFIG_SYS_INT_FLASH_BASE) && \ +#if defined(CFG_SYS_INT_FLASH_BASE) && \ (defined(CONFIG_M5282) || defined(CONFIG_M5281)) -#if (CONFIG_TEXT_BASE == CONFIG_SYS_INT_FLASH_BASE) +#if (CONFIG_TEXT_BASE == CFG_SYS_INT_FLASH_BASE) .long 0x55AA55AA,0xAA55AA55 /* CFM Backdoorkey */ .long 0xFFFFFFFF /* all sectors protected */ .long 0x00000000 /* supervisor/User restriction */ @@ -100,53 +100,53 @@ _start: #if defined(CONFIG_M5208) /* Initialize RAMBAR: locate SRAM and validate it */ - move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0 + move.l #(CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_RAM_CTRL), %d0 movec %d0, %RAMBAR1 #endif #if defined(CONFIG_M5272) || defined(CONFIG_M5249) || defined(CONFIG_M5253) /* set MBAR address + valid flag */ - move.l #(CONFIG_SYS_MBAR + 1), %d0 + move.l #(CFG_SYS_MBAR + 1), %d0 move.c %d0, %MBAR /*** The 5249 has MBAR2 as well ***/ -#ifdef CONFIG_SYS_MBAR2 +#ifdef CFG_SYS_MBAR2 /* Get MBAR2 address */ - move.l #(CONFIG_SYS_MBAR2 + 1), %d0 + move.l #(CFG_SYS_MBAR2 + 1), %d0 /* Set MBAR2 */ movec %d0, #0xc0e #endif - move.l #(CONFIG_SYS_INIT_RAM_ADDR + 1), %d0 + move.l #(CFG_SYS_INIT_RAM_ADDR + 1), %d0 movec %d0, %RAMBAR0 #endif /* CONFIG_M5272 || CONFIG_M5249 || CONFIG_M5253 */ #if defined(CONFIG_M5282) || defined(CONFIG_M5271) /* set MBAR address + valid flag */ - move.l #(CONFIG_SYS_MBAR + 1), %d0 + move.l #(CFG_SYS_MBAR + 1), %d0 move.l %d0, 0x40000000 /* Initialize RAMBAR1: locate SRAM and validate it */ - move.l #(CONFIG_SYS_INIT_RAM_ADDR + 0x21), %d0 + move.l #(CFG_SYS_INIT_RAM_ADDR + 0x21), %d0 movec %d0, %RAMBAR1 #if defined(CONFIG_M5282) -#if (CONFIG_TEXT_BASE == CONFIG_SYS_INT_FLASH_BASE) +#if (CONFIG_TEXT_BASE == CFG_SYS_INT_FLASH_BASE) /* * Setup code in SRAM to initialize FLASHBAR, * if start from internal Flash */ - move.l #(_flashbar_setup-CONFIG_SYS_INT_FLASH_BASE), %a0 - move.l #(_flashbar_setup_end-CONFIG_SYS_INT_FLASH_BASE), %a1 - move.l #(CONFIG_SYS_INIT_RAM_ADDR), %a2 + move.l #(_flashbar_setup-CFG_SYS_INT_FLASH_BASE), %a0 + move.l #(_flashbar_setup_end-CFG_SYS_INT_FLASH_BASE), %a1 + move.l #(CFG_SYS_INIT_RAM_ADDR), %a2 _copy_flash: move.l (%a0)+, (%a2)+ cmp.l %a0, %a1 bgt.s _copy_flash - jmp CONFIG_SYS_INIT_RAM_ADDR + jmp CFG_SYS_INIT_RAM_ADDR _flashbar_setup: /* Initialize FLASHBAR: locate internal Flash and validate it */ - move.l #(CONFIG_SYS_INT_FLASH_BASE + CONFIG_SYS_INT_FLASH_ENABLE), %d0 + move.l #(CFG_SYS_INT_FLASH_BASE + CFG_SYS_INT_FLASH_ENABLE), %d0 movec %d0, %FLASHBAR jmp _after_flashbar_copy.L /* Force jump to absolute address */ _flashbar_setup_end: @@ -154,9 +154,9 @@ _flashbar_setup_end: _after_flashbar_copy: #else /* Setup code to initialize FLASHBAR, if start from external Memory */ - move.l #(CONFIG_SYS_INT_FLASH_BASE + CONFIG_SYS_INT_FLASH_ENABLE), %d0 + move.l #(CFG_SYS_INT_FLASH_BASE + CFG_SYS_INT_FLASH_ENABLE), %d0 movec %d0, %FLASHBAR -#endif /* (CONFIG_TEXT_BASE == CONFIG_SYS_INT_FLASH_BASE) */ +#endif /* (CONFIG_TEXT_BASE == CFG_SYS_INT_FLASH_BASE) */ #endif #endif @@ -165,22 +165,22 @@ _after_flashbar_copy: * therefore no VBR to set */ #if !defined(CONFIG_MONITOR_IS_IN_RAM) -#if defined(CONFIG_M5282) && (CONFIG_TEXT_BASE == CONFIG_SYS_INT_FLASH_BASE) - move.l #CONFIG_SYS_INT_FLASH_BASE, %d0 +#if defined(CONFIG_M5282) && (CONFIG_TEXT_BASE == CFG_SYS_INT_FLASH_BASE) + move.l #CFG_SYS_INT_FLASH_BASE, %d0 #else - move.l #CONFIG_SYS_FLASH_BASE, %d0 + move.l #CFG_SYS_FLASH_BASE, %d0 #endif movec %d0, %VBR #endif #ifdef CONFIG_M5275 /* set MBAR address + valid flag */ - move.l #(CONFIG_SYS_MBAR + 1), %d0 + move.l #(CFG_SYS_MBAR + 1), %d0 move.l %d0, 0x40000000 /* movec %d0, %MBAR */ /* Initialize RAMBAR: locate SRAM and validate it */ - move.l #(CONFIG_SYS_INIT_RAM_ADDR + 0x21), %d0 + move.l #(CFG_SYS_INIT_RAM_ADDR + 0x21), %d0 movec %d0, %RAMBAR1 #endif @@ -195,7 +195,7 @@ _after_flashbar_copy: move.l #__got_start, %a5 /* setup stack initially on top of internal static ram */ - move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE), %sp + move.l #(CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_RAM_SIZE), %sp /* * if configured, malloc_f arena will be reserved first, diff --git a/arch/m68k/cpu/mcf530x/cpu.c b/arch/m68k/cpu/mcf530x/cpu.c index 0659bf6558..53a25d8362 100644 --- a/arch/m68k/cpu/mcf530x/cpu.c +++ b/arch/m68k/cpu/mcf530x/cpu.c @@ -33,7 +33,7 @@ int print_cpuinfo(void) char buf[32]; printf("CPU: Freescale Coldfire MCF5307 at %s MHz\n", - strmhz(buf, CONFIG_SYS_CPU_CLK)); + strmhz(buf, CFG_SYS_CPU_CLK)); return 0; } #endif /* CONFIG_DISPLAY_CPUINFO */ diff --git a/arch/m68k/cpu/mcf530x/cpu_init.c b/arch/m68k/cpu/mcf530x/cpu_init.c index 83529408eb..dad47d87ab 100644 --- a/arch/m68k/cpu/mcf530x/cpu_init.c +++ b/arch/m68k/cpu/mcf530x/cpu_init.c @@ -40,35 +40,35 @@ void init_csm(void) { csm_t *csm = (csm_t *)(MMAP_CSM); -#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) && \ - defined(CONFIG_SYS_CS0_CTRL)) - out_be16(&csm->csar0, CONFIG_SYS_CS0_BASE); - out_be32(&csm->csmr0, CONFIG_SYS_CS0_MASK); - out_be16(&csm->cscr0, CONFIG_SYS_CS0_CTRL); - MCF5307_SP_ERR_FIX(CONFIG_SYS_CS0_BASE, csm->csmr0); +#if (defined(CFG_SYS_CS0_BASE) && defined(CFG_SYS_CS0_MASK) && \ + defined(CFG_SYS_CS0_CTRL)) + out_be16(&csm->csar0, CFG_SYS_CS0_BASE); + out_be32(&csm->csmr0, CFG_SYS_CS0_MASK); + out_be16(&csm->cscr0, CFG_SYS_CS0_CTRL); + MCF5307_SP_ERR_FIX(CFG_SYS_CS0_BASE, csm->csmr0); #else #warning "Chip Select 0 are not initialized/used" #endif -#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) && \ - defined(CONFIG_SYS_CS1_CTRL)) - out_be16(&csm->csar1, CONFIG_SYS_CS1_BASE); - out_be32(&csm->csmr1, CONFIG_SYS_CS1_MASK); - out_be16(&csm->cscr1, CONFIG_SYS_CS1_CTRL); - MCF5307_SP_ERR_FIX(CONFIG_SYS_CS1_BASE, csm->csmr1); +#if (defined(CFG_SYS_CS1_BASE) && defined(CFG_SYS_CS1_MASK) && \ + defined(CFG_SYS_CS1_CTRL)) + out_be16(&csm->csar1, CFG_SYS_CS1_BASE); + out_be32(&csm->csmr1, CFG_SYS_CS1_MASK); + out_be16(&csm->cscr1, CFG_SYS_CS1_CTRL); + MCF5307_SP_ERR_FIX(CFG_SYS_CS1_BASE, csm->csmr1); #endif -#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) && \ - defined(CONFIG_SYS_CS2_CTRL)) - out_be16(&csm->csar2, CONFIG_SYS_CS2_BASE); - out_be32(&csm->csmr2, CONFIG_SYS_CS2_MASK); - out_be16(&csm->cscr2, CONFIG_SYS_CS2_CTRL); - MCF5307_SP_ERR_FIX(CONFIG_SYS_CS2_BASE, csm->csmr2); +#if (defined(CFG_SYS_CS2_BASE) && defined(CFG_SYS_CS2_MASK) && \ + defined(CFG_SYS_CS2_CTRL)) + out_be16(&csm->csar2, CFG_SYS_CS2_BASE); + out_be32(&csm->csmr2, CFG_SYS_CS2_MASK); + out_be16(&csm->cscr2, CFG_SYS_CS2_CTRL); + MCF5307_SP_ERR_FIX(CFG_SYS_CS2_BASE, csm->csmr2); #endif -#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) && \ - defined(CONFIG_SYS_CS3_CTRL)) - out_be16(&csm->csar3, CONFIG_SYS_CS3_BASE); - out_be32(&csm->csmr3, CONFIG_SYS_CS3_MASK); - out_be16(&csm->cscr3, CONFIG_SYS_CS3_CTRL); - MCF5307_SP_ERR_FIX(CONFIG_SYS_CS3_BASE, csm->csmr3); +#if (defined(CFG_SYS_CS3_BASE) && defined(CFG_SYS_CS3_MASK) && \ + defined(CFG_SYS_CS3_CTRL)) + out_be16(&csm->csar3, CFG_SYS_CS3_BASE); + out_be32(&csm->csmr3, CFG_SYS_CS3_MASK); + out_be16(&csm->cscr3, CFG_SYS_CS3_CTRL); + MCF5307_SP_ERR_FIX(CFG_SYS_CS3_BASE, csm->csmr3); #endif #if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) && \ defined(CONFIG_SYS_CS4_CTRL)) diff --git a/arch/m68k/cpu/mcf530x/speed.c b/arch/m68k/cpu/mcf530x/speed.c index 03d9abeb18..c8d079016f 100644 --- a/arch/m68k/cpu/mcf530x/speed.c +++ b/arch/m68k/cpu/mcf530x/speed.c @@ -16,8 +16,8 @@ DECLARE_GLOBAL_DATA_PTR; int get_clocks(void) { #if defined(CONFIG_M5307) - gd->bus_clk = CONFIG_SYS_CLK; - gd->cpu_clk = CONFIG_SYS_CPU_CLK; + gd->bus_clk = CFG_SYS_CLK; + gd->cpu_clk = CFG_SYS_CPU_CLK; #endif return 0; diff --git a/arch/m68k/cpu/mcf530x/start.S b/arch/m68k/cpu/mcf530x/start.S index 644c372bdd..dbe2b54e41 100644 --- a/arch/m68k/cpu/mcf530x/start.S +++ b/arch/m68k/cpu/mcf530x/start.S @@ -39,7 +39,7 @@ _vectors: /* Flash offset is 0 until we setup CS0 */ .long 0x00000000 #if defined(CONFIG_M5307) && \ - (CONFIG_TEXT_BASE == CONFIG_SYS_INT_FLASH_BASE) + (CONFIG_TEXT_BASE == CFG_SYS_INT_FLASH_BASE) .long _start - CONFIG_TEXT_BASE #else .long _START @@ -92,10 +92,10 @@ _start: move.w #0x2700,%sr /* set MBAR address + valid flag */ - move.l #(CONFIG_SYS_MBAR + 1), %d0 + move.l #(CFG_SYS_MBAR + 1), %d0 move.c %d0, %MBAR - move.l #(CONFIG_SYS_INIT_RAM_ADDR + 1), %d0 + move.l #(CFG_SYS_INIT_RAM_ADDR + 1), %d0 move.c %d0, %RAMBAR /* DS 4.8.2 (Cache Organization) invalidate and disable cache */ @@ -110,7 +110,7 @@ _start: * therefore no VBR to set */ #if !defined(CONFIG_MONITOR_IS_IN_RAM) - move.l #CONFIG_SYS_FLASH_BASE, %d0 + move.l #CFG_SYS_FLASH_BASE, %d0 movec %d0, %VBR #endif @@ -125,7 +125,7 @@ _start: move.l #__got_start, %a5 /* setup stack initially on top of internal static ram */ - move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE), %sp + move.l #(CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_RAM_SIZE), %sp /* * if configured, malloc_f arena will be reserved first, diff --git a/arch/m68k/cpu/mcf532x/cpu.c b/arch/m68k/cpu/mcf532x/cpu.c index 1dadffd4ca..548cbca36a 100644 --- a/arch/m68k/cpu/mcf532x/cpu.c +++ b/arch/m68k/cpu/mcf532x/cpu.c @@ -131,7 +131,7 @@ int watchdog_init(void) u32 wdog_module = 0; /* set timeout and enable watchdog */ - wdog_module = ((CONFIG_SYS_CLK / 1000) * CONFIG_WATCHDOG_TIMEOUT); + wdog_module = ((CFG_SYS_CLK / 1000) * CONFIG_WATCHDOG_TIMEOUT_MSECS); #ifdef CONFIG_M5329 out_be16(&wdp->mr, wdog_module / 8192); #else diff --git a/arch/m68k/cpu/mcf532x/cpu_init.c b/arch/m68k/cpu/mcf532x/cpu_init.c index 1311f3967c..844d2cd760 100644 --- a/arch/m68k/cpu/mcf532x/cpu_init.c +++ b/arch/m68k/cpu/mcf532x/cpu_init.c @@ -37,34 +37,34 @@ void cpu_init_f(void) out_be32(&scm1->pacrf, 0); out_be32(&scm1->pacrg, 0); -#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) \ - && defined(CONFIG_SYS_CS0_CTRL)) +#if (defined(CFG_SYS_CS0_BASE) && defined(CFG_SYS_CS0_MASK) \ + && defined(CFG_SYS_CS0_CTRL)) setbits_8(&gpio->par_cs, GPIO_PAR_CS0_CS0); - out_be32(&fbcs->csar0, CONFIG_SYS_CS0_BASE); - out_be32(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL); - out_be32(&fbcs->csmr0, CONFIG_SYS_CS0_MASK); + out_be32(&fbcs->csar0, CFG_SYS_CS0_BASE); + out_be32(&fbcs->cscr0, CFG_SYS_CS0_CTRL); + out_be32(&fbcs->csmr0, CFG_SYS_CS0_MASK); #endif -#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) \ - && defined(CONFIG_SYS_CS1_CTRL)) +#if (defined(CFG_SYS_CS1_BASE) && defined(CFG_SYS_CS1_MASK) \ + && defined(CFG_SYS_CS1_CTRL)) setbits_8(&gpio->par_cs, GPIO_PAR_CS1_CS1); - out_be32(&fbcs->csar1, CONFIG_SYS_CS1_BASE); - out_be32(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL); - out_be32(&fbcs->csmr1, CONFIG_SYS_CS1_MASK); + out_be32(&fbcs->csar1, CFG_SYS_CS1_BASE); + out_be32(&fbcs->cscr1, CFG_SYS_CS1_CTRL); + out_be32(&fbcs->csmr1, CFG_SYS_CS1_MASK); #endif -#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) \ - && defined(CONFIG_SYS_CS2_CTRL)) - out_be32(&fbcs->csar2, CONFIG_SYS_CS2_BASE); - out_be32(&fbcs->cscr2, CONFIG_SYS_CS2_CTRL); - out_be32(&fbcs->csmr2, CONFIG_SYS_CS2_MASK); +#if (defined(CFG_SYS_CS2_BASE) && defined(CFG_SYS_CS2_MASK) \ + && defined(CFG_SYS_CS2_CTRL)) + out_be32(&fbcs->csar2, CFG_SYS_CS2_BASE); + out_be32(&fbcs->cscr2, CFG_SYS_CS2_CTRL); + out_be32(&fbcs->csmr2, CFG_SYS_CS2_MASK); #endif -#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) \ - && defined(CONFIG_SYS_CS3_CTRL)) - out_be32(&fbcs->csar3, CONFIG_SYS_CS3_BASE); - out_be32(&fbcs->cscr3, CONFIG_SYS_CS3_CTRL); - out_be32(&fbcs->csmr3, CONFIG_SYS_CS3_MASK); +#if (defined(CFG_SYS_CS3_BASE) && defined(CFG_SYS_CS3_MASK) \ + && defined(CFG_SYS_CS3_CTRL)) + out_be32(&fbcs->csar3, CFG_SYS_CS3_BASE); + out_be32(&fbcs->cscr3, CFG_SYS_CS3_CTRL); + out_be32(&fbcs->csmr3, CFG_SYS_CS3_MASK); #endif #if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) \ @@ -102,8 +102,8 @@ int cpu_init_r(void) rtc_t *rtc = (rtc_t *) (CONFIG_SYS_MCFRTC_BASE); rtcex_t *rtcex = (rtcex_t *) &rtc->extended; - out_be32(&rtcex->gocu, CONFIG_SYS_RTC_CNT); - out_be32(&rtcex->gocl, CONFIG_SYS_RTC_SETUP); + out_be32(&rtcex->gocu, CFG_SYS_RTC_CNT); + out_be32(&rtcex->gocl, CFG_SYS_RTC_SETUP); #endif #ifdef CONFIG_MCFFEC @@ -236,36 +236,36 @@ void cpu_init_f(void) /* Port configuration */ out_8(&gpio->par_cs, 0); -#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) \ - && defined(CONFIG_SYS_CS0_CTRL)) - out_be32(&fbcs->csar0, CONFIG_SYS_CS0_BASE); - out_be32(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL); - out_be32(&fbcs->csmr0, CONFIG_SYS_CS0_MASK); +#if (defined(CFG_SYS_CS0_BASE) && defined(CFG_SYS_CS0_MASK) \ + && defined(CFG_SYS_CS0_CTRL)) + out_be32(&fbcs->csar0, CFG_SYS_CS0_BASE); + out_be32(&fbcs->cscr0, CFG_SYS_CS0_CTRL); + out_be32(&fbcs->csmr0, CFG_SYS_CS0_MASK); #endif -#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) \ - && defined(CONFIG_SYS_CS1_CTRL)) +#if (defined(CFG_SYS_CS1_BASE) && defined(CFG_SYS_CS1_MASK) \ + && defined(CFG_SYS_CS1_CTRL)) /* Latch chipselect */ setbits_8(&gpio->par_cs, GPIO_PAR_CS1); - out_be32(&fbcs->csar1, CONFIG_SYS_CS1_BASE); - out_be32(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL); - out_be32(&fbcs->csmr1, CONFIG_SYS_CS1_MASK); + out_be32(&fbcs->csar1, CFG_SYS_CS1_BASE); + out_be32(&fbcs->cscr1, CFG_SYS_CS1_CTRL); + out_be32(&fbcs->csmr1, CFG_SYS_CS1_MASK); #endif -#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) \ - && defined(CONFIG_SYS_CS2_CTRL)) +#if (defined(CFG_SYS_CS2_BASE) && defined(CFG_SYS_CS2_MASK) \ + && defined(CFG_SYS_CS2_CTRL)) setbits_8(&gpio->par_cs, GPIO_PAR_CS2); - out_be32(&fbcs->csar2, CONFIG_SYS_CS2_BASE); - out_be32(&fbcs->cscr2, CONFIG_SYS_CS2_CTRL); - out_be32(&fbcs->csmr2, CONFIG_SYS_CS2_MASK); + out_be32(&fbcs->csar2, CFG_SYS_CS2_BASE); + out_be32(&fbcs->cscr2, CFG_SYS_CS2_CTRL); + out_be32(&fbcs->csmr2, CFG_SYS_CS2_MASK); #endif -#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) \ - && defined(CONFIG_SYS_CS3_CTRL)) +#if (defined(CFG_SYS_CS3_BASE) && defined(CFG_SYS_CS3_MASK) \ + && defined(CFG_SYS_CS3_CTRL)) setbits_8(&gpio->par_cs, GPIO_PAR_CS3); - out_be32(&fbcs->csar3, CONFIG_SYS_CS3_BASE); - out_be32(&fbcs->cscr3, CONFIG_SYS_CS3_CTRL); - out_be32(&fbcs->csmr3, CONFIG_SYS_CS3_MASK); + out_be32(&fbcs->csar3, CFG_SYS_CS3_BASE); + out_be32(&fbcs->cscr3, CFG_SYS_CS3_CTRL); + out_be32(&fbcs->csmr3, CFG_SYS_CS3_MASK); #endif #if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) \ @@ -327,7 +327,7 @@ void uart_port_conf(int port) clrbits_8(&gpio->par_feci2c, 0x00ff); setbits_8(&gpio->par_feci2c, GPIO_PAR_FECI2C_SCL_UTXD2 | GPIO_PAR_FECI2C_SDA_URXD2); -#elif defined(CONFIG_SYS_UART2_ALT3_GPIO) +#elif defined(CFG_SYS_UART2_ALT3_GPIO) clrbits_be16(&gpio->par_ssi, 0x0f00); setbits_be16(&gpio->par_ssi, GPIO_PAR_SSI_RXD(2) | GPIO_PAR_SSI_TXD(2)); diff --git a/arch/m68k/cpu/mcf532x/speed.c b/arch/m68k/cpu/mcf532x/speed.c index e2985792d9..32ffac0813 100644 --- a/arch/m68k/cpu/mcf532x/speed.c +++ b/arch/m68k/cpu/mcf532x/speed.c @@ -239,7 +239,7 @@ int clock_pll(int fsys, int flags) * software workaround for SDRAM opeartion after exiting LIMP * mode errata */ - out_be32(sdram_workaround, CONFIG_SYS_SDRAM_BASE); + out_be32(sdram_workaround, CFG_SYS_SDRAM_BASE); #endif /* wait for DQS logic to relock */ @@ -252,7 +252,7 @@ int clock_pll(int fsys, int flags) /* get_clocks() fills in gd->cpu_clock and gd->bus_clk */ int get_clocks(void) { - gd->bus_clk = clock_pll(CONFIG_SYS_CLK / 1000, 0) * 1000; + gd->bus_clk = clock_pll(CFG_SYS_CLK / 1000, 0) * 1000; gd->cpu_clk = (gd->bus_clk * 3); #ifdef CONFIG_SYS_I2C_FSL diff --git a/arch/m68k/cpu/mcf532x/start.S b/arch/m68k/cpu/mcf532x/start.S index 2672891916..72a2f99b7d 100644 --- a/arch/m68k/cpu/mcf532x/start.S +++ b/arch/m68k/cpu/mcf532x/start.S @@ -98,11 +98,11 @@ _start: #if !defined(CONFIG_MONITOR_IS_IN_RAM) /* Set vector base register at the beginning of the Flash */ - move.l #CONFIG_SYS_FLASH_BASE, %d0 + move.l #CFG_SYS_FLASH_BASE, %d0 movec %d0, %VBR #endif - move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0 + move.l #(CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_RAM_CTRL), %d0 movec %d0, %RAMBAR1 /* invalidate and disable cache */ @@ -131,7 +131,7 @@ _start: move.l #__got_start, %a5 /* setup stack initially on top of internal static ram */ - move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE), %sp + move.l #(CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_RAM_SIZE), %sp /* * if configured, malloc_f arena will be reserved first, diff --git a/arch/m68k/cpu/mcf5445x/cpu_init.c b/arch/m68k/cpu/mcf5445x/cpu_init.c index 9b3f9f0fe1..1ce244872f 100644 --- a/arch/m68k/cpu/mcf5445x/cpu_init.c +++ b/arch/m68k/cpu/mcf5445x/cpu_init.c @@ -29,30 +29,30 @@ void init_fbcs(void) fbcs_t *fbcs __maybe_unused = (fbcs_t *) MMAP_FBCS; #if !defined(CONFIG_SERIAL_BOOT) -#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) && defined(CONFIG_SYS_CS0_CTRL)) - out_be32(&fbcs->csar0, CONFIG_SYS_CS0_BASE); - out_be32(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL); - out_be32(&fbcs->csmr0, CONFIG_SYS_CS0_MASK); +#if (defined(CFG_SYS_CS0_BASE) && defined(CFG_SYS_CS0_MASK) && defined(CFG_SYS_CS0_CTRL)) + out_be32(&fbcs->csar0, CFG_SYS_CS0_BASE); + out_be32(&fbcs->cscr0, CFG_SYS_CS0_CTRL); + out_be32(&fbcs->csmr0, CFG_SYS_CS0_MASK); #endif #endif -#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) && defined(CONFIG_SYS_CS1_CTRL)) +#if (defined(CFG_SYS_CS1_BASE) && defined(CFG_SYS_CS1_MASK) && defined(CFG_SYS_CS1_CTRL)) /* Latch chipselect */ - out_be32(&fbcs->csar1, CONFIG_SYS_CS1_BASE); - out_be32(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL); - out_be32(&fbcs->csmr1, CONFIG_SYS_CS1_MASK); + out_be32(&fbcs->csar1, CFG_SYS_CS1_BASE); + out_be32(&fbcs->cscr1, CFG_SYS_CS1_CTRL); + out_be32(&fbcs->csmr1, CFG_SYS_CS1_MASK); #endif -#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) && defined(CONFIG_SYS_CS2_CTRL)) - out_be32(&fbcs->csar2, CONFIG_SYS_CS2_BASE); - out_be32(&fbcs->cscr2, CONFIG_SYS_CS2_CTRL); - out_be32(&fbcs->csmr2, CONFIG_SYS_CS2_MASK); +#if (defined(CFG_SYS_CS2_BASE) && defined(CFG_SYS_CS2_MASK) && defined(CFG_SYS_CS2_CTRL)) + out_be32(&fbcs->csar2, CFG_SYS_CS2_BASE); + out_be32(&fbcs->cscr2, CFG_SYS_CS2_CTRL); + out_be32(&fbcs->csmr2, CFG_SYS_CS2_MASK); #endif -#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) && defined(CONFIG_SYS_CS3_CTRL)) - out_be32(&fbcs->csar3, CONFIG_SYS_CS3_BASE); - out_be32(&fbcs->cscr3, CONFIG_SYS_CS3_CTRL); - out_be32(&fbcs->csmr3, CONFIG_SYS_CS3_MASK); +#if (defined(CFG_SYS_CS3_BASE) && defined(CFG_SYS_CS3_MASK) && defined(CFG_SYS_CS3_CTRL)) + out_be32(&fbcs->csar3, CFG_SYS_CS3_BASE); + out_be32(&fbcs->cscr3, CFG_SYS_CS3_CTRL); + out_be32(&fbcs->csmr3, CFG_SYS_CS3_MASK); #endif #if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) && defined(CONFIG_SYS_CS4_CTRL)) @@ -208,14 +208,14 @@ void cpu_init_f(void) /* FlexBus Chipselect */ init_fbcs(); -#ifdef CONFIG_SYS_CS0_BASE +#ifdef CFG_SYS_CS0_BASE /* * now the flash base address is no longer at 0 (Newer ColdFire family * boot at address 0 instead of 0xFFnn_nnnn). The vector table must * also move to the new location. */ - if (CONFIG_SYS_CS0_BASE != 0) - setvbr(CONFIG_SYS_CS0_BASE); + if (CFG_SYS_CS0_BASE != 0) + setvbr(CFG_SYS_CS0_BASE); #endif icache_enable(); diff --git a/arch/m68k/cpu/mcf5445x/start.S b/arch/m68k/cpu/mcf5445x/start.S index aea8f3090f..a083c3d45d 100644 --- a/arch/m68k/cpu/mcf5445x/start.S +++ b/arch/m68k/cpu/mcf5445x/start.S @@ -27,10 +27,10 @@ #if defined(CONFIG_SERIAL_BOOT) #define ASM_DRAMINIT (asm_dram_init - CONFIG_TEXT_BASE + \ - CONFIG_SYS_INIT_RAM_ADDR) + CFG_SYS_INIT_RAM_ADDR) #define ASM_DRAMINIT_N (asm_dram_init - CONFIG_TEXT_BASE) #define ASM_SBF_IMG_HDR (asm_sbf_img_hdr - CONFIG_TEXT_BASE + \ - CONFIG_SYS_INIT_RAM_ADDR) + CFG_SYS_INIT_RAM_ADDR) #endif .text @@ -123,18 +123,18 @@ asm_dram_init: #ifdef CONFIG_SYS_NAND_BOOT /* for assembly stack */ - move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0 + move.l #(CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_RAM_CTRL), %d0 movec %d0, %RAMBAR1 - move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp + move.l #(CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_SP_OFFSET), %sp clr.l %sp@- #endif #ifdef CONFIG_CF_SBF - move.l #CONFIG_SYS_INIT_RAM_ADDR, %d0 + move.l #CFG_SYS_INIT_RAM_ADDR, %d0 movec %d0, %VBR - move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0 + move.l #(CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_RAM_CTRL), %d0 movec %d0, %RAMBAR1 /* initialize general use internal ram */ @@ -145,7 +145,7 @@ asm_dram_init: move.l %d0, (%a2) /* invalidate and disable cache */ - move.l #(CONFIG_SYS_ICACHE_INV + CONFIG_SYS_DCACHE_INV), %d0 + move.l #(CFG_SYS_ICACHE_INV + CFG_SYS_DCACHE_INV), %d0 movec %d0, %CACR /* Invalidate cache */ move.l #0, %d0 movec %d0, %ACR0 @@ -153,17 +153,17 @@ asm_dram_init: movec %d0, %ACR2 movec %d0, %ACR3 - move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp + move.l #(CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_SP_OFFSET), %sp clr.l %sp@- -#ifdef CONFIG_SYS_CS0_BASE +#ifdef CFG_SYS_CS0_BASE /* Must disable global address */ move.l #0xFC008000, %a1 - move.l #(CONFIG_SYS_CS0_BASE), (%a1) + move.l #(CFG_SYS_CS0_BASE), (%a1) move.l #0xFC008008, %a1 - move.l #(CONFIG_SYS_CS0_CTRL), (%a1) + move.l #(CFG_SYS_CS0_CTRL), (%a1) move.l #0xFC008004, %a1 - move.l #(CONFIG_SYS_CS0_MASK), (%a1) + move.l #(CFG_SYS_CS0_MASK), (%a1) #endif #endif /* CONFIG_CF_SBF */ @@ -216,8 +216,8 @@ asm_dspi_init: move.l (%a1)+, %d5 move.l (%a1), %a4 - move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_SBFHDR_DATA_OFFSET), %a0 - move.l #(CONFIG_SYS_SBFHDR_SIZE), %d4 + move.l #(CFG_SYS_INIT_RAM_ADDR + CFG_SYS_SBFHDR_DATA_OFFSET), %a0 + move.l #(CFG_SYS_SBFHDR_SIZE), %d4 move.l #0xFC05C02C, %a1 /* dspi status */ @@ -334,14 +334,14 @@ asm_nand_init: movec %d0, %ACR2 movec %d0, %ACR3 -#ifdef CONFIG_SYS_CS0_BASE +#ifdef CFG_SYS_CS0_BASE /* Must disable global address */ move.l #0xFC008000, %a1 - move.l #(CONFIG_SYS_CS0_BASE), (%a1) + move.l #(CFG_SYS_CS0_BASE), (%a1) move.l #0xFC008008, %a1 - move.l #(CONFIG_SYS_CS0_CTRL), (%a1) + move.l #(CFG_SYS_CS0_CTRL), (%a1) move.l #0xFC008004, %a1 - move.l #(CONFIG_SYS_CS0_MASK), (%a1) + move.l #(CFG_SYS_CS0_MASK), (%a1) #endif /* NAND port configuration */ @@ -442,10 +442,10 @@ _start: move.w #0x2700,%sr /* Mask off Interrupt */ /* Set vector base register at the beginning of the Flash */ - move.l #CONFIG_SYS_FLASH_BASE, %d0 + move.l #CFG_SYS_FLASH_BASE, %d0 movec %d0, %VBR - move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0 + move.l #(CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_RAM_CTRL), %d0 movec %d0, %RAMBAR1 /* initialize general use internal ram */ @@ -456,7 +456,7 @@ _start: move.l %d0, (%a2) /* invalidate and disable cache */ - move.l #(CONFIG_SYS_ICACHE_INV + CONFIG_SYS_DCACHE_INV), %d0 + move.l #(CFG_SYS_ICACHE_INV + CFG_SYS_DCACHE_INV), %d0 movec %d0, %CACR /* Invalidate cache */ move.l #0, %d0 movec %d0, %ACR0 @@ -464,7 +464,7 @@ _start: movec %d0, %ACR2 movec %d0, %ACR3 #else - move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0 + move.l #(CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_RAM_CTRL), %d0 movec %d0, %RAMBAR1 #endif @@ -472,7 +472,7 @@ _start: move.l #__got_start, %a5 /* setup stack initially on top of internal static ram */ - move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE), %sp + move.l #(CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_RAM_SIZE), %sp /* * if configured, malloc_f arena will be reserved first, diff --git a/arch/m68k/include/asm/cache.h b/arch/m68k/include/asm/cache.h index ceb462f438..c05356fc93 100644 --- a/arch/m68k/include/asm/cache.h +++ b/arch/m68k/include/asm/cache.h @@ -135,28 +135,28 @@ #endif /* CONFIG_CF_V4 */ -#ifndef CONFIG_SYS_CACHE_ICACR -#define CONFIG_SYS_CACHE_ICACR 0 +#ifndef CFG_SYS_CACHE_ICACR +#define CFG_SYS_CACHE_ICACR 0 #endif -#ifndef CONFIG_SYS_CACHE_DCACR -#ifdef CONFIG_SYS_CACHE_ICACR -#define CONFIG_SYS_CACHE_DCACR CONFIG_SYS_CACHE_ICACR +#ifndef CFG_SYS_CACHE_DCACR +#ifdef CFG_SYS_CACHE_ICACR +#define CFG_SYS_CACHE_DCACR CFG_SYS_CACHE_ICACR #else -#define CONFIG_SYS_CACHE_DCACR 0 +#define CFG_SYS_CACHE_DCACR 0 #endif #endif -#ifndef CONFIG_SYS_CACHE_ACR0 -#define CONFIG_SYS_CACHE_ACR0 0 +#ifndef CFG_SYS_CACHE_ACR0 +#define CFG_SYS_CACHE_ACR0 0 #endif -#ifndef CONFIG_SYS_CACHE_ACR1 -#define CONFIG_SYS_CACHE_ACR1 0 +#ifndef CFG_SYS_CACHE_ACR1 +#define CFG_SYS_CACHE_ACR1 0 #endif -#ifndef CONFIG_SYS_CACHE_ACR2 -#define CONFIG_SYS_CACHE_ACR2 0 +#ifndef CFG_SYS_CACHE_ACR2 +#define CFG_SYS_CACHE_ACR2 0 #endif #ifndef CONFIG_SYS_CACHE_ACR3 diff --git a/arch/m68k/include/asm/immap.h b/arch/m68k/include/asm/immap.h index ead62cd038..dab8b26a70 100644 --- a/arch/m68k/include/asm/immap.h +++ b/arch/m68k/include/asm/immap.h @@ -14,7 +14,7 @@ #include <asm/m520x.h> #define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC0) -#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x4000)) +#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x4000)) /* Timer */ #ifdef CONFIG_MCFTMR @@ -37,7 +37,7 @@ #include <asm/m5235.h> #define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC) -#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40)) +#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40)) /* Timer */ #ifdef CONFIG_MCFTMR @@ -59,7 +59,7 @@ #include <asm/immap_5249.h> #include <asm/m5249.h> -#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40)) +#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40)) #define CONFIG_SYS_INTR_BASE (MMAP_INTC) #define CONFIG_SYS_NUM_IRQS (64) @@ -82,7 +82,7 @@ #include <asm/m5249.h> #include <asm/m5253.h> -#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40)) +#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40)) #define CONFIG_SYS_INTR_BASE (MMAP_INTC) #define CONFIG_SYS_NUM_IRQS (64) @@ -105,7 +105,7 @@ #include <asm/m5271.h> #define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC) -#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40)) +#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40)) /* Timer */ #ifdef CONFIG_MCFTMR @@ -128,7 +128,7 @@ #include <asm/m5272.h> #define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC) -#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40)) +#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40)) #define CONFIG_SYS_INTR_BASE (MMAP_INTC) #define CONFIG_SYS_NUM_IRQS (64) @@ -152,7 +152,7 @@ #define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC0) #define CONFIG_SYS_FEC1_IOBASE (MMAP_FEC1) -#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40)) +#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40)) #define CONFIG_SYS_INTR_BASE (MMAP_INTC0) #define CONFIG_SYS_NUM_IRQS (192) @@ -175,7 +175,7 @@ #include <asm/m5282.h> #define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC) -#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40)) +#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40)) #define CONFIG_SYS_INTR_BASE (MMAP_INTC0) #define CONFIG_SYS_NUM_IRQS (128) @@ -198,7 +198,7 @@ #include <asm/m5307.h> #define CONFIG_SYS_UART_BASE (MMAP_UART0 + \ - (CONFIG_SYS_UART_PORT * 0x40)) + (CFG_SYS_UART_PORT * 0x40)) #define CONFIG_SYS_INTR_BASE (MMAP_INTC) #define CONFIG_SYS_NUM_IRQS (64) @@ -223,7 +223,7 @@ #define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC0) #define CONFIG_SYS_FEC1_IOBASE (MMAP_FEC1) -#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x4000)) +#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x4000)) /* Timer */ #ifdef CONFIG_MCFTMR @@ -246,7 +246,7 @@ #include <asm/m5329.h> #define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC) -#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x4000)) +#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x4000)) /* Timer */ #ifdef CONFIG_MCFTMR @@ -271,12 +271,12 @@ #define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC0) #define CONFIG_SYS_FEC1_IOBASE (MMAP_FEC1) -#if (CONFIG_SYS_UART_PORT < 4) +#if (CFG_SYS_UART_PORT < 4) #define CONFIG_SYS_UART_BASE (MMAP_UART0 + \ - (CONFIG_SYS_UART_PORT * 0x4000)) + (CFG_SYS_UART_PORT * 0x4000)) #else #define CONFIG_SYS_UART_BASE (MMAP_UART4 + \ - ((CONFIG_SYS_UART_PORT - 4) * 0x4000)) + ((CFG_SYS_UART_PORT - 4) * 0x4000)) #endif #define MMAP_DSPI MMAP_DSPI0 @@ -320,7 +320,7 @@ #define FEC1_TX_INIT 31 #endif -#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x100)) +#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x100)) #ifdef CONFIG_SLTTMR #define CONFIG_SYS_UDELAY_BASE (MMAP_SLT1) @@ -337,10 +337,10 @@ #define CONFIG_SYS_NUM_IRQS (128) #ifdef CONFIG_PCI -#define CONFIG_SYS_PCI_BAR0 (0x40000000) -#define CONFIG_SYS_PCI_BAR1 (CONFIG_SYS_SDRAM_BASE) -#define CONFIG_SYS_PCI_TBATR0 (CONFIG_SYS_MBAR) -#define CONFIG_SYS_PCI_TBATR1 (CONFIG_SYS_SDRAM_BASE) +#define CFG_SYS_PCI_BAR0 (0x40000000) +#define CFG_SYS_PCI_BAR1 (CFG_SYS_SDRAM_BASE) +#define CFG_SYS_PCI_TBATR0 (CFG_SYS_MBAR) +#define CFG_SYS_PCI_TBATR1 (CFG_SYS_SDRAM_BASE) #endif #endif /* CONFIG_M547x */ diff --git a/arch/m68k/include/asm/immap_520x.h b/arch/m68k/include/asm/immap_520x.h index bb1237453f..7c7443b968 100644 --- a/arch/m68k/include/asm/immap_520x.h +++ b/arch/m68k/include/asm/immap_520x.h @@ -9,32 +9,32 @@ #ifndef __IMMAP_520X__ #define __IMMAP_520X__ -#define MMAP_SCM1 (CONFIG_SYS_MBAR + 0x00000000) -#define MMAP_XBS (CONFIG_SYS_MBAR + 0x00004000) -#define MMAP_FBCS (CONFIG_SYS_MBAR + 0x00008000) -#define MMAP_FEC0 (CONFIG_SYS_MBAR + 0x00030000) -#define MMAP_SCM2 (CONFIG_SYS_MBAR + 0x00040000) -#define MMAP_EDMA (CONFIG_SYS_MBAR + 0x00044000) -#define MMAP_INTC0 (CONFIG_SYS_MBAR + 0x00048000) -#define MMAP_INTCACK (CONFIG_SYS_MBAR + 0x00054000) -#define MMAP_I2C (CONFIG_SYS_MBAR + 0x00058000) -#define MMAP_QSPI (CONFIG_SYS_MBAR + 0x0005C000) -#define MMAP_UART0 (CONFIG_SYS_MBAR + 0x00060000) -#define MMAP_UART1 (CONFIG_SYS_MBAR + 0x00064000) -#define MMAP_UART2 (CONFIG_SYS_MBAR + 0x00068000) -#define MMAP_DTMR0 (CONFIG_SYS_MBAR + 0x00070000) -#define MMAP_DTMR1 (CONFIG_SYS_MBAR + 0x00074000) -#define MMAP_DTMR2 (CONFIG_SYS_MBAR + 0x00078000) -#define MMAP_DTMR3 (CONFIG_SYS_MBAR + 0x0007C000) -#define MMAP_PIT0 (CONFIG_SYS_MBAR + 0x00080000) -#define MMAP_PIT1 (CONFIG_SYS_MBAR + 0x00084000) -#define MMAP_EPORT0 (CONFIG_SYS_MBAR + 0x00088000) -#define MMAP_WDOG (CONFIG_SYS_MBAR + 0x0008C000) -#define MMAP_PLL (CONFIG_SYS_MBAR + 0x00090000) -#define MMAP_RCM (CONFIG_SYS_MBAR + 0x000A0000) -#define MMAP_CCM (CONFIG_SYS_MBAR + 0x000A0004) -#define MMAP_GPIO (CONFIG_SYS_MBAR + 0x000A4000) -#define MMAP_SDRAM (CONFIG_SYS_MBAR + 0x000A8000) +#define MMAP_SCM1 (CFG_SYS_MBAR + 0x00000000) +#define MMAP_XBS (CFG_SYS_MBAR + 0x00004000) +#define MMAP_FBCS (CFG_SYS_MBAR + 0x00008000) +#define MMAP_FEC0 (CFG_SYS_MBAR + 0x00030000) +#define MMAP_SCM2 (CFG_SYS_MBAR + 0x00040000) +#define MMAP_EDMA (CFG_SYS_MBAR + 0x00044000) +#define MMAP_INTC0 (CFG_SYS_MBAR + 0x00048000) +#define MMAP_INTCACK (CFG_SYS_MBAR + 0x00054000) +#define MMAP_I2C (CFG_SYS_MBAR + 0x00058000) +#define MMAP_QSPI (CFG_SYS_MBAR + 0x0005C000) +#define MMAP_UART0 (CFG_SYS_MBAR + 0x00060000) +#define MMAP_UART1 (CFG_SYS_MBAR + 0x00064000) +#define MMAP_UART2 (CFG_SYS_MBAR + 0x00068000) +#define MMAP_DTMR0 (CFG_SYS_MBAR + 0x00070000) +#define MMAP_DTMR1 (CFG_SYS_MBAR + 0x00074000) +#define MMAP_DTMR2 (CFG_SYS_MBAR + 0x00078000) +#define MMAP_DTMR3 (CFG_SYS_MBAR + 0x0007C000) +#define MMAP_PIT0 (CFG_SYS_MBAR + 0x00080000) +#define MMAP_PIT1 (CFG_SYS_MBAR + 0x00084000) +#define MMAP_EPORT0 (CFG_SYS_MBAR + 0x00088000) +#define MMAP_WDOG (CFG_SYS_MBAR + 0x0008C000) +#define MMAP_PLL (CFG_SYS_MBAR + 0x00090000) +#define MMAP_RCM (CFG_SYS_MBAR + 0x000A0000) +#define MMAP_CCM (CFG_SYS_MBAR + 0x000A0004) +#define MMAP_GPIO (CFG_SYS_MBAR + 0x000A4000) +#define MMAP_SDRAM (CFG_SYS_MBAR + 0x000A8000) #include <asm/coldfire/crossbar.h> #include <asm/coldfire/edma.h> diff --git a/arch/m68k/include/asm/immap_5235.h b/arch/m68k/include/asm/immap_5235.h index 27d905ef94..a1825c2a94 100644 --- a/arch/m68k/include/asm/immap_5235.h +++ b/arch/m68k/include/asm/immap_5235.h @@ -9,42 +9,42 @@ #ifndef __IMMAP_5235__ #define __IMMAP_5235__ -#define MMAP_SCM (CONFIG_SYS_MBAR + 0x00000000) -#define MMAP_SDRAM (CONFIG_SYS_MBAR + 0x00000040) -#define MMAP_FBCS (CONFIG_SYS_MBAR + 0x00000080) -#define MMAP_DMA0 (CONFIG_SYS_MBAR + 0x00000100) -#define MMAP_DMA1 (CONFIG_SYS_MBAR + 0x00000110) -#define MMAP_DMA2 (CONFIG_SYS_MBAR + 0x00000120) -#define MMAP_DMA3 (CONFIG_SYS_MBAR + 0x00000130) -#define MMAP_UART0 (CONFIG_SYS_MBAR + 0x00000200) -#define MMAP_UART1 (CONFIG_SYS_MBAR + 0x00000240) -#define MMAP_UART2 (CONFIG_SYS_MBAR + 0x00000280) -#define MMAP_I2C (CONFIG_SYS_MBAR + 0x00000300) -#define MMAP_QSPI (CONFIG_SYS_MBAR + 0x00000340) -#define MMAP_DTMR0 (CONFIG_SYS_MBAR + 0x00000400) -#define MMAP_DTMR1 (CONFIG_SYS_MBAR + 0x00000440) -#define MMAP_DTMR2 (CONFIG_SYS_MBAR + 0x00000480) -#define MMAP_DTMR3 (CONFIG_SYS_MBAR + 0x000004C0) -#define MMAP_INTC0 (CONFIG_SYS_MBAR + 0x00000C00) -#define MMAP_INTC1 (CONFIG_SYS_MBAR + 0x00000D00) -#define MMAP_INTCACK (CONFIG_SYS_MBAR + 0x00000F00) -#define MMAP_FEC (CONFIG_SYS_MBAR + 0x00001000) -#define MMAP_FECFIFO (CONFIG_SYS_MBAR + 0x00001400) -#define MMAP_GPIO (CONFIG_SYS_MBAR + 0x00100000) -#define MMAP_CCM (CONFIG_SYS_MBAR + 0x00110000) -#define MMAP_PLL (CONFIG_SYS_MBAR + 0x00120000) -#define MMAP_EPORT (CONFIG_SYS_MBAR + 0x00130000) -#define MMAP_WDOG (CONFIG_SYS_MBAR + 0x00140000) -#define MMAP_PIT0 (CONFIG_SYS_MBAR + 0x00150000) -#define MMAP_PIT1 (CONFIG_SYS_MBAR + 0x00160000) -#define MMAP_PIT2 (CONFIG_SYS_MBAR + 0x00170000) -#define MMAP_PIT3 (CONFIG_SYS_MBAR + 0x00180000) -#define MMAP_MDHA (CONFIG_SYS_MBAR + 0x00190000) -#define MMAP_RNG (CONFIG_SYS_MBAR + 0x001A0000) -#define MMAP_SKHA (CONFIG_SYS_MBAR + 0x001B0000) -#define MMAP_CAN1 (CONFIG_SYS_MBAR + 0x001C0000) -#define MMAP_ETPU (CONFIG_SYS_MBAR + 0x001D0000) -#define MMAP_CAN2 (CONFIG_SYS_MBAR + 0x001F0000) +#define MMAP_SCM (CFG_SYS_MBAR + 0x00000000) +#define MMAP_SDRAM (CFG_SYS_MBAR + 0x00000040) +#define MMAP_FBCS (CFG_SYS_MBAR + 0x00000080) +#define MMAP_DMA0 (CFG_SYS_MBAR + 0x00000100) +#define MMAP_DMA1 (CFG_SYS_MBAR + 0x00000110) +#define MMAP_DMA2 (CFG_SYS_MBAR + 0x00000120) +#define MMAP_DMA3 (CFG_SYS_MBAR + 0x00000130) +#define MMAP_UART0 (CFG_SYS_MBAR + 0x00000200) +#define MMAP_UART1 (CFG_SYS_MBAR + 0x00000240) +#define MMAP_UART2 (CFG_SYS_MBAR + 0x00000280) +#define MMAP_I2C (CFG_SYS_MBAR + 0x00000300) +#define MMAP_QSPI (CFG_SYS_MBAR + 0x00000340) +#define MMAP_DTMR0 (CFG_SYS_MBAR + 0x00000400) +#define MMAP_DTMR1 (CFG_SYS_MBAR + 0x00000440) +#define MMAP_DTMR2 (CFG_SYS_MBAR + 0x00000480) +#define MMAP_DTMR3 (CFG_SYS_MBAR + 0x000004C0) +#define MMAP_INTC0 (CFG_SYS_MBAR + 0x00000C00) +#define MMAP_INTC1 (CFG_SYS_MBAR + 0x00000D00) +#define MMAP_INTCACK (CFG_SYS_MBAR + 0x00000F00) +#define MMAP_FEC (CFG_SYS_MBAR + 0x00001000) +#define MMAP_FECFIFO (CFG_SYS_MBAR + 0x00001400) +#define MMAP_GPIO (CFG_SYS_MBAR + 0x00100000) +#define MMAP_CCM (CFG_SYS_MBAR + 0x00110000) +#define MMAP_PLL (CFG_SYS_MBAR + 0x00120000) +#define MMAP_EPORT (CFG_SYS_MBAR + 0x00130000) +#define MMAP_WDOG (CFG_SYS_MBAR + 0x00140000) +#define MMAP_PIT0 (CFG_SYS_MBAR + 0x00150000) +#define MMAP_PIT1 (CFG_SYS_MBAR + 0x00160000) +#define MMAP_PIT2 (CFG_SYS_MBAR + 0x00170000) +#define MMAP_PIT3 (CFG_SYS_MBAR + 0x00180000) +#define MMAP_MDHA (CFG_SYS_MBAR + 0x00190000) +#define MMAP_RNG (CFG_SYS_MBAR + 0x001A0000) +#define MMAP_SKHA (CFG_SYS_MBAR + 0x001B0000) +#define MMAP_CAN1 (CFG_SYS_MBAR + 0x001C0000) +#define MMAP_ETPU (CFG_SYS_MBAR + 0x001D0000) +#define MMAP_CAN2 (CFG_SYS_MBAR + 0x001F0000) #include <asm/coldfire/eport.h> #include <asm/coldfire/flexbus.h> diff --git a/arch/m68k/include/asm/immap_5249.h b/arch/m68k/include/asm/immap_5249.h index b599ca6e81..aa4c3ef42f 100644 --- a/arch/m68k/include/asm/immap_5249.h +++ b/arch/m68k/include/asm/immap_5249.h @@ -8,13 +8,13 @@ #ifndef __IMMAP_5249__ #define __IMMAP_5249__ -#define MMAP_INTC (CONFIG_SYS_MBAR + 0x00000040) -#define MMAP_FBCS (CONFIG_SYS_MBAR + 0x00000080) -#define MMAP_DTMR0 (CONFIG_SYS_MBAR + 0x00000140) -#define MMAP_DTMR1 (CONFIG_SYS_MBAR + 0x00000180) -#define MMAP_UART0 (CONFIG_SYS_MBAR + 0x000001C0) -#define MMAP_UART1 (CONFIG_SYS_MBAR + 0x00000200) -#define MMAP_QSPI (CONFIG_SYS_MBAR + 0x00000400) +#define MMAP_INTC (CFG_SYS_MBAR + 0x00000040) +#define MMAP_FBCS (CFG_SYS_MBAR + 0x00000080) +#define MMAP_DTMR0 (CFG_SYS_MBAR + 0x00000140) +#define MMAP_DTMR1 (CFG_SYS_MBAR + 0x00000180) +#define MMAP_UART0 (CFG_SYS_MBAR + 0x000001C0) +#define MMAP_UART1 (CFG_SYS_MBAR + 0x00000200) +#define MMAP_QSPI (CFG_SYS_MBAR + 0x00000400) #include <asm/coldfire/flexbus.h> #include <asm/coldfire/qspi.h> diff --git a/arch/m68k/include/asm/immap_5253.h b/arch/m68k/include/asm/immap_5253.h index 883782aa97..1ab7243dfd 100644 --- a/arch/m68k/include/asm/immap_5253.h +++ b/arch/m68k/include/asm/immap_5253.h @@ -9,20 +9,20 @@ #ifndef __IMMAP_5253__ #define __IMMAP_5253__ -#define MMAP_INTC (CONFIG_SYS_MBAR + 0x00000040) -#define MMAP_FBCS (CONFIG_SYS_MBAR + 0x00000080) -#define MMAP_DTMR0 (CONFIG_SYS_MBAR + 0x00000140) -#define MMAP_DTMR1 (CONFIG_SYS_MBAR + 0x00000180) -#define MMAP_UART0 (CONFIG_SYS_MBAR + 0x000001C0) -#define MMAP_UART1 (CONFIG_SYS_MBAR + 0x00000200) -#define MMAP_I2C0 (CONFIG_SYS_MBAR + 0x00000280) -#define MMAP_QSPI (CONFIG_SYS_MBAR + 0x00000400) -#define MMAP_CAN0 (CONFIG_SYS_MBAR + 0x00010000) -#define MMAP_CAN1 (CONFIG_SYS_MBAR + 0x00011000) +#define MMAP_INTC (CFG_SYS_MBAR + 0x00000040) +#define MMAP_FBCS (CFG_SYS_MBAR + 0x00000080) +#define MMAP_DTMR0 (CFG_SYS_MBAR + 0x00000140) +#define MMAP_DTMR1 (CFG_SYS_MBAR + 0x00000180) +#define MMAP_UART0 (CFG_SYS_MBAR + 0x000001C0) +#define MMAP_UART1 (CFG_SYS_MBAR + 0x00000200) +#define MMAP_I2C0 (CFG_SYS_MBAR + 0x00000280) +#define MMAP_QSPI (CFG_SYS_MBAR + 0x00000400) +#define MMAP_CAN0 (CFG_SYS_MBAR + 0x00010000) +#define MMAP_CAN1 (CFG_SYS_MBAR + 0x00011000) -#define MMAP_PAR (CONFIG_SYS_MBAR2 + 0x0000019C) -#define MMAP_I2C1 (CONFIG_SYS_MBAR2 + 0x00000440) -#define MMAP_UART2 (CONFIG_SYS_MBAR2 + 0x00000C00) +#define MMAP_PAR (CFG_SYS_MBAR2 + 0x0000019C) +#define MMAP_I2C1 (CFG_SYS_MBAR2 + 0x00000440) +#define MMAP_UART2 (CFG_SYS_MBAR2 + 0x00000C00) #include <asm/coldfire/ata.h> #include <asm/coldfire/flexbus.h> diff --git a/arch/m68k/include/asm/immap_5271.h b/arch/m68k/include/asm/immap_5271.h index 27d7861399..a5bf18c4b8 100644 --- a/arch/m68k/include/asm/immap_5271.h +++ b/arch/m68k/include/asm/immap_5271.h @@ -9,42 +9,42 @@ #ifndef __IMMAP_5271__ #define __IMMAP_5271__ -#define MMAP_SCM (CONFIG_SYS_MBAR + 0x00000000) -#define MMAP_SDRAM (CONFIG_SYS_MBAR + 0x00000040) -#define MMAP_FBCS (CONFIG_SYS_MBAR + 0x00000080) -#define MMAP_DMA0 (CONFIG_SYS_MBAR + 0x00000100) -#define MMAP_DMA1 (CONFIG_SYS_MBAR + 0x00000110) -#define MMAP_DMA2 (CONFIG_SYS_MBAR + 0x00000120) -#define MMAP_DMA3 (CONFIG_SYS_MBAR + 0x00000130) -#define MMAP_UART0 (CONFIG_SYS_MBAR + 0x00000200) -#define MMAP_UART1 (CONFIG_SYS_MBAR + 0x00000240) -#define MMAP_UART2 (CONFIG_SYS_MBAR + 0x00000280) -#define MMAP_I2C (CONFIG_SYS_MBAR + 0x00000300) -#define MMAP_QSPI (CONFIG_SYS_MBAR + 0x00000340) -#define MMAP_DTMR0 (CONFIG_SYS_MBAR + 0x00000400) -#define MMAP_DTMR1 (CONFIG_SYS_MBAR + 0x00000440) -#define MMAP_DTMR2 (CONFIG_SYS_MBAR + 0x00000480) -#define MMAP_DTMR3 (CONFIG_SYS_MBAR + 0x000004C0) -#define MMAP_INTC0 (CONFIG_SYS_MBAR + 0x00000C00) -#define MMAP_INTC1 (CONFIG_SYS_MBAR + 0x00000D00) -#define MMAP_INTCACK (CONFIG_SYS_MBAR + 0x00000F00) -#define MMAP_FEC (CONFIG_SYS_MBAR + 0x00001000) -#define MMAP_FECFIFO (CONFIG_SYS_MBAR + 0x00001400) -#define MMAP_GPIO (CONFIG_SYS_MBAR + 0x00100000) -#define MMAP_CCM (CONFIG_SYS_MBAR + 0x00110000) -#define MMAP_PLL (CONFIG_SYS_MBAR + 0x00120000) -#define MMAP_EPORT (CONFIG_SYS_MBAR + 0x00130000) -#define MMAP_WDOG (CONFIG_SYS_MBAR + 0x00140000) -#define MMAP_PIT0 (CONFIG_SYS_MBAR + 0x00150000) -#define MMAP_PIT1 (CONFIG_SYS_MBAR + 0x00160000) -#define MMAP_PIT2 (CONFIG_SYS_MBAR + 0x00170000) -#define MMAP_PIT3 (CONFIG_SYS_MBAR + 0x00180000) -#define MMAP_MDHA (CONFIG_SYS_MBAR + 0x00190000) -#define MMAP_RNG (CONFIG_SYS_MBAR + 0x001A0000) -#define MMAP_SKHA (CONFIG_SYS_MBAR + 0x001B0000) -#define MMAP_CAN1 (CONFIG_SYS_MBAR + 0x001C0000) -#define MMAP_ETPU (CONFIG_SYS_MBAR + 0x001D0000) -#define MMAP_CAN2 (CONFIG_SYS_MBAR + 0x001F0000) +#define MMAP_SCM (CFG_SYS_MBAR + 0x00000000) +#define MMAP_SDRAM (CFG_SYS_MBAR + 0x00000040) +#define MMAP_FBCS (CFG_SYS_MBAR + 0x00000080) +#define MMAP_DMA0 (CFG_SYS_MBAR + 0x00000100) +#define MMAP_DMA1 (CFG_SYS_MBAR + 0x00000110) +#define MMAP_DMA2 (CFG_SYS_MBAR + 0x00000120) +#define MMAP_DMA3 (CFG_SYS_MBAR + 0x00000130) +#define MMAP_UART0 (CFG_SYS_MBAR + 0x00000200) +#define MMAP_UART1 (CFG_SYS_MBAR + 0x00000240) +#define MMAP_UART2 (CFG_SYS_MBAR + 0x00000280) +#define MMAP_I2C (CFG_SYS_MBAR + 0x00000300) +#define MMAP_QSPI (CFG_SYS_MBAR + 0x00000340) +#define MMAP_DTMR0 (CFG_SYS_MBAR + 0x00000400) +#define MMAP_DTMR1 (CFG_SYS_MBAR + 0x00000440) +#define MMAP_DTMR2 (CFG_SYS_MBAR + 0x00000480) +#define MMAP_DTMR3 (CFG_SYS_MBAR + 0x000004C0) +#define MMAP_INTC0 (CFG_SYS_MBAR + 0x00000C00) +#define MMAP_INTC1 (CFG_SYS_MBAR + 0x00000D00) +#define MMAP_INTCACK (CFG_SYS_MBAR + 0x00000F00) +#define MMAP_FEC (CFG_SYS_MBAR + 0x00001000) +#define MMAP_FECFIFO (CFG_SYS_MBAR + 0x00001400) +#define MMAP_GPIO (CFG_SYS_MBAR + 0x00100000) +#define MMAP_CCM (CFG_SYS_MBAR + 0x00110000) +#define MMAP_PLL (CFG_SYS_MBAR + 0x00120000) +#define MMAP_EPORT (CFG_SYS_MBAR + 0x00130000) +#define MMAP_WDOG (CFG_SYS_MBAR + 0x00140000) +#define MMAP_PIT0 (CFG_SYS_MBAR + 0x00150000) +#define MMAP_PIT1 (CFG_SYS_MBAR + 0x00160000) +#define MMAP_PIT2 (CFG_SYS_MBAR + 0x00170000) +#define MMAP_PIT3 (CFG_SYS_MBAR + 0x00180000) +#define MMAP_MDHA (CFG_SYS_MBAR + 0x00190000) +#define MMAP_RNG (CFG_SYS_MBAR + 0x001A0000) +#define MMAP_SKHA (CFG_SYS_MBAR + 0x001B0000) +#define MMAP_CAN1 (CFG_SYS_MBAR + 0x001C0000) +#define MMAP_ETPU (CFG_SYS_MBAR + 0x001D0000) +#define MMAP_CAN2 (CFG_SYS_MBAR + 0x001F0000) #include <asm/coldfire/eport.h> #include <asm/coldfire/flexbus.h> diff --git a/arch/m68k/include/asm/immap_5272.h b/arch/m68k/include/asm/immap_5272.h index cd7b67256c..c5c3cc7512 100644 --- a/arch/m68k/include/asm/immap_5272.h +++ b/arch/m68k/include/asm/immap_5272.h @@ -8,24 +8,24 @@ #ifndef __IMMAP_5272__ #define __IMMAP_5272__ -#define MMAP_CFG (CONFIG_SYS_MBAR + 0x00000000) -#define MMAP_INTC (CONFIG_SYS_MBAR + 0x00000020) -#define MMAP_FBCS (CONFIG_SYS_MBAR + 0x00000040) -#define MMAP_GPIO (CONFIG_SYS_MBAR + 0x00000080) -#define MMAP_QSPI (CONFIG_SYS_MBAR + 0x000000A0) -#define MMAP_PWM (CONFIG_SYS_MBAR + 0x000000C0) -#define MMAP_DMA0 (CONFIG_SYS_MBAR + 0x000000E0) -#define MMAP_UART0 (CONFIG_SYS_MBAR + 0x00000100) -#define MMAP_UART1 (CONFIG_SYS_MBAR + 0x00000140) -#define MMAP_SDRAM (CONFIG_SYS_MBAR + 0x00000180) -#define MMAP_TMR0 (CONFIG_SYS_MBAR + 0x00000200) -#define MMAP_TMR1 (CONFIG_SYS_MBAR + 0x00000220) -#define MMAP_TMR2 (CONFIG_SYS_MBAR + 0x00000240) -#define MMAP_TMR3 (CONFIG_SYS_MBAR + 0x00000260) -#define MMAP_WDOG (CONFIG_SYS_MBAR + 0x00000280) -#define MMAP_PLIC (CONFIG_SYS_MBAR + 0x00000300) -#define MMAP_FEC (CONFIG_SYS_MBAR + 0x00000840) -#define MMAP_USB (CONFIG_SYS_MBAR + 0x00001000) +#define MMAP_CFG (CFG_SYS_MBAR + 0x00000000) +#define MMAP_INTC (CFG_SYS_MBAR + 0x00000020) +#define MMAP_FBCS (CFG_SYS_MBAR + 0x00000040) +#define MMAP_GPIO (CFG_SYS_MBAR + 0x00000080) +#define MMAP_QSPI (CFG_SYS_MBAR + 0x000000A0) +#define MMAP_PWM (CFG_SYS_MBAR + 0x000000C0) +#define MMAP_DMA0 (CFG_SYS_MBAR + 0x000000E0) +#define MMAP_UART0 (CFG_SYS_MBAR + 0x00000100) +#define MMAP_UART1 (CFG_SYS_MBAR + 0x00000140) +#define MMAP_SDRAM (CFG_SYS_MBAR + 0x00000180) +#define MMAP_TMR0 (CFG_SYS_MBAR + 0x00000200) +#define MMAP_TMR1 (CFG_SYS_MBAR + 0x00000220) +#define MMAP_TMR2 (CFG_SYS_MBAR + 0x00000240) +#define MMAP_TMR3 (CFG_SYS_MBAR + 0x00000260) +#define MMAP_WDOG (CFG_SYS_MBAR + 0x00000280) +#define MMAP_PLIC (CFG_SYS_MBAR + 0x00000300) +#define MMAP_FEC (CFG_SYS_MBAR + 0x00000840) +#define MMAP_USB (CFG_SYS_MBAR + 0x00001000) #include <asm/coldfire/pwm.h> diff --git a/arch/m68k/include/asm/immap_5275.h b/arch/m68k/include/asm/immap_5275.h index 8b1a08b4f2..9b8d71d30d 100644 --- a/arch/m68k/include/asm/immap_5275.h +++ b/arch/m68k/include/asm/immap_5275.h @@ -10,44 +10,44 @@ #ifndef __IMMAP_5275__ #define __IMMAP_5275__ -#define MMAP_SCM (CONFIG_SYS_MBAR + 0x00000000) -#define MMAP_SDRAM (CONFIG_SYS_MBAR + 0x00000040) -#define MMAP_FBCS (CONFIG_SYS_MBAR + 0x00000080) -#define MMAP_DMA0 (CONFIG_SYS_MBAR + 0x00000100) -#define MMAP_DMA1 (CONFIG_SYS_MBAR + 0x00000110) -#define MMAP_DMA2 (CONFIG_SYS_MBAR + 0x00000120) -#define MMAP_DMA3 (CONFIG_SYS_MBAR + 0x00000130) -#define MMAP_UART0 (CONFIG_SYS_MBAR + 0x00000200) -#define MMAP_UART1 (CONFIG_SYS_MBAR + 0x00000240) -#define MMAP_UART2 (CONFIG_SYS_MBAR + 0x00000280) -#define MMAP_I2C (CONFIG_SYS_MBAR + 0x00000300) -#define MMAP_QSPI (CONFIG_SYS_MBAR + 0x00000340) -#define MMAP_DTMR0 (CONFIG_SYS_MBAR + 0x00000400) -#define MMAP_DTMR1 (CONFIG_SYS_MBAR + 0x00000440) -#define MMAP_DTMR2 (CONFIG_SYS_MBAR + 0x00000480) -#define MMAP_DTMR3 (CONFIG_SYS_MBAR + 0x000004C0) -#define MMAP_INTC0 (CONFIG_SYS_MBAR + 0x00000C00) -#define MMAP_INTC1 (CONFIG_SYS_MBAR + 0x00000D00) -#define MMAP_INTCACK (CONFIG_SYS_MBAR + 0x00000F00) -#define MMAP_FEC0 (CONFIG_SYS_MBAR + 0x00001000) -#define MMAP_FEC0FIFO (CONFIG_SYS_MBAR + 0x00001400) -#define MMAP_FEC1 (CONFIG_SYS_MBAR + 0x00001800) -#define MMAP_FEC1FIFO (CONFIG_SYS_MBAR + 0x00001C00) -#define MMAP_GPIO (CONFIG_SYS_MBAR + 0x00100000) -#define MMAP_RCM (CONFIG_SYS_MBAR + 0x00110000) -#define MMAP_CCM (CONFIG_SYS_MBAR + 0x00110004) -#define MMAP_PLL (CONFIG_SYS_MBAR + 0x00120000) -#define MMAP_EPORT (CONFIG_SYS_MBAR + 0x00130000) -#define MMAP_WDOG (CONFIG_SYS_MBAR + 0x00140000) -#define MMAP_PIT0 (CONFIG_SYS_MBAR + 0x00150000) -#define MMAP_PIT1 (CONFIG_SYS_MBAR + 0x00160000) -#define MMAP_PIT2 (CONFIG_SYS_MBAR + 0x00170000) -#define MMAP_PIT3 (CONFIG_SYS_MBAR + 0x00180000) -#define MMAP_MDHA (CONFIG_SYS_MBAR + 0x00190000) -#define MMAP_RNG (CONFIG_SYS_MBAR + 0x001A0000) -#define MMAP_SKHA (CONFIG_SYS_MBAR + 0x001B0000) -#define MMAP_USB (CONFIG_SYS_MBAR + 0x001C0000) -#define MMAP_PWM0 (CONFIG_SYS_MBAR + 0x001D0000) +#define MMAP_SCM (CFG_SYS_MBAR + 0x00000000) +#define MMAP_SDRAM (CFG_SYS_MBAR + 0x00000040) +#define MMAP_FBCS (CFG_SYS_MBAR + 0x00000080) +#define MMAP_DMA0 (CFG_SYS_MBAR + 0x00000100) +#define MMAP_DMA1 (CFG_SYS_MBAR + 0x00000110) +#define MMAP_DMA2 (CFG_SYS_MBAR + 0x00000120) +#define MMAP_DMA3 (CFG_SYS_MBAR + 0x00000130) +#define MMAP_UART0 (CFG_SYS_MBAR + 0x00000200) +#define MMAP_UART1 (CFG_SYS_MBAR + 0x00000240) +#define MMAP_UART2 (CFG_SYS_MBAR + 0x00000280) +#define MMAP_I2C (CFG_SYS_MBAR + 0x00000300) +#define MMAP_QSPI (CFG_SYS_MBAR + 0x00000340) +#define MMAP_DTMR0 (CFG_SYS_MBAR + 0x00000400) +#define MMAP_DTMR1 (CFG_SYS_MBAR + 0x00000440) +#define MMAP_DTMR2 (CFG_SYS_MBAR + 0x00000480) +#define MMAP_DTMR3 (CFG_SYS_MBAR + 0x000004C0) +#define MMAP_INTC0 (CFG_SYS_MBAR + 0x00000C00) +#define MMAP_INTC1 (CFG_SYS_MBAR + 0x00000D00) +#define MMAP_INTCACK (CFG_SYS_MBAR + 0x00000F00) +#define MMAP_FEC0 (CFG_SYS_MBAR + 0x00001000) +#define MMAP_FEC0FIFO (CFG_SYS_MBAR + 0x00001400) +#define MMAP_FEC1 (CFG_SYS_MBAR + 0x00001800) +#define MMAP_FEC1FIFO (CFG_SYS_MBAR + 0x00001C00) +#define MMAP_GPIO (CFG_SYS_MBAR + 0x00100000) +#define MMAP_RCM (CFG_SYS_MBAR + 0x00110000) +#define MMAP_CCM (CFG_SYS_MBAR + 0x00110004) +#define MMAP_PLL (CFG_SYS_MBAR + 0x00120000) +#define MMAP_EPORT (CFG_SYS_MBAR + 0x00130000) +#define MMAP_WDOG (CFG_SYS_MBAR + 0x00140000) +#define MMAP_PIT0 (CFG_SYS_MBAR + 0x00150000) +#define MMAP_PIT1 (CFG_SYS_MBAR + 0x00160000) +#define MMAP_PIT2 (CFG_SYS_MBAR + 0x00170000) +#define MMAP_PIT3 (CFG_SYS_MBAR + 0x00180000) +#define MMAP_MDHA (CFG_SYS_MBAR + 0x00190000) +#define MMAP_RNG (CFG_SYS_MBAR + 0x001A0000) +#define MMAP_SKHA (CFG_SYS_MBAR + 0x001B0000) +#define MMAP_USB (CFG_SYS_MBAR + 0x001C0000) +#define MMAP_PWM0 (CFG_SYS_MBAR + 0x001D0000) #include <asm/coldfire/eport.h> #include <asm/coldfire/flexbus.h> diff --git a/arch/m68k/include/asm/immap_5282.h b/arch/m68k/include/asm/immap_5282.h index d7c68f5749..f810a4dd5c 100644 --- a/arch/m68k/include/asm/immap_5282.h +++ b/arch/m68k/include/asm/immap_5282.h @@ -8,42 +8,42 @@ #ifndef __IMMAP_5282__ #define __IMMAP_5282__ -#define MMAP_SCM (CONFIG_SYS_MBAR + 0x00000000) -#define MMAP_SDRAMC (CONFIG_SYS_MBAR + 0x00000040) -#define MMAP_FBCS (CONFIG_SYS_MBAR + 0x00000080) -#define MMAP_DMA0 (CONFIG_SYS_MBAR + 0x00000100) -#define MMAP_DMA1 (CONFIG_SYS_MBAR + 0x00000140) -#define MMAP_DMA2 (CONFIG_SYS_MBAR + 0x00000180) -#define MMAP_DMA3 (CONFIG_SYS_MBAR + 0x000001C0) -#define MMAP_UART0 (CONFIG_SYS_MBAR + 0x00000200) -#define MMAP_UART1 (CONFIG_SYS_MBAR + 0x00000240) -#define MMAP_UART2 (CONFIG_SYS_MBAR + 0x00000280) -#define MMAP_I2C (CONFIG_SYS_MBAR + 0x00000300) -#define MMAP_QSPI (CONFIG_SYS_MBAR + 0x00000340) -#define MMAP_DTMR0 (CONFIG_SYS_MBAR + 0x00000400) -#define MMAP_DTMR1 (CONFIG_SYS_MBAR + 0x00000440) -#define MMAP_DTMR2 (CONFIG_SYS_MBAR + 0x00000480) -#define MMAP_DTMR3 (CONFIG_SYS_MBAR + 0x000004C0) -#define MMAP_INTC0 (CONFIG_SYS_MBAR + 0x00000C00) -#define MMAP_INTC1 (CONFIG_SYS_MBAR + 0x00000D00) -#define MMAP_INTCACK (CONFIG_SYS_MBAR + 0x00000F00) -#define MMAP_FEC (CONFIG_SYS_MBAR + 0x00001000) -#define MMAP_FECFIFO (CONFIG_SYS_MBAR + 0x00001400) -#define MMAP_GPIO (CONFIG_SYS_MBAR + 0x00100000) -#define MMAP_CCM (CONFIG_SYS_MBAR + 0x00110000) -#define MMAP_PLL (CONFIG_SYS_MBAR + 0x00120000) -#define MMAP_EPORT (CONFIG_SYS_MBAR + 0x00130000) -#define MMAP_WDOG (CONFIG_SYS_MBAR + 0x00140000) -#define MMAP_PIT0 (CONFIG_SYS_MBAR + 0x00150000) -#define MMAP_PIT1 (CONFIG_SYS_MBAR + 0x00160000) -#define MMAP_PIT2 (CONFIG_SYS_MBAR + 0x00170000) -#define MMAP_PIT3 (CONFIG_SYS_MBAR + 0x00180000) -#define MMAP_QADC (CONFIG_SYS_MBAR + 0x00190000) -#define MMAP_GPTMRA (CONFIG_SYS_MBAR + 0x001A0000) -#define MMAP_GPTMRB (CONFIG_SYS_MBAR + 0x001B0000) -#define MMAP_CAN (CONFIG_SYS_MBAR + 0x001C0000) -#define MMAP_CFMC (CONFIG_SYS_MBAR + 0x001D0000) -#define MMAP_CFMMEM (CONFIG_SYS_MBAR + 0x04000000) +#define MMAP_SCM (CFG_SYS_MBAR + 0x00000000) +#define MMAP_SDRAMC (CFG_SYS_MBAR + 0x00000040) +#define MMAP_FBCS (CFG_SYS_MBAR + 0x00000080) +#define MMAP_DMA0 (CFG_SYS_MBAR + 0x00000100) +#define MMAP_DMA1 (CFG_SYS_MBAR + 0x00000140) +#define MMAP_DMA2 (CFG_SYS_MBAR + 0x00000180) +#define MMAP_DMA3 (CFG_SYS_MBAR + 0x000001C0) +#define MMAP_UART0 (CFG_SYS_MBAR + 0x00000200) +#define MMAP_UART1 (CFG_SYS_MBAR + 0x00000240) +#define MMAP_UART2 (CFG_SYS_MBAR + 0x00000280) +#define MMAP_I2C (CFG_SYS_MBAR + 0x00000300) +#define MMAP_QSPI (CFG_SYS_MBAR + 0x00000340) +#define MMAP_DTMR0 (CFG_SYS_MBAR + 0x00000400) +#define MMAP_DTMR1 (CFG_SYS_MBAR + 0x00000440) +#define MMAP_DTMR2 (CFG_SYS_MBAR + 0x00000480) +#define MMAP_DTMR3 (CFG_SYS_MBAR + 0x000004C0) +#define MMAP_INTC0 (CFG_SYS_MBAR + 0x00000C00) +#define MMAP_INTC1 (CFG_SYS_MBAR + 0x00000D00) +#define MMAP_INTCACK (CFG_SYS_MBAR + 0x00000F00) +#define MMAP_FEC (CFG_SYS_MBAR + 0x00001000) +#define MMAP_FECFIFO (CFG_SYS_MBAR + 0x00001400) +#define MMAP_GPIO (CFG_SYS_MBAR + 0x00100000) +#define MMAP_CCM (CFG_SYS_MBAR + 0x00110000) +#define MMAP_PLL (CFG_SYS_MBAR + 0x00120000) +#define MMAP_EPORT (CFG_SYS_MBAR + 0x00130000) +#define MMAP_WDOG (CFG_SYS_MBAR + 0x00140000) +#define MMAP_PIT0 (CFG_SYS_MBAR + 0x00150000) +#define MMAP_PIT1 (CFG_SYS_MBAR + 0x00160000) +#define MMAP_PIT2 (CFG_SYS_MBAR + 0x00170000) +#define MMAP_PIT3 (CFG_SYS_MBAR + 0x00180000) +#define MMAP_QADC (CFG_SYS_MBAR + 0x00190000) +#define MMAP_GPTMRA (CFG_SYS_MBAR + 0x001A0000) +#define MMAP_GPTMRB (CFG_SYS_MBAR + 0x001B0000) +#define MMAP_CAN (CFG_SYS_MBAR + 0x001C0000) +#define MMAP_CFMC (CFG_SYS_MBAR + 0x001D0000) +#define MMAP_CFMMEM (CFG_SYS_MBAR + 0x04000000) #include <asm/coldfire/eport.h> #include <asm/coldfire/flexbus.h> diff --git a/arch/m68k/include/asm/immap_5301x.h b/arch/m68k/include/asm/immap_5301x.h index 29e60863bf..e1f7858b10 100644 --- a/arch/m68k/include/asm/immap_5301x.h +++ b/arch/m68k/include/asm/immap_5301x.h @@ -9,46 +9,46 @@ #ifndef __IMMAP_5301X__ #define __IMMAP_5301X__ -#define MMAP_SCM1 (CONFIG_SYS_MBAR + 0x00000000) -#define MMAP_XBS (CONFIG_SYS_MBAR + 0x00004000) -#define MMAP_FBCS (CONFIG_SYS_MBAR + 0x00008000) -#define MMAP_MPU (CONFIG_SYS_MBAR + 0x00014000) -#define MMAP_FEC0 (CONFIG_SYS_MBAR + 0x00030000) -#define MMAP_FEC1 (CONFIG_SYS_MBAR + 0x00034000) -#define MMAP_SCM2 (CONFIG_SYS_MBAR + 0x00040000) -#define MMAP_EDMA (CONFIG_SYS_MBAR + 0x00044000) -#define MMAP_INTC0 (CONFIG_SYS_MBAR + 0x00048000) -#define MMAP_INTC1 (CONFIG_SYS_MBAR + 0x0004C000) -#define MMAP_INTCACK (CONFIG_SYS_MBAR + 0x00054000) -#define MMAP_I2C (CONFIG_SYS_MBAR + 0x00058000) -#define MMAP_DSPI (CONFIG_SYS_MBAR + 0x0005C000) -#define MMAP_UART0 (CONFIG_SYS_MBAR + 0x00060000) -#define MMAP_UART1 (CONFIG_SYS_MBAR + 0x00064000) -#define MMAP_UART2 (CONFIG_SYS_MBAR + 0x00068000) -#define MMAP_DTMR0 (CONFIG_SYS_MBAR + 0x00070000) -#define MMAP_DTMR1 (CONFIG_SYS_MBAR + 0x00074000) -#define MMAP_DTMR2 (CONFIG_SYS_MBAR + 0x00078000) -#define MMAP_DTMR3 (CONFIG_SYS_MBAR + 0x0007C000) -#define MMAP_PIT0 (CONFIG_SYS_MBAR + 0x00080000) -#define MMAP_PIT1 (CONFIG_SYS_MBAR + 0x00084000) -#define MMAP_PIT2 (CONFIG_SYS_MBAR + 0x00088000) -#define MMAP_PIT3 (CONFIG_SYS_MBAR + 0x0008C000) -#define MMAP_EPORT0 (CONFIG_SYS_MBAR + 0x00090000) -#define MMAP_EPORT1 (CONFIG_SYS_MBAR + 0x00094000) -#define MMAP_VOICOD (CONFIG_SYS_MBAR + 0x0009C000) -#define MMAP_RCM (CONFIG_SYS_MBAR + 0x000A0000) -#define MMAP_CCM (CONFIG_SYS_MBAR + 0x000A0004) -#define MMAP_GPIO (CONFIG_SYS_MBAR + 0x000A4000) -#define MMAP_RTC (CONFIG_SYS_MBAR + 0x000A8000) -#define MMAP_SIM (CONFIG_SYS_MBAR + 0x000AC000) -#define MMAP_USBOTG (CONFIG_SYS_MBAR + 0x000B0000) -#define MMAP_USBH (CONFIG_SYS_MBAR + 0x000B4000) -#define MMAP_SDRAM (CONFIG_SYS_MBAR + 0x000B8000) -#define MMAP_SSI (CONFIG_SYS_MBAR + 0x000BC000) -#define MMAP_PLL (CONFIG_SYS_MBAR + 0x000C0000) -#define MMAP_RNG (CONFIG_SYS_MBAR + 0x000C4000) -#define MMAP_IIM (CONFIG_SYS_MBAR + 0x000C8000) -#define MMAP_ESDHC (CONFIG_SYS_MBAR + 0x000CC000) +#define MMAP_SCM1 (CFG_SYS_MBAR + 0x00000000) +#define MMAP_XBS (CFG_SYS_MBAR + 0x00004000) +#define MMAP_FBCS (CFG_SYS_MBAR + 0x00008000) +#define MMAP_MPU (CFG_SYS_MBAR + 0x00014000) +#define MMAP_FEC0 (CFG_SYS_MBAR + 0x00030000) +#define MMAP_FEC1 (CFG_SYS_MBAR + 0x00034000) +#define MMAP_SCM2 (CFG_SYS_MBAR + 0x00040000) +#define MMAP_EDMA (CFG_SYS_MBAR + 0x00044000) +#define MMAP_INTC0 (CFG_SYS_MBAR + 0x00048000) +#define MMAP_INTC1 (CFG_SYS_MBAR + 0x0004C000) +#define MMAP_INTCACK (CFG_SYS_MBAR + 0x00054000) +#define MMAP_I2C (CFG_SYS_MBAR + 0x00058000) +#define MMAP_DSPI (CFG_SYS_MBAR + 0x0005C000) +#define MMAP_UART0 (CFG_SYS_MBAR + 0x00060000) +#define MMAP_UART1 (CFG_SYS_MBAR + 0x00064000) +#define MMAP_UART2 (CFG_SYS_MBAR + 0x00068000) +#define MMAP_DTMR0 (CFG_SYS_MBAR + 0x00070000) +#define MMAP_DTMR1 (CFG_SYS_MBAR + 0x00074000) +#define MMAP_DTMR2 (CFG_SYS_MBAR + 0x00078000) +#define MMAP_DTMR3 (CFG_SYS_MBAR + 0x0007C000) +#define MMAP_PIT0 (CFG_SYS_MBAR + 0x00080000) +#define MMAP_PIT1 (CFG_SYS_MBAR + 0x00084000) +#define MMAP_PIT2 (CFG_SYS_MBAR + 0x00088000) +#define MMAP_PIT3 (CFG_SYS_MBAR + 0x0008C000) +#define MMAP_EPORT0 (CFG_SYS_MBAR + 0x00090000) +#define MMAP_EPORT1 (CFG_SYS_MBAR + 0x00094000) +#define MMAP_VOICOD (CFG_SYS_MBAR + 0x0009C000) +#define MMAP_RCM (CFG_SYS_MBAR + 0x000A0000) +#define MMAP_CCM (CFG_SYS_MBAR + 0x000A0004) +#define MMAP_GPIO (CFG_SYS_MBAR + 0x000A4000) +#define MMAP_RTC (CFG_SYS_MBAR + 0x000A8000) +#define MMAP_SIM (CFG_SYS_MBAR + 0x000AC000) +#define MMAP_USBOTG (CFG_SYS_MBAR + 0x000B0000) +#define MMAP_USBH (CFG_SYS_MBAR + 0x000B4000) +#define MMAP_SDRAM (CFG_SYS_MBAR + 0x000B8000) +#define MMAP_SSI (CFG_SYS_MBAR + 0x000BC000) +#define MMAP_PLL (CFG_SYS_MBAR + 0x000C0000) +#define MMAP_RNG (CFG_SYS_MBAR + 0x000C4000) +#define MMAP_IIM (CFG_SYS_MBAR + 0x000C8000) +#define MMAP_ESDHC (CFG_SYS_MBAR + 0x000CC000) #include <asm/coldfire/crossbar.h> #include <asm/coldfire/dspi.h> diff --git a/arch/m68k/include/asm/immap_5307.h b/arch/m68k/include/asm/immap_5307.h index 930e0899e8..d6442d95b4 100644 --- a/arch/m68k/include/asm/immap_5307.h +++ b/arch/m68k/include/asm/immap_5307.h @@ -7,15 +7,15 @@ #ifndef __IMMAP_5307__ #define __IMMAP_5307__ -#define MMAP_SIM (CONFIG_SYS_MBAR + 0x00000000) -#define MMAP_INTC (CONFIG_SYS_MBAR + 0x00000040) -#define MMAP_CSM (CONFIG_SYS_MBAR + 0x00000080) -#define MMAP_DRAMC (CONFIG_SYS_MBAR + 0x00000100) -#define MMAP_DTMR0 (CONFIG_SYS_MBAR + 0x00000140) -#define MMAP_DTMR1 (CONFIG_SYS_MBAR + 0x00000180) -#define MMAP_UART0 (CONFIG_SYS_MBAR + 0x000001C0) -#define MMAP_UART1 (CONFIG_SYS_MBAR + 0x00000200) -#define MMAP_GPIO (CONFIG_SYS_MBAR + 0x00000244) +#define MMAP_SIM (CFG_SYS_MBAR + 0x00000000) +#define MMAP_INTC (CFG_SYS_MBAR + 0x00000040) +#define MMAP_CSM (CFG_SYS_MBAR + 0x00000080) +#define MMAP_DRAMC (CFG_SYS_MBAR + 0x00000100) +#define MMAP_DTMR0 (CFG_SYS_MBAR + 0x00000140) +#define MMAP_DTMR1 (CFG_SYS_MBAR + 0x00000180) +#define MMAP_UART0 (CFG_SYS_MBAR + 0x000001C0) +#define MMAP_UART1 (CFG_SYS_MBAR + 0x00000200) +#define MMAP_GPIO (CFG_SYS_MBAR + 0x00000244) typedef struct sim { u8 rsr; diff --git a/arch/m68k/include/asm/m5249.h b/arch/m68k/include/asm/m5249.h index 9303629e4b..afafb4e547 100644 --- a/arch/m68k/include/asm/m5249.h +++ b/arch/m68k/include/asm/m5249.h @@ -14,14 +14,14 @@ /* * useful definitions for reading/writing MBAR offset memory */ -#define mbar_readLong(x) *((volatile unsigned long *) (CONFIG_SYS_MBAR + x)) -#define mbar_writeLong(x,y) *((volatile unsigned long *) (CONFIG_SYS_MBAR + x)) = y -#define mbar_writeShort(x,y) *((volatile unsigned short *) (CONFIG_SYS_MBAR + x)) = y -#define mbar_writeByte(x,y) *((volatile unsigned char *) (CONFIG_SYS_MBAR + x)) = y -#define mbar2_readLong(x) *((volatile unsigned long *) (CONFIG_SYS_MBAR2 + x)) -#define mbar2_writeLong(x,y) *((volatile unsigned long *) (CONFIG_SYS_MBAR2 + x)) = y -#define mbar2_writeShort(x,y) *((volatile unsigned short *) (CONFIG_SYS_MBAR2 + x)) = y -#define mbar2_writeByte(x,y) *((volatile unsigned char *) (CONFIG_SYS_MBAR2 + x)) = y +#define mbar_readLong(x) *((volatile unsigned long *) (CFG_SYS_MBAR + x)) +#define mbar_writeLong(x,y) *((volatile unsigned long *) (CFG_SYS_MBAR + x)) = y +#define mbar_writeShort(x,y) *((volatile unsigned short *) (CFG_SYS_MBAR + x)) = y +#define mbar_writeByte(x,y) *((volatile unsigned char *) (CFG_SYS_MBAR + x)) = y +#define mbar2_readLong(x) *((volatile unsigned long *) (CFG_SYS_MBAR2 + x)) +#define mbar2_writeLong(x,y) *((volatile unsigned long *) (CFG_SYS_MBAR2 + x)) = y +#define mbar2_writeShort(x,y) *((volatile unsigned short *) (CFG_SYS_MBAR2 + x)) = y +#define mbar2_writeByte(x,y) *((volatile unsigned char *) (CFG_SYS_MBAR2 + x)) = y /* * Size of internal RAM diff --git a/arch/m68k/include/asm/m5271.h b/arch/m68k/include/asm/m5271.h index 7ebeddbb68..e63b42c00d 100644 --- a/arch/m68k/include/asm/m5271.h +++ b/arch/m68k/include/asm/m5271.h @@ -11,12 +11,12 @@ #ifndef _MCF5271_H_ #define _MCF5271_H_ -#define mbar_readLong(x) *((volatile unsigned long *) (CONFIG_SYS_MBAR + x)) -#define mbar_readShort(x) *((volatile unsigned short *) (CONFIG_SYS_MBAR + x)) -#define mbar_readByte(x) *((volatile unsigned char *) (CONFIG_SYS_MBAR + x)) -#define mbar_writeLong(x,y) *((volatile unsigned long *) (CONFIG_SYS_MBAR + x)) = y -#define mbar_writeShort(x,y) *((volatile unsigned short *) (CONFIG_SYS_MBAR + x)) = y -#define mbar_writeByte(x,y) *((volatile unsigned char *) (CONFIG_SYS_MBAR + x)) = y +#define mbar_readLong(x) *((volatile unsigned long *) (CFG_SYS_MBAR + x)) +#define mbar_readShort(x) *((volatile unsigned short *) (CFG_SYS_MBAR + x)) +#define mbar_readByte(x) *((volatile unsigned char *) (CFG_SYS_MBAR + x)) +#define mbar_writeLong(x,y) *((volatile unsigned long *) (CFG_SYS_MBAR + x)) = y +#define mbar_writeShort(x,y) *((volatile unsigned short *) (CFG_SYS_MBAR + x)) = y +#define mbar_writeByte(x,y) *((volatile unsigned char *) (CFG_SYS_MBAR + x)) = y #define MCF_FMPLL_SYNCR 0x120000 #define MCF_FMPLL_SYNSR 0x120004 diff --git a/arch/m68k/include/asm/m5282.h b/arch/m68k/include/asm/m5282.h index 0c91cf491e..180f20386f 100644 --- a/arch/m68k/include/asm/m5282.h +++ b/arch/m68k/include/asm/m5282.h @@ -108,112 +108,112 @@ /* General Purpose I/O Module GPIO */ -#define MCFGPIO_PORTA (*(vu_char *) (CONFIG_SYS_MBAR+0x100000)) -#define MCFGPIO_PORTB (*(vu_char *) (CONFIG_SYS_MBAR+0x100001)) -#define MCFGPIO_PORTC (*(vu_char *) (CONFIG_SYS_MBAR+0x100002)) -#define MCFGPIO_PORTD (*(vu_char *) (CONFIG_SYS_MBAR+0x100003)) -#define MCFGPIO_PORTE (*(vu_char *) (CONFIG_SYS_MBAR+0x100004)) -#define MCFGPIO_PORTF (*(vu_char *) (CONFIG_SYS_MBAR+0x100005)) -#define MCFGPIO_PORTG (*(vu_char *) (CONFIG_SYS_MBAR+0x100006)) -#define MCFGPIO_PORTH (*(vu_char *) (CONFIG_SYS_MBAR+0x100007)) -#define MCFGPIO_PORTJ (*(vu_char *) (CONFIG_SYS_MBAR+0x100008)) -#define MCFGPIO_PORTDD (*(vu_char *) (CONFIG_SYS_MBAR+0x100009)) -#define MCFGPIO_PORTEH (*(vu_char *) (CONFIG_SYS_MBAR+0x10000A)) -#define MCFGPIO_PORTEL (*(vu_char *) (CONFIG_SYS_MBAR+0x10000B)) -#define MCFGPIO_PORTAS (*(vu_char *) (CONFIG_SYS_MBAR+0x10000C)) -#define MCFGPIO_PORTQS (*(vu_char *) (CONFIG_SYS_MBAR+0x10000D)) -#define MCFGPIO_PORTSD (*(vu_char *) (CONFIG_SYS_MBAR+0x10000E)) -#define MCFGPIO_PORTTC (*(vu_char *) (CONFIG_SYS_MBAR+0x10000F)) -#define MCFGPIO_PORTTD (*(vu_char *) (CONFIG_SYS_MBAR+0x100010)) -#define MCFGPIO_PORTUA (*(vu_char *) (CONFIG_SYS_MBAR+0x100011)) - -#define MCFGPIO_DDRA (*(vu_char *) (CONFIG_SYS_MBAR+0x100014)) -#define MCFGPIO_DDRB (*(vu_char *) (CONFIG_SYS_MBAR+0x100015)) -#define MCFGPIO_DDRC (*(vu_char *) (CONFIG_SYS_MBAR+0x100016)) -#define MCFGPIO_DDRD (*(vu_char *) (CONFIG_SYS_MBAR+0x100017)) -#define MCFGPIO_DDRE (*(vu_char *) (CONFIG_SYS_MBAR+0x100018)) -#define MCFGPIO_DDRF (*(vu_char *) (CONFIG_SYS_MBAR+0x100019)) -#define MCFGPIO_DDRG (*(vu_char *) (CONFIG_SYS_MBAR+0x10001A)) -#define MCFGPIO_DDRH (*(vu_char *) (CONFIG_SYS_MBAR+0x10001B)) -#define MCFGPIO_DDRJ (*(vu_char *) (CONFIG_SYS_MBAR+0x10001C)) -#define MCFGPIO_DDRDD (*(vu_char *) (CONFIG_SYS_MBAR+0x10001D)) -#define MCFGPIO_DDREH (*(vu_char *) (CONFIG_SYS_MBAR+0x10001E)) -#define MCFGPIO_DDREL (*(vu_char *) (CONFIG_SYS_MBAR+0x10001F)) -#define MCFGPIO_DDRAS (*(vu_char *) (CONFIG_SYS_MBAR+0x100020)) -#define MCFGPIO_DDRQS (*(vu_char *) (CONFIG_SYS_MBAR+0x100021)) -#define MCFGPIO_DDRSD (*(vu_char *) (CONFIG_SYS_MBAR+0x100022)) -#define MCFGPIO_DDRTC (*(vu_char *) (CONFIG_SYS_MBAR+0x100023)) -#define MCFGPIO_DDRTD (*(vu_char *) (CONFIG_SYS_MBAR+0x100024)) -#define MCFGPIO_DDRUA (*(vu_char *) (CONFIG_SYS_MBAR+0x100025)) - -#define MCFGPIO_PORTAP (*(vu_char *) (CONFIG_SYS_MBAR+0x100028)) -#define MCFGPIO_PORTBP (*(vu_char *) (CONFIG_SYS_MBAR+0x100029)) -#define MCFGPIO_PORTCP (*(vu_char *) (CONFIG_SYS_MBAR+0x10002A)) -#define MCFGPIO_PORTDP (*(vu_char *) (CONFIG_SYS_MBAR+0x10002B)) -#define MCFGPIO_PORTEP (*(vu_char *) (CONFIG_SYS_MBAR+0x10002C)) -#define MCFGPIO_PORTFP (*(vu_char *) (CONFIG_SYS_MBAR+0x10002D)) -#define MCFGPIO_PORTGP (*(vu_char *) (CONFIG_SYS_MBAR+0x10002E)) -#define MCFGPIO_PORTHP (*(vu_char *) (CONFIG_SYS_MBAR+0x10002F)) -#define MCFGPIO_PORTJP (*(vu_char *) (CONFIG_SYS_MBAR+0x100030)) -#define MCFGPIO_PORTDDP (*(vu_char *) (CONFIG_SYS_MBAR+0x100031)) -#define MCFGPIO_PORTEHP (*(vu_char *) (CONFIG_SYS_MBAR+0x100032)) -#define MCFGPIO_PORTELP (*(vu_char *) (CONFIG_SYS_MBAR+0x100033)) -#define MCFGPIO_PORTASP (*(vu_char *) (CONFIG_SYS_MBAR+0x100034)) -#define MCFGPIO_PORTQSP (*(vu_char *) (CONFIG_SYS_MBAR+0x100035)) -#define MCFGPIO_PORTSDP (*(vu_char *) (CONFIG_SYS_MBAR+0x100036)) -#define MCFGPIO_PORTTCP (*(vu_char *) (CONFIG_SYS_MBAR+0x100037)) -#define MCFGPIO_PORTTDP (*(vu_char *) (CONFIG_SYS_MBAR+0x100038)) -#define MCFGPIO_PORTUAP (*(vu_char *) (CONFIG_SYS_MBAR+0x100039)) - -#define MCFGPIO_SETA (*(vu_char *) (CONFIG_SYS_MBAR+0x100028)) -#define MCFGPIO_SETB (*(vu_char *) (CONFIG_SYS_MBAR+0x100029)) -#define MCFGPIO_SETC (*(vu_char *) (CONFIG_SYS_MBAR+0x10002A)) -#define MCFGPIO_SETD (*(vu_char *) (CONFIG_SYS_MBAR+0x10002B)) -#define MCFGPIO_SETE (*(vu_char *) (CONFIG_SYS_MBAR+0x10002C)) -#define MCFGPIO_SETF (*(vu_char *) (CONFIG_SYS_MBAR+0x10002D)) -#define MCFGPIO_SETG (*(vu_char *) (CONFIG_SYS_MBAR+0x10002E)) -#define MCFGPIO_SETH (*(vu_char *) (CONFIG_SYS_MBAR+0x10002F)) -#define MCFGPIO_SETJ (*(vu_char *) (CONFIG_SYS_MBAR+0x100030)) -#define MCFGPIO_SETDD (*(vu_char *) (CONFIG_SYS_MBAR+0x100031)) -#define MCFGPIO_SETEH (*(vu_char *) (CONFIG_SYS_MBAR+0x100032)) -#define MCFGPIO_SETEL (*(vu_char *) (CONFIG_SYS_MBAR+0x100033)) -#define MCFGPIO_SETAS (*(vu_char *) (CONFIG_SYS_MBAR+0x100034)) -#define MCFGPIO_SETQS (*(vu_char *) (CONFIG_SYS_MBAR+0x100035)) -#define MCFGPIO_SETSD (*(vu_char *) (CONFIG_SYS_MBAR+0x100036)) -#define MCFGPIO_SETTC (*(vu_char *) (CONFIG_SYS_MBAR+0x100037)) -#define MCFGPIO_SETTD (*(vu_char *) (CONFIG_SYS_MBAR+0x100038)) -#define MCFGPIO_SETUA (*(vu_char *) (CONFIG_SYS_MBAR+0x100039)) - -#define MCFGPIO_CLRA (*(vu_char *) (CONFIG_SYS_MBAR+0x10003C)) -#define MCFGPIO_CLRB (*(vu_char *) (CONFIG_SYS_MBAR+0x10003D)) -#define MCFGPIO_CLRC (*(vu_char *) (CONFIG_SYS_MBAR+0x10003E)) -#define MCFGPIO_CLRD (*(vu_char *) (CONFIG_SYS_MBAR+0x10003F)) -#define MCFGPIO_CLRE (*(vu_char *) (CONFIG_SYS_MBAR+0x100040)) -#define MCFGPIO_CLRF (*(vu_char *) (CONFIG_SYS_MBAR+0x100041)) -#define MCFGPIO_CLRG (*(vu_char *) (CONFIG_SYS_MBAR+0x100042)) -#define MCFGPIO_CLRH (*(vu_char *) (CONFIG_SYS_MBAR+0x100043)) -#define MCFGPIO_CLRJ (*(vu_char *) (CONFIG_SYS_MBAR+0x100044)) -#define MCFGPIO_CLRDD (*(vu_char *) (CONFIG_SYS_MBAR+0x100045)) -#define MCFGPIO_CLREH (*(vu_char *) (CONFIG_SYS_MBAR+0x100046)) -#define MCFGPIO_CLREL (*(vu_char *) (CONFIG_SYS_MBAR+0x100047)) -#define MCFGPIO_CLRAS (*(vu_char *) (CONFIG_SYS_MBAR+0x100048)) -#define MCFGPIO_CLRQS (*(vu_char *) (CONFIG_SYS_MBAR+0x100049)) -#define MCFGPIO_CLRSD (*(vu_char *) (CONFIG_SYS_MBAR+0x10004A)) -#define MCFGPIO_CLRTC (*(vu_char *) (CONFIG_SYS_MBAR+0x10004B)) -#define MCFGPIO_CLRTD (*(vu_char *) (CONFIG_SYS_MBAR+0x10004C)) -#define MCFGPIO_CLRUA (*(vu_char *) (CONFIG_SYS_MBAR+0x10004D)) - -#define MCFGPIO_PBCDPAR (*(vu_char *) (CONFIG_SYS_MBAR+0x100050)) -#define MCFGPIO_PFPAR (*(vu_char *) (CONFIG_SYS_MBAR+0x100051)) -#define MCFGPIO_PEPAR (*(vu_short *)(CONFIG_SYS_MBAR+0x100052)) -#define MCFGPIO_PJPAR (*(vu_char *) (CONFIG_SYS_MBAR+0x100054)) -#define MCFGPIO_PSDPAR (*(vu_char *) (CONFIG_SYS_MBAR+0x100055)) -#define MCFGPIO_PASPAR (*(vu_short *)(CONFIG_SYS_MBAR+0x100056)) -#define MCFGPIO_PEHLPAR (*(vu_char *) (CONFIG_SYS_MBAR+0x100058)) -#define MCFGPIO_PQSPAR (*(vu_char *) (CONFIG_SYS_MBAR+0x100059)) -#define MCFGPIO_PTCPAR (*(vu_char *) (CONFIG_SYS_MBAR+0x10005A)) -#define MCFGPIO_PTDPAR (*(vu_char *) (CONFIG_SYS_MBAR+0x10005B)) -#define MCFGPIO_PUAPAR (*(vu_char *) (CONFIG_SYS_MBAR+0x10005C)) +#define MCFGPIO_PORTA (*(vu_char *) (CFG_SYS_MBAR+0x100000)) +#define MCFGPIO_PORTB (*(vu_char *) (CFG_SYS_MBAR+0x100001)) +#define MCFGPIO_PORTC (*(vu_char *) (CFG_SYS_MBAR+0x100002)) +#define MCFGPIO_PORTD (*(vu_char *) (CFG_SYS_MBAR+0x100003)) +#define MCFGPIO_PORTE (*(vu_char *) (CFG_SYS_MBAR+0x100004)) +#define MCFGPIO_PORTF (*(vu_char *) (CFG_SYS_MBAR+0x100005)) +#define MCFGPIO_PORTG (*(vu_char *) (CFG_SYS_MBAR+0x100006)) +#define MCFGPIO_PORTH (*(vu_char *) (CFG_SYS_MBAR+0x100007)) +#define MCFGPIO_PORTJ (*(vu_char *) (CFG_SYS_MBAR+0x100008)) +#define MCFGPIO_PORTDD (*(vu_char *) (CFG_SYS_MBAR+0x100009)) +#define MCFGPIO_PORTEH (*(vu_char *) (CFG_SYS_MBAR+0x10000A)) +#define MCFGPIO_PORTEL (*(vu_char *) (CFG_SYS_MBAR+0x10000B)) +#define MCFGPIO_PORTAS (*(vu_char *) (CFG_SYS_MBAR+0x10000C)) +#define MCFGPIO_PORTQS (*(vu_char *) (CFG_SYS_MBAR+0x10000D)) +#define MCFGPIO_PORTSD (*(vu_char *) (CFG_SYS_MBAR+0x10000E)) +#define MCFGPIO_PORTTC (*(vu_char *) (CFG_SYS_MBAR+0x10000F)) +#define MCFGPIO_PORTTD (*(vu_char *) (CFG_SYS_MBAR+0x100010)) +#define MCFGPIO_PORTUA (*(vu_char *) (CFG_SYS_MBAR+0x100011)) + +#define MCFGPIO_DDRA (*(vu_char *) (CFG_SYS_MBAR+0x100014)) +#define MCFGPIO_DDRB (*(vu_char *) (CFG_SYS_MBAR+0x100015)) +#define MCFGPIO_DDRC (*(vu_char *) (CFG_SYS_MBAR+0x100016)) +#define MCFGPIO_DDRD (*(vu_char *) (CFG_SYS_MBAR+0x100017)) +#define MCFGPIO_DDRE (*(vu_char *) (CFG_SYS_MBAR+0x100018)) +#define MCFGPIO_DDRF (*(vu_char *) (CFG_SYS_MBAR+0x100019)) +#define MCFGPIO_DDRG (*(vu_char *) (CFG_SYS_MBAR+0x10001A)) +#define MCFGPIO_DDRH (*(vu_char *) (CFG_SYS_MBAR+0x10001B)) +#define MCFGPIO_DDRJ (*(vu_char *) (CFG_SYS_MBAR+0x10001C)) +#define MCFGPIO_DDRDD (*(vu_char *) (CFG_SYS_MBAR+0x10001D)) +#define MCFGPIO_DDREH (*(vu_char *) (CFG_SYS_MBAR+0x10001E)) +#define MCFGPIO_DDREL (*(vu_char *) (CFG_SYS_MBAR+0x10001F)) +#define MCFGPIO_DDRAS (*(vu_char *) (CFG_SYS_MBAR+0x100020)) +#define MCFGPIO_DDRQS (*(vu_char *) (CFG_SYS_MBAR+0x100021)) +#define MCFGPIO_DDRSD (*(vu_char *) (CFG_SYS_MBAR+0x100022)) +#define MCFGPIO_DDRTC (*(vu_char *) (CFG_SYS_MBAR+0x100023)) +#define MCFGPIO_DDRTD (*(vu_char *) (CFG_SYS_MBAR+0x100024)) +#define MCFGPIO_DDRUA (*(vu_char *) (CFG_SYS_MBAR+0x100025)) + +#define MCFGPIO_PORTAP (*(vu_char *) (CFG_SYS_MBAR+0x100028)) +#define MCFGPIO_PORTBP (*(vu_char *) (CFG_SYS_MBAR+0x100029)) +#define MCFGPIO_PORTCP (*(vu_char *) (CFG_SYS_MBAR+0x10002A)) +#define MCFGPIO_PORTDP (*(vu_char *) (CFG_SYS_MBAR+0x10002B)) +#define MCFGPIO_PORTEP (*(vu_char *) (CFG_SYS_MBAR+0x10002C)) +#define MCFGPIO_PORTFP (*(vu_char *) (CFG_SYS_MBAR+0x10002D)) +#define MCFGPIO_PORTGP (*(vu_char *) (CFG_SYS_MBAR+0x10002E)) +#define MCFGPIO_PORTHP (*(vu_char *) (CFG_SYS_MBAR+0x10002F)) +#define MCFGPIO_PORTJP (*(vu_char *) (CFG_SYS_MBAR+0x100030)) +#define MCFGPIO_PORTDDP (*(vu_char *) (CFG_SYS_MBAR+0x100031)) +#define MCFGPIO_PORTEHP (*(vu_char *) (CFG_SYS_MBAR+0x100032)) +#define MCFGPIO_PORTELP (*(vu_char *) (CFG_SYS_MBAR+0x100033)) +#define MCFGPIO_PORTASP (*(vu_char *) (CFG_SYS_MBAR+0x100034)) +#define MCFGPIO_PORTQSP (*(vu_char *) (CFG_SYS_MBAR+0x100035)) +#define MCFGPIO_PORTSDP (*(vu_char *) (CFG_SYS_MBAR+0x100036)) +#define MCFGPIO_PORTTCP (*(vu_char *) (CFG_SYS_MBAR+0x100037)) +#define MCFGPIO_PORTTDP (*(vu_char *) (CFG_SYS_MBAR+0x100038)) +#define MCFGPIO_PORTUAP (*(vu_char *) (CFG_SYS_MBAR+0x100039)) + +#define MCFGPIO_SETA (*(vu_char *) (CFG_SYS_MBAR+0x100028)) +#define MCFGPIO_SETB (*(vu_char *) (CFG_SYS_MBAR+0x100029)) +#define MCFGPIO_SETC (*(vu_char *) (CFG_SYS_MBAR+0x10002A)) +#define MCFGPIO_SETD (*(vu_char *) (CFG_SYS_MBAR+0x10002B)) +#define MCFGPIO_SETE (*(vu_char *) (CFG_SYS_MBAR+0x10002C)) +#define MCFGPIO_SETF (*(vu_char *) (CFG_SYS_MBAR+0x10002D)) +#define MCFGPIO_SETG (*(vu_char *) (CFG_SYS_MBAR+0x10002E)) +#define MCFGPIO_SETH (*(vu_char *) (CFG_SYS_MBAR+0x10002F)) +#define MCFGPIO_SETJ (*(vu_char *) (CFG_SYS_MBAR+0x100030)) +#define MCFGPIO_SETDD (*(vu_char *) (CFG_SYS_MBAR+0x100031)) +#define MCFGPIO_SETEH (*(vu_char *) (CFG_SYS_MBAR+0x100032)) +#define MCFGPIO_SETEL (*(vu_char *) (CFG_SYS_MBAR+0x100033)) +#define MCFGPIO_SETAS (*(vu_char *) (CFG_SYS_MBAR+0x100034)) +#define MCFGPIO_SETQS (*(vu_char *) (CFG_SYS_MBAR+0x100035)) +#define MCFGPIO_SETSD (*(vu_char *) (CFG_SYS_MBAR+0x100036)) +#define MCFGPIO_SETTC (*(vu_char *) (CFG_SYS_MBAR+0x100037)) +#define MCFGPIO_SETTD (*(vu_char *) (CFG_SYS_MBAR+0x100038)) +#define MCFGPIO_SETUA (*(vu_char *) (CFG_SYS_MBAR+0x100039)) + +#define MCFGPIO_CLRA (*(vu_char *) (CFG_SYS_MBAR+0x10003C)) +#define MCFGPIO_CLRB (*(vu_char *) (CFG_SYS_MBAR+0x10003D)) +#define MCFGPIO_CLRC (*(vu_char *) (CFG_SYS_MBAR+0x10003E)) +#define MCFGPIO_CLRD (*(vu_char *) (CFG_SYS_MBAR+0x10003F)) +#define MCFGPIO_CLRE (*(vu_char *) (CFG_SYS_MBAR+0x100040)) +#define MCFGPIO_CLRF (*(vu_char *) (CFG_SYS_MBAR+0x100041)) +#define MCFGPIO_CLRG (*(vu_char *) (CFG_SYS_MBAR+0x100042)) +#define MCFGPIO_CLRH (*(vu_char *) (CFG_SYS_MBAR+0x100043)) +#define MCFGPIO_CLRJ (*(vu_char *) (CFG_SYS_MBAR+0x100044)) +#define MCFGPIO_CLRDD (*(vu_char *) (CFG_SYS_MBAR+0x100045)) +#define MCFGPIO_CLREH (*(vu_char *) (CFG_SYS_MBAR+0x100046)) +#define MCFGPIO_CLREL (*(vu_char *) (CFG_SYS_MBAR+0x100047)) +#define MCFGPIO_CLRAS (*(vu_char *) (CFG_SYS_MBAR+0x100048)) +#define MCFGPIO_CLRQS (*(vu_char *) (CFG_SYS_MBAR+0x100049)) +#define MCFGPIO_CLRSD (*(vu_char *) (CFG_SYS_MBAR+0x10004A)) +#define MCFGPIO_CLRTC (*(vu_char *) (CFG_SYS_MBAR+0x10004B)) +#define MCFGPIO_CLRTD (*(vu_char *) (CFG_SYS_MBAR+0x10004C)) +#define MCFGPIO_CLRUA (*(vu_char *) (CFG_SYS_MBAR+0x10004D)) + +#define MCFGPIO_PBCDPAR (*(vu_char *) (CFG_SYS_MBAR+0x100050)) +#define MCFGPIO_PFPAR (*(vu_char *) (CFG_SYS_MBAR+0x100051)) +#define MCFGPIO_PEPAR (*(vu_short *)(CFG_SYS_MBAR+0x100052)) +#define MCFGPIO_PJPAR (*(vu_char *) (CFG_SYS_MBAR+0x100054)) +#define MCFGPIO_PSDPAR (*(vu_char *) (CFG_SYS_MBAR+0x100055)) +#define MCFGPIO_PASPAR (*(vu_short *)(CFG_SYS_MBAR+0x100056)) +#define MCFGPIO_PEHLPAR (*(vu_char *) (CFG_SYS_MBAR+0x100058)) +#define MCFGPIO_PQSPAR (*(vu_char *) (CFG_SYS_MBAR+0x100059)) +#define MCFGPIO_PTCPAR (*(vu_char *) (CFG_SYS_MBAR+0x10005A)) +#define MCFGPIO_PTDPAR (*(vu_char *) (CFG_SYS_MBAR+0x10005B)) +#define MCFGPIO_PUAPAR (*(vu_char *) (CFG_SYS_MBAR+0x10005C)) /* Bit level definitions and macros */ #define MCFGPIO_PORT7 (0x80) @@ -310,25 +310,25 @@ /* System Conrol Module SCM */ -#define MCFSCM_RAMBAR (*(vu_long *) (CONFIG_SYS_MBAR+0x00000008)) -#define MCFSCM_CRSR (*(vu_char *) (CONFIG_SYS_MBAR+0x00000010)) -#define MCFSCM_CWCR (*(vu_char *) (CONFIG_SYS_MBAR+0x00000011)) -#define MCFSCM_LPICR (*(vu_char *) (CONFIG_SYS_MBAR+0x00000012)) -#define MCFSCM_CWSR (*(vu_char *) (CONFIG_SYS_MBAR+0x00000013)) - -#define MCFSCM_MPARK (*(vu_long *) (CONFIG_SYS_MBAR+0x0000001C)) -#define MCFSCM_MPR (*(vu_char *) (CONFIG_SYS_MBAR+0x00000020)) -#define MCFSCM_PACR0 (*(vu_char *) (CONFIG_SYS_MBAR+0x00000024)) -#define MCFSCM_PACR1 (*(vu_char *) (CONFIG_SYS_MBAR+0x00000025)) -#define MCFSCM_PACR2 (*(vu_char *) (CONFIG_SYS_MBAR+0x00000026)) -#define MCFSCM_PACR3 (*(vu_char *) (CONFIG_SYS_MBAR+0x00000027)) -#define MCFSCM_PACR4 (*(vu_char *) (CONFIG_SYS_MBAR+0x00000028)) -#define MCFSCM_PACR5 (*(vu_char *) (CONFIG_SYS_MBAR+0x0000002A)) -#define MCFSCM_PACR6 (*(vu_char *) (CONFIG_SYS_MBAR+0x0000002B)) -#define MCFSCM_PACR7 (*(vu_char *) (CONFIG_SYS_MBAR+0x0000002C)) -#define MCFSCM_PACR8 (*(vu_char *) (CONFIG_SYS_MBAR+0x0000002E)) -#define MCFSCM_GPACR0 (*(vu_char *) (CONFIG_SYS_MBAR+0x00000030)) -#define MCFSCM_GPACR1 (*(vu_char *) (CONFIG_SYS_MBAR+0x00000031)) +#define MCFSCM_RAMBAR (*(vu_long *) (CFG_SYS_MBAR+0x00000008)) +#define MCFSCM_CRSR (*(vu_char *) (CFG_SYS_MBAR+0x00000010)) +#define MCFSCM_CWCR (*(vu_char *) (CFG_SYS_MBAR+0x00000011)) +#define MCFSCM_LPICR (*(vu_char *) (CFG_SYS_MBAR+0x00000012)) +#define MCFSCM_CWSR (*(vu_char *) (CFG_SYS_MBAR+0x00000013)) + +#define MCFSCM_MPARK (*(vu_long *) (CFG_SYS_MBAR+0x0000001C)) +#define MCFSCM_MPR (*(vu_char *) (CFG_SYS_MBAR+0x00000020)) +#define MCFSCM_PACR0 (*(vu_char *) (CFG_SYS_MBAR+0x00000024)) +#define MCFSCM_PACR1 (*(vu_char *) (CFG_SYS_MBAR+0x00000025)) +#define MCFSCM_PACR2 (*(vu_char *) (CFG_SYS_MBAR+0x00000026)) +#define MCFSCM_PACR3 (*(vu_char *) (CFG_SYS_MBAR+0x00000027)) +#define MCFSCM_PACR4 (*(vu_char *) (CFG_SYS_MBAR+0x00000028)) +#define MCFSCM_PACR5 (*(vu_char *) (CFG_SYS_MBAR+0x0000002A)) +#define MCFSCM_PACR6 (*(vu_char *) (CFG_SYS_MBAR+0x0000002B)) +#define MCFSCM_PACR7 (*(vu_char *) (CFG_SYS_MBAR+0x0000002C)) +#define MCFSCM_PACR8 (*(vu_char *) (CFG_SYS_MBAR+0x0000002E)) +#define MCFSCM_GPACR0 (*(vu_char *) (CFG_SYS_MBAR+0x00000030)) +#define MCFSCM_GPACR1 (*(vu_char *) (CFG_SYS_MBAR+0x00000031)) #define MCFSCM_CRSR_EXT (0x80) #define MCFSCM_CRSR_CWDR (0x20) @@ -337,8 +337,8 @@ /* Reset Controller Module RCM */ -#define MCFRESET_RCR (*(vu_char *) (CONFIG_SYS_MBAR+0x00110000)) -#define MCFRESET_RSR (*(vu_char *) (CONFIG_SYS_MBAR+0x00110001)) +#define MCFRESET_RCR (*(vu_char *) (CFG_SYS_MBAR+0x00110000)) +#define MCFRESET_RSR (*(vu_char *) (CFG_SYS_MBAR+0x00110001)) #define MCFRESET_RCR_SOFTRST (0x80) #define MCFRESET_RCR_FRCRSTOUT (0x40) @@ -360,9 +360,9 @@ /* Chip Configuration Module CCM */ -#define MCFCCM_CCR (*(vu_short *)(CONFIG_SYS_MBAR+0x00110004)) -#define MCFCCM_RCON (*(vu_short *)(CONFIG_SYS_MBAR+0x00110008)) -#define MCFCCM_CIR (*(vu_short *)(CONFIG_SYS_MBAR+0x0011000A)) +#define MCFCCM_CCR (*(vu_short *)(CFG_SYS_MBAR+0x00110004)) +#define MCFCCM_RCON (*(vu_short *)(CFG_SYS_MBAR+0x00110008)) +#define MCFCCM_CIR (*(vu_short *)(CFG_SYS_MBAR+0x0011000A)) /* Bit level definitions and macros */ #define MCFCCM_CCR_LOAD (0x8000) @@ -377,18 +377,18 @@ /* Clock Module */ -#define MCFCLOCK_SYNCR (*(vu_short *)(CONFIG_SYS_MBAR+0x120000)) -#define MCFCLOCK_SYNSR (*(vu_char *) (CONFIG_SYS_MBAR+0x120002)) +#define MCFCLOCK_SYNCR (*(vu_short *)(CFG_SYS_MBAR+0x120000)) +#define MCFCLOCK_SYNSR (*(vu_char *) (CFG_SYS_MBAR+0x120002)) #define MCFCLOCK_SYNCR_MFD(x) (((x)&0x0007)<<12) #define MCFCLOCK_SYNCR_RFD(x) (((x)&0x0007)<<8) #define MCFCLOCK_SYNSR_LOCK 0x08 -#define MCFSDRAMC_DCR (*(vu_short *)(CONFIG_SYS_MBAR+0x00000040)) -#define MCFSDRAMC_DACR0 (*(vu_long *) (CONFIG_SYS_MBAR+0x00000048)) -#define MCFSDRAMC_DMR0 (*(vu_long *) (CONFIG_SYS_MBAR+0x0000004c)) -#define MCFSDRAMC_DACR1 (*(vu_long *) (CONFIG_SYS_MBAR+0x00000050)) -#define MCFSDRAMC_DMR1 (*(vu_long *) (CONFIG_SYS_MBAR+0x00000054)) +#define MCFSDRAMC_DCR (*(vu_short *)(CFG_SYS_MBAR+0x00000040)) +#define MCFSDRAMC_DACR0 (*(vu_long *) (CFG_SYS_MBAR+0x00000048)) +#define MCFSDRAMC_DMR0 (*(vu_long *) (CFG_SYS_MBAR+0x0000004c)) +#define MCFSDRAMC_DACR1 (*(vu_long *) (CFG_SYS_MBAR+0x00000050)) +#define MCFSDRAMC_DMR1 (*(vu_long *) (CFG_SYS_MBAR+0x00000054)) #define MCFSDRAMC_DCR_NAM (0x2000) #define MCFSDRAMC_DCR_COC (0x1000) @@ -418,60 +418,60 @@ #define MCFSDRAMC_DMR_UD (0x00000002) #define MCFSDRAMC_DMR_V (0x00000001) -#define MCFWTM_WCR (*(vu_short *)(CONFIG_SYS_MBAR+0x00140000)) -#define MCFWTM_WMR (*(vu_short *)(CONFIG_SYS_MBAR+0x00140002)) -#define MCFWTM_WCNTR (*(vu_short *)(CONFIG_SYS_MBAR+0x00140004)) -#define MCFWTM_WSR (*(vu_short *)(CONFIG_SYS_MBAR+0x00140006)) +#define MCFWTM_WCR (*(vu_short *)(CFG_SYS_MBAR+0x00140000)) +#define MCFWTM_WMR (*(vu_short *)(CFG_SYS_MBAR+0x00140002)) +#define MCFWTM_WCNTR (*(vu_short *)(CFG_SYS_MBAR+0x00140004)) +#define MCFWTM_WSR (*(vu_short *)(CFG_SYS_MBAR+0x00140006)) /********************************************************************* * General Purpose Timer (GPT) Module *********************************************************************/ -#define MCFGPTA_GPTIOS (*(vu_char *)(CONFIG_SYS_MBAR+0x1A0000)) -#define MCFGPTA_GPTCFORC (*(vu_char *)(CONFIG_SYS_MBAR+0x1A0001)) -#define MCFGPTA_GPTOC3M (*(vu_char *)(CONFIG_SYS_MBAR+0x1A0002)) -#define MCFGPTA_GPTOC3D (*(vu_char *)(CONFIG_SYS_MBAR+0x1A0003)) -#define MCFGPTA_GPTCNT (*(vu_short *)(CONFIG_SYS_MBAR+0x1A0004)) -#define MCFGPTA_GPTSCR1 (*(vu_char *)(CONFIG_SYS_MBAR+0x1A0006)) -#define MCFGPTA_GPTTOV (*(vu_char *)(CONFIG_SYS_MBAR+0x1A0008)) -#define MCFGPTA_GPTCTL1 (*(vu_char *)(CONFIG_SYS_MBAR+0x1A0009)) -#define MCFGPTA_GPTCTL2 (*(vu_char *)(CONFIG_SYS_MBAR+0x1A000B)) -#define MCFGPTA_GPTIE (*(vu_char *)(CONFIG_SYS_MBAR+0x1A000C)) -#define MCFGPTA_GPTSCR2 (*(vu_char *)(CONFIG_SYS_MBAR+0x1A000D)) -#define MCFGPTA_GPTFLG1 (*(vu_char *)(CONFIG_SYS_MBAR+0x1A000E)) -#define MCFGPTA_GPTFLG2 (*(vu_char *)(CONFIG_SYS_MBAR+0x1A000F)) -#define MCFGPTA_GPTC0 (*(vu_short *)(CONFIG_SYS_MBAR+0x1A0010)) -#define MCFGPTA_GPTC1 (*(vu_short *)(CONFIG_SYS_MBAR+0x1A0012)) -#define MCFGPTA_GPTC2 (*(vu_short *)(CONFIG_SYS_MBAR+0x1A0014)) -#define MCFGPTA_GPTC3 (*(vu_short *)(CONFIG_SYS_MBAR+0x1A0016)) -#define MCFGPTA_GPTPACTL (*(vu_char *)(CONFIG_SYS_MBAR+0x1A0018)) -#define MCFGPTA_GPTPAFLG (*(vu_char *)(CONFIG_SYS_MBAR+0x1A0019)) -#define MCFGPTA_GPTPACNT (*(vu_short *)(CONFIG_SYS_MBAR+0x1A001A)) -#define MCFGPTA_GPTPORT (*(vu_char *)(CONFIG_SYS_MBAR+0x1A001D)) -#define MCFGPTA_GPTDDR (*(vu_char *)(CONFIG_SYS_MBAR+0x1A001E)) - -#define MCFGPTB_GPTIOS (*(vu_char *)(CONFIG_SYS_MBAR+0x1B0000)) -#define MCFGPTB_GPTCFORC (*(vu_char *)(CONFIG_SYS_MBAR+0x1B0001)) -#define MCFGPTB_GPTOC3M (*(vu_char *)(CONFIG_SYS_MBAR+0x1B0002)) -#define MCFGPTB_GPTOC3D (*(vu_char *)(CONFIG_SYS_MBAR+0x1B0003)) -#define MCFGPTB_GPTCNT (*(vu_short *)(CONFIG_SYS_MBAR+0x1B0004)) -#define MCFGPTB_GPTSCR1 (*(vu_char *)(CONFIG_SYS_MBAR+0x1B0006)) -#define MCFGPTB_GPTTOV (*(vu_char *)(CONFIG_SYS_MBAR+0x1B0008)) -#define MCFGPTB_GPTCTL1 (*(vu_char *)(CONFIG_SYS_MBAR+0x1B0009)) -#define MCFGPTB_GPTCTL2 (*(vu_char *)(CONFIG_SYS_MBAR+0x1B000B)) -#define MCFGPTB_GPTIE (*(vu_char *)(CONFIG_SYS_MBAR+0x1B000C)) -#define MCFGPTB_GPTSCR2 (*(vu_char *)(CONFIG_SYS_MBAR+0x1B000D)) -#define MCFGPTB_GPTFLG1 (*(vu_char *)(CONFIG_SYS_MBAR+0x1B000E)) -#define MCFGPTB_GPTFLG2 (*(vu_char *)(CONFIG_SYS_MBAR+0x1B000F)) -#define MCFGPTB_GPTC0 (*(vu_short *)(CONFIG_SYS_MBAR+0x1B0010)) -#define MCFGPTB_GPTC1 (*(vu_short *)(CONFIG_SYS_MBAR+0x1B0012)) -#define MCFGPTB_GPTC2 (*(vu_short *)(CONFIG_SYS_MBAR+0x1B0014)) -#define MCFGPTB_GPTC3 (*(vu_short *)(CONFIG_SYS_MBAR+0x1B0016)) -#define MCFGPTB_GPTPACTL (*(vu_char *)(CONFIG_SYS_MBAR+0x1B0018)) -#define MCFGPTB_GPTPAFLG (*(vu_char *)(CONFIG_SYS_MBAR+0x1B0019)) -#define MCFGPTB_GPTPACNT (*(vu_short *)(CONFIG_SYS_MBAR+0x1B001A)) -#define MCFGPTB_GPTPORT (*(vu_char *)(CONFIG_SYS_MBAR+0x1B001D)) -#define MCFGPTB_GPTDDR (*(vu_char *)(CONFIG_SYS_MBAR+0x1B001E)) +#define MCFGPTA_GPTIOS (*(vu_char *)(CFG_SYS_MBAR+0x1A0000)) +#define MCFGPTA_GPTCFORC (*(vu_char *)(CFG_SYS_MBAR+0x1A0001)) +#define MCFGPTA_GPTOC3M (*(vu_char *)(CFG_SYS_MBAR+0x1A0002)) +#define MCFGPTA_GPTOC3D (*(vu_char *)(CFG_SYS_MBAR+0x1A0003)) +#define MCFGPTA_GPTCNT (*(vu_short *)(CFG_SYS_MBAR+0x1A0004)) +#define MCFGPTA_GPTSCR1 (*(vu_char *)(CFG_SYS_MBAR+0x1A0006)) +#define MCFGPTA_GPTTOV (*(vu_char *)(CFG_SYS_MBAR+0x1A0008)) +#define MCFGPTA_GPTCTL1 (*(vu_char *)(CFG_SYS_MBAR+0x1A0009)) +#define MCFGPTA_GPTCTL2 (*(vu_char *)(CFG_SYS_MBAR+0x1A000B)) +#define MCFGPTA_GPTIE (*(vu_char *)(CFG_SYS_MBAR+0x1A000C)) +#define MCFGPTA_GPTSCR2 (*(vu_char *)(CFG_SYS_MBAR+0x1A000D)) +#define MCFGPTA_GPTFLG1 (*(vu_char *)(CFG_SYS_MBAR+0x1A000E)) +#define MCFGPTA_GPTFLG2 (*(vu_char *)(CFG_SYS_MBAR+0x1A000F)) +#define MCFGPTA_GPTC0 (*(vu_short *)(CFG_SYS_MBAR+0x1A0010)) +#define MCFGPTA_GPTC1 (*(vu_short *)(CFG_SYS_MBAR+0x1A0012)) +#define MCFGPTA_GPTC2 (*(vu_short *)(CFG_SYS_MBAR+0x1A0014)) +#define MCFGPTA_GPTC3 (*(vu_short *)(CFG_SYS_MBAR+0x1A0016)) +#define MCFGPTA_GPTPACTL (*(vu_char *)(CFG_SYS_MBAR+0x1A0018)) +#define MCFGPTA_GPTPAFLG (*(vu_char *)(CFG_SYS_MBAR+0x1A0019)) +#define MCFGPTA_GPTPACNT (*(vu_short *)(CFG_SYS_MBAR+0x1A001A)) +#define MCFGPTA_GPTPORT (*(vu_char *)(CFG_SYS_MBAR+0x1A001D)) +#define MCFGPTA_GPTDDR (*(vu_char *)(CFG_SYS_MBAR+0x1A001E)) + +#define MCFGPTB_GPTIOS (*(vu_char *)(CFG_SYS_MBAR+0x1B0000)) +#define MCFGPTB_GPTCFORC (*(vu_char *)(CFG_SYS_MBAR+0x1B0001)) +#define MCFGPTB_GPTOC3M (*(vu_char *)(CFG_SYS_MBAR+0x1B0002)) +#define MCFGPTB_GPTOC3D (*(vu_char *)(CFG_SYS_MBAR+0x1B0003)) +#define MCFGPTB_GPTCNT (*(vu_short *)(CFG_SYS_MBAR+0x1B0004)) +#define MCFGPTB_GPTSCR1 (*(vu_char *)(CFG_SYS_MBAR+0x1B0006)) +#define MCFGPTB_GPTTOV (*(vu_char *)(CFG_SYS_MBAR+0x1B0008)) +#define MCFGPTB_GPTCTL1 (*(vu_char *)(CFG_SYS_MBAR+0x1B0009)) +#define MCFGPTB_GPTCTL2 (*(vu_char *)(CFG_SYS_MBAR+0x1B000B)) +#define MCFGPTB_GPTIE (*(vu_char *)(CFG_SYS_MBAR+0x1B000C)) +#define MCFGPTB_GPTSCR2 (*(vu_char *)(CFG_SYS_MBAR+0x1B000D)) +#define MCFGPTB_GPTFLG1 (*(vu_char *)(CFG_SYS_MBAR+0x1B000E)) +#define MCFGPTB_GPTFLG2 (*(vu_char *)(CFG_SYS_MBAR+0x1B000F)) +#define MCFGPTB_GPTC0 (*(vu_short *)(CFG_SYS_MBAR+0x1B0010)) +#define MCFGPTB_GPTC1 (*(vu_short *)(CFG_SYS_MBAR+0x1B0012)) +#define MCFGPTB_GPTC2 (*(vu_short *)(CFG_SYS_MBAR+0x1B0014)) +#define MCFGPTB_GPTC3 (*(vu_short *)(CFG_SYS_MBAR+0x1B0016)) +#define MCFGPTB_GPTPACTL (*(vu_char *)(CFG_SYS_MBAR+0x1B0018)) +#define MCFGPTB_GPTPAFLG (*(vu_char *)(CFG_SYS_MBAR+0x1B0019)) +#define MCFGPTB_GPTPACNT (*(vu_short *)(CFG_SYS_MBAR+0x1B001A)) +#define MCFGPTB_GPTPORT (*(vu_char *)(CFG_SYS_MBAR+0x1B001D)) +#define MCFGPTB_GPTDDR (*(vu_char *)(CFG_SYS_MBAR+0x1B001E)) /* Bit level definitions and macros */ #define MCFGPT_GPTIOS_IOS3 (0x08) @@ -556,7 +556,7 @@ /* Coldfire Flash Module CFM */ -#define MCFCFM_MCR (*(vu_short *)(CONFIG_SYS_MBAR+0x1D0000)) +#define MCFCFM_MCR (*(vu_short *)(CFG_SYS_MBAR+0x1D0000)) #define MCFCFM_MCR_LOCK (0x0400) #define MCFCFM_MCR_PVIE (0x0200) #define MCFCFM_MCR_AEIE (0x0100) @@ -564,23 +564,23 @@ #define MCFCFM_MCR_CCIE (0x0040) #define MCFCFM_MCR_KEYACC (0x0020) -#define MCFCFM_CLKD (*(vu_char *)(CONFIG_SYS_MBAR+0x1D0002)) +#define MCFCFM_CLKD (*(vu_char *)(CFG_SYS_MBAR+0x1D0002)) -#define MCFCFM_SEC (*(vu_long*) (CONFIG_SYS_MBAR+0x1D0008)) +#define MCFCFM_SEC (*(vu_long*) (CFG_SYS_MBAR+0x1D0008)) #define MCFCFM_SEC_KEYEN (0x80000000) #define MCFCFM_SEC_SECSTAT (0x40000000) -#define MCFCFM_PROT (*(vu_long*) (CONFIG_SYS_MBAR+0x1D0010)) -#define MCFCFM_SACC (*(vu_long*) (CONFIG_SYS_MBAR+0x1D0014)) -#define MCFCFM_DACC (*(vu_long*) (CONFIG_SYS_MBAR+0x1D0018)) -#define MCFCFM_USTAT (*(vu_char*) (CONFIG_SYS_MBAR+0x1D0020)) +#define MCFCFM_PROT (*(vu_long*) (CFG_SYS_MBAR+0x1D0010)) +#define MCFCFM_SACC (*(vu_long*) (CFG_SYS_MBAR+0x1D0014)) +#define MCFCFM_DACC (*(vu_long*) (CFG_SYS_MBAR+0x1D0018)) +#define MCFCFM_USTAT (*(vu_char*) (CFG_SYS_MBAR+0x1D0020)) #define MCFCFM_USTAT_CBEIF 0x80 #define MCFCFM_USTAT_CCIF 0x40 #define MCFCFM_USTAT_PVIOL 0x20 #define MCFCFM_USTAT_ACCERR 0x10 #define MCFCFM_USTAT_BLANK 0x04 -#define MCFCFM_CMD (*(vu_char*) (CONFIG_SYS_MBAR+0x1D0024)) +#define MCFCFM_CMD (*(vu_char*) (CFG_SYS_MBAR+0x1D0024)) #define MCFCFM_CMD_ERSVER 0x05 #define MCFCFM_CMD_PGERSVER 0x06 #define MCFCFM_CMD_PGM 0x20 diff --git a/arch/m68k/lib/bdinfo.c b/arch/m68k/lib/bdinfo.c index 7eca6725a6..0b4629f1c8 100644 --- a/arch/m68k/lib/bdinfo.c +++ b/arch/m68k/lib/bdinfo.c @@ -16,7 +16,7 @@ int arch_setup_bdinfo(void) { struct bd_info *bd = gd->bd; - bd->bi_mbar_base = CONFIG_SYS_MBAR; /* base of internal registers */ + bd->bi_mbar_base = CFG_SYS_MBAR; /* base of internal registers */ bd->bi_intfreq = gd->cpu_clk; /* Internal Freq, in Hz */ bd->bi_busfreq = gd->bus_clk; /* Bus Freq, in Hz */ @@ -38,7 +38,7 @@ void arch_print_bdinfo(void) struct bd_info *bd = gd->bd; bdinfo_print_mhz("busfreq", bd->bi_busfreq); -#if defined(CONFIG_SYS_MBAR) +#if defined(CFG_SYS_MBAR) bdinfo_print_num_l("mbar", bd->bi_mbar_base); #endif bdinfo_print_mhz("cpufreq", bd->bi_intfreq); diff --git a/arch/m68k/lib/cache.c b/arch/m68k/lib/cache.c index aa2b93e0e0..4ddda69f5a 100644 --- a/arch/m68k/lib/cache.c +++ b/arch/m68k/lib/cache.c @@ -34,18 +34,18 @@ void icache_enable(void) *cf_icache_status = 1; #if defined(CONFIG_CF_V4) || defined(CONFIG_CF_V4E) - __asm__ __volatile__("movec %0, %%acr2"::"r"(CONFIG_SYS_CACHE_ACR2)); + __asm__ __volatile__("movec %0, %%acr2"::"r"(CFG_SYS_CACHE_ACR2)); __asm__ __volatile__("movec %0, %%acr3"::"r"(CONFIG_SYS_CACHE_ACR3)); #if defined(CONFIG_CF_V4E) __asm__ __volatile__("movec %0, %%acr6"::"r"(CONFIG_SYS_CACHE_ACR6)); __asm__ __volatile__("movec %0, %%acr7"::"r"(CONFIG_SYS_CACHE_ACR7)); #endif #else - __asm__ __volatile__("movec %0, %%acr0"::"r"(CONFIG_SYS_CACHE_ACR0)); - __asm__ __volatile__("movec %0, %%acr1"::"r"(CONFIG_SYS_CACHE_ACR1)); + __asm__ __volatile__("movec %0, %%acr0"::"r"(CFG_SYS_CACHE_ACR0)); + __asm__ __volatile__("movec %0, %%acr1"::"r"(CFG_SYS_CACHE_ACR1)); #endif - __asm__ __volatile__("movec %0, %%cacr"::"r"(CONFIG_SYS_CACHE_ICACR)); + __asm__ __volatile__("movec %0, %%cacr"::"r"(CFG_SYS_CACHE_ICACR)); } void icache_disable(void) @@ -72,9 +72,9 @@ void icache_invalid(void) { u32 temp; - temp = CONFIG_SYS_ICACHE_INV; + temp = CFG_SYS_ICACHE_INV; if (*cf_icache_status) - temp |= CONFIG_SYS_CACHE_ICACR; + temp |= CFG_SYS_CACHE_ICACR; __asm__ __volatile__("movec %0, %%cacr"::"r"(temp)); } @@ -89,15 +89,15 @@ void dcache_enable(void) *cf_dcache_status = 1; #if defined(CONFIG_CF_V4) || defined(CONFIG_CF_V4E) - __asm__ __volatile__("movec %0, %%acr0"::"r"(CONFIG_SYS_CACHE_ACR0)); - __asm__ __volatile__("movec %0, %%acr1"::"r"(CONFIG_SYS_CACHE_ACR1)); + __asm__ __volatile__("movec %0, %%acr0"::"r"(CFG_SYS_CACHE_ACR0)); + __asm__ __volatile__("movec %0, %%acr1"::"r"(CFG_SYS_CACHE_ACR1)); #if defined(CONFIG_CF_V4E) __asm__ __volatile__("movec %0, %%acr4"::"r"(CONFIG_SYS_CACHE_ACR4)); __asm__ __volatile__("movec %0, %%acr5"::"r"(CONFIG_SYS_CACHE_ACR5)); #endif #endif - __asm__ __volatile__("movec %0, %%cacr"::"r"(CONFIG_SYS_CACHE_DCACR)); + __asm__ __volatile__("movec %0, %%cacr"::"r"(CFG_SYS_CACHE_DCACR)); } void dcache_disable(void) @@ -124,11 +124,11 @@ void dcache_invalid(void) #if defined(CONFIG_CF_V4) || defined(CONFIG_CF_V4E) u32 temp; - temp = CONFIG_SYS_DCACHE_INV; + temp = CFG_SYS_DCACHE_INV; if (*cf_dcache_status) - temp |= CONFIG_SYS_CACHE_DCACR; + temp |= CFG_SYS_CACHE_DCACR; if (*cf_icache_status) - temp |= CONFIG_SYS_CACHE_ICACR; + temp |= CFG_SYS_CACHE_ICACR; __asm__ __volatile__("movec %0, %%cacr"::"r"(temp)); #endif diff --git a/arch/m68k/lib/traps.c b/arch/m68k/lib/traps.c index 0c2c1a9965..28fe803928 100644 --- a/arch/m68k/lib/traps.c +++ b/arch/m68k/lib/traps.c @@ -62,7 +62,7 @@ static void trap_init(ulong value) { int arch_initr_trap(void) { - trap_init(CONFIG_SYS_SDRAM_BASE); + trap_init(CFG_SYS_SDRAM_BASE); return 0; } diff --git a/arch/microblaze/config.mk b/arch/microblaze/config.mk index d35b4f6db7..467c5ca1b1 100644 --- a/arch/microblaze/config.mk +++ b/arch/microblaze/config.mk @@ -6,8 +6,6 @@ # (C) Copyright 2004 Atmark Techno, Inc. # Yasushi SHOJI <yashi@atmark-techno.com> -CONFIG_STANDALONE_LOAD_ADDR ?= 0x80F00000 - PLATFORM_CPPFLAGS += -ffixed-r31 -D__microblaze__ PLATFORM_CPPFLAGS += -fdata-sections -ffunction-sections diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 9af0133f10..23142bd270 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -19,7 +19,6 @@ config TARGET_MALTA select DM select DM_SERIAL select PCI - select DM_ETH select DYNAMIC_IO_PORT_BASE select MIPS_CM select MIPS_INSERT_BOOT_CONFIG @@ -71,7 +70,6 @@ config ARCH_MTMIPS imply CMD_DM select DISPLAY_CPUINFO select DM - imply DM_ETH imply DM_GPIO select DM_RESET select DM_SERIAL @@ -104,7 +102,6 @@ config ARCH_OCTEON select DISPLAY_CPUINFO select DMA_ADDR_T_64BIT select DM - select DM_ETH select DM_GPIO select DM_I2C select DM_SERIAL @@ -153,7 +150,6 @@ config TARGET_XILFPGA bool "Support Imagination Xilfpga" select HAS_FIXED_TIMER_FREQUENCY select DM - select DM_ETH select DM_GPIO select DM_SERIAL select SYS_CACHE_SHIFT_4 diff --git a/arch/mips/config.mk b/arch/mips/config.mk index 04f3627805..745f03190e 100644 --- a/arch/mips/config.mk +++ b/arch/mips/config.mk @@ -25,14 +25,12 @@ ifdef CONFIG_32BIT PLATFORM_CPPFLAGS += -mabi=32 KBUILD_LDFLAGS += -m $(32bit-emul) OBJCOPYFLAGS += -O $(32bit-bfd) -CONFIG_STANDALONE_LOAD_ADDR ?= 0x80200000 endif ifdef CONFIG_64BIT PLATFORM_CPPFLAGS += -mabi=64 KBUILD_LDFLAGS += -m$(64bit-emul) OBJCOPYFLAGS += -O $(64bit-bfd) -CONFIG_STANDALONE_LOAD_ADDR ?= 0xffffffff80200000 endif PLATFORM_CPPFLAGS += -D__MIPS__ diff --git a/arch/mips/lib/traps.c b/arch/mips/lib/traps.c index 7577fdd25d..7a682f256a 100644 --- a/arch/mips/lib/traps.c +++ b/arch/mips/lib/traps.c @@ -135,7 +135,7 @@ void trap_restore(void) int arch_initr_trap(void) { - trap_init(CONFIG_SYS_SDRAM_BASE); + trap_init(CFG_SYS_SDRAM_BASE); return 0; } diff --git a/arch/mips/mach-jz47xx/jz4780/jz4780.c b/arch/mips/mach-jz47xx/jz4780/jz4780.c index cff98b0a77..15d1eff2ba 100644 --- a/arch/mips/mach-jz47xx/jz4780/jz4780.c +++ b/arch/mips/mach-jz47xx/jz4780/jz4780.c @@ -78,7 +78,7 @@ void board_init_f(ulong dummy) phys_size_t board_get_usable_ram_top(phys_size_t total_size) { - return CONFIG_SYS_SDRAM_BASE + (256 * 1024 * 1024); + return CFG_SYS_SDRAM_BASE + (256 * 1024 * 1024); } int print_cpuinfo(void) diff --git a/arch/mips/mach-mscc/cpu.c b/arch/mips/mach-mscc/cpu.c index 5bc31006aa..d484eb92c4 100644 --- a/arch/mips/mach-mscc/cpu.c +++ b/arch/mips/mach-mscc/cpu.c @@ -17,16 +17,16 @@ DECLARE_GLOBAL_DATA_PTR; -#if CONFIG_SYS_SDRAM_SIZE <= SZ_64M +#if CFG_SYS_SDRAM_SIZE <= SZ_64M #define MSCC_RAM_TLB_SIZE SZ_64M #define MSCC_ATTRIB2 MMU_REGIO_INVAL -#elif CONFIG_SYS_SDRAM_SIZE <= SZ_128M +#elif CFG_SYS_SDRAM_SIZE <= SZ_128M #define MSCC_RAM_TLB_SIZE SZ_64M #define MSCC_ATTRIB2 MMU_REGIO_RW -#elif CONFIG_SYS_SDRAM_SIZE <= SZ_256M +#elif CFG_SYS_SDRAM_SIZE <= SZ_256M #define MSCC_RAM_TLB_SIZE SZ_256M #define MSCC_ATTRIB2 MMU_REGIO_INVAL -#elif CONFIG_SYS_SDRAM_SIZE <= SZ_512M +#elif CFG_SYS_SDRAM_SIZE <= SZ_512M #define MSCC_RAM_TLB_SIZE SZ_256M #define MSCC_ATTRIB2 MMU_REGIO_RW #else diff --git a/arch/mips/mach-mscc/dram.c b/arch/mips/mach-mscc/dram.c index c53a4202e0..f7fbd33cc4 100644 --- a/arch/mips/mach-mscc/dram.c +++ b/arch/mips/mach-mscc/dram.c @@ -67,6 +67,6 @@ int print_cpuinfo(void) int dram_init(void) { - gd->ram_size = CONFIG_SYS_SDRAM_SIZE; + gd->ram_size = CFG_SYS_SDRAM_SIZE; return 0; } diff --git a/arch/mips/mach-mscc/include/mach/ddr.h b/arch/mips/mach-mscc/include/mach/ddr.h index d52eabbd2b..75fb3ca00d 100644 --- a/arch/mips/mach-mscc/include/mach/ddr.h +++ b/arch/mips/mach-mscc/include/mach/ddr.h @@ -13,7 +13,7 @@ #include <mach/common.h> #define MIPS_VCOREIII_MEMORY_DDR3 -#define MIPS_VCOREIII_DDR_SIZE CONFIG_SYS_SDRAM_SIZE +#define MIPS_VCOREIII_DDR_SIZE CFG_SYS_SDRAM_SIZE #if defined(CONFIG_DDRTYPE_H5TQ1G63BFA) /* Serval1 Refboard */ diff --git a/arch/mips/mach-mtmips/mt7621/spl/start.S b/arch/mips/mach-mtmips/mt7621/spl/start.S index 3cad3567e7..7063f32610 100644 --- a/arch/mips/mach-mtmips/mt7621/spl/start.S +++ b/arch/mips/mach-mtmips/mt7621/spl/start.S @@ -18,8 +18,8 @@ #include "dram.h" #ifndef CONFIG_SYS_INIT_SP_ADDR -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + \ - CONFIG_SYS_INIT_SP_OFFSET) +#define CONFIG_SYS_INIT_SP_ADDR (CFG_SYS_SDRAM_BASE + \ + CFG_SYS_INIT_SP_OFFSET) #endif #define SP_ADDR_TEMP 0xbe10dff0 diff --git a/arch/mips/mach-octeon/dram.c b/arch/mips/mach-octeon/dram.c index 9c5789b1c8..85cb084c13 100644 --- a/arch/mips/mach-octeon/dram.c +++ b/arch/mips/mach-octeon/dram.c @@ -81,7 +81,7 @@ phys_size_t board_get_usable_ram_top(phys_size_t total_size) { if (IS_ENABLED(CONFIG_RAM_OCTEON)) { /* Map a maximum of 256MiB - return not size but address */ - return CONFIG_SYS_SDRAM_BASE + min(gd->ram_size, + return CFG_SYS_SDRAM_BASE + min(gd->ram_size, UBOOT_RAM_SIZE_MAX); } else { return gd->ram_top; diff --git a/arch/nios2/config.mk b/arch/nios2/config.mk index 44260b1431..b18b9b78ab 100644 --- a/arch/nios2/config.mk +++ b/arch/nios2/config.mk @@ -4,8 +4,6 @@ # Psyent Corporation <www.psyent.com> # Scott McNutt <smcnutt@psyent.com> -CONFIG_STANDALONE_LOAD_ADDR ?= 0x02000000 - PLATFORM_CPPFLAGS += -D__NIOS2__ PLATFORM_CPPFLAGS += -G0 diff --git a/arch/nios2/cpu/cpu.c b/arch/nios2/cpu/cpu.c index 4dd9c10faa..85544503a5 100644 --- a/arch/nios2/cpu/cpu.c +++ b/arch/nios2/cpu/cpu.c @@ -73,7 +73,7 @@ static int nios_cpu_setup(void *ctx, struct event *event) if (ret) return ret; - gd->ram_size = CONFIG_SYS_SDRAM_SIZE; + gd->ram_size = CFG_SYS_SDRAM_SIZE; #ifndef CONFIG_ROM_STUBS copy_exception_trampoline(); #endif diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig index c355a95453..e0801c2594 100644 --- a/arch/powerpc/Kconfig +++ b/arch/powerpc/Kconfig @@ -34,6 +34,10 @@ config MPC8xx endchoice +config FSL_LBC + def_bool y + depends on (MPC85xx || MPC83xx) && !FSL_IFC + config HIGH_BATS bool "Enable high BAT registers" help @@ -44,9 +48,36 @@ config SYS_INIT_RAM_LOCK bool "Lock some portion of L1 for initial ram stack" depends on MPC83xx || MPC85xx +config SYS_SRIO + bool "Serial RapidIO support" + +config SRIO1 + bool "Board has SRIO 1 port available" + depends on SYS_SRIO + +config SRIO2 + bool "Board has SRIO 2 port available" + depends on SYS_SRIO + +config SRIO_PCIE_BOOT_MASTER + bool "Board can support master function for Boot from SRIO and PCIE" + depends on SYS_SRIO + source "arch/powerpc/cpu/mpc83xx/Kconfig" source "arch/powerpc/cpu/mpc85xx/Kconfig" source "arch/powerpc/cpu/mpc8xx/Kconfig" source "arch/powerpc/lib/Kconfig" +config USE_UBOOTPATH + bool "Set a default 'uboot' value in the environment" + help + Many default environment scripts will check the "uboot" variable + to determine the name of the file to load via tftp that will then + be written to flash. + +config UBOOTPATH + string "Value of the default 'uboot' value in the environment" + depends on USE_UBOOTPATH + default "u-boot.bin" + endmenu diff --git a/arch/powerpc/config.mk b/arch/powerpc/config.mk index 307ca65745..725a4f48aa 100644 --- a/arch/powerpc/config.mk +++ b/arch/powerpc/config.mk @@ -3,7 +3,6 @@ # (C) Copyright 2000-2010 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. -CONFIG_STANDALONE_LOAD_ADDR ?= 0x40000 LDFLAGS_FINAL += --gc-sections LDFLAGS_FINAL += --bss-plt PLATFORM_RELFLAGS += -fpic -mrelocatable -ffunction-sections \ diff --git a/arch/powerpc/cpu/mpc83xx/Kconfig b/arch/powerpc/cpu/mpc83xx/Kconfig index ec3405e967..b695c7e4d8 100644 --- a/arch/powerpc/cpu/mpc83xx/Kconfig +++ b/arch/powerpc/cpu/mpc83xx/Kconfig @@ -196,6 +196,13 @@ config 83XX_PCICLK config FSL_ELBC bool +config FSL_SERDES + bool "SerDes initialization" + depends on !MPC83XX_SERDES + +config NEVER_ASSERT_ODT_TO_CPU + bool "Never assert ODT to internal IOs" + source "board/freescale/mpc837xerdb/Kconfig" source "board/gdsys/mpc8308/Kconfig" diff --git a/arch/powerpc/cpu/mpc83xx/cpu.c b/arch/powerpc/cpu/mpc83xx/cpu.c index 8d531898bd..a6c063556e 100644 --- a/arch/powerpc/cpu/mpc83xx/cpu.c +++ b/arch/powerpc/cpu/mpc83xx/cpu.c @@ -180,24 +180,6 @@ void watchdog_reset (void) } #endif -#ifndef CONFIG_DM_ETH -/* - * Initializes on-chip ethernet controllers. - * to override, implement board_eth_init() - */ -int cpu_eth_init(struct bd_info *bis) -{ -#if defined(CONFIG_UEC_ETH) - uec_standard_init(bis); -#endif - -#if defined(CONFIG_TSEC_ENET) - tsec_standard_init(bis); -#endif - return 0; -} -#endif /* !CONFIG_DM_ETH */ - /* * Initializes on-chip MMC controllers. * to override, implement board_mmc_init() diff --git a/arch/powerpc/cpu/mpc83xx/cpu_init.c b/arch/powerpc/cpu/mpc83xx/cpu_init.c index 33835eeec2..63c2729411 100644 --- a/arch/powerpc/cpu/mpc83xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc83xx/cpu_init.c @@ -77,10 +77,10 @@ void cpu_init_f (volatile immap_t * im) #ifdef CONFIG_SYS_SCCR_TSECCM /* all TSEC's clock mode */ SCCR_TSECCM | #endif -#ifdef CONFIG_SYS_SCCR_TSEC1CM /* TSEC1 clock mode */ +#ifdef CFG_SYS_SCCR_TSEC1CM /* TSEC1 clock mode */ SCCR_TSEC1CM | #endif -#ifdef CONFIG_SYS_SCCR_TSEC2CM /* TSEC2 clock mode */ +#ifdef CFG_SYS_SCCR_TSEC2CM /* TSEC2 clock mode */ SCCR_TSEC2CM | #endif #ifdef CONFIG_SYS_SCCR_TSEC1ON /* TSEC1 clock switch */ @@ -92,10 +92,10 @@ void cpu_init_f (volatile immap_t * im) #ifdef CONFIG_SYS_SCCR_USBMPHCM /* USB MPH clock mode */ SCCR_USBMPHCM | #endif -#ifdef CONFIG_SYS_SCCR_USBDRCM /* USB DR clock mode */ +#ifdef CFG_SYS_SCCR_USBDRCM /* USB DR clock mode */ SCCR_USBDRCM | #endif -#ifdef CONFIG_SYS_SCCR_SATACM /* SATA controller clock mode */ +#ifdef CFG_SYS_SCCR_SATACM /* SATA controller clock mode */ SCCR_SATACM | #endif 0; @@ -115,11 +115,11 @@ void cpu_init_f (volatile immap_t * im) #ifdef CONFIG_SYS_SCCR_TSECCM /* all TSEC's clock mode */ (CONFIG_SYS_SCCR_TSECCM << SCCR_TSECCM_SHIFT) | #endif -#ifdef CONFIG_SYS_SCCR_TSEC1CM /* TSEC1 clock mode */ - (CONFIG_SYS_SCCR_TSEC1CM << SCCR_TSEC1CM_SHIFT) | +#ifdef CFG_SYS_SCCR_TSEC1CM /* TSEC1 clock mode */ + (CFG_SYS_SCCR_TSEC1CM << SCCR_TSEC1CM_SHIFT) | #endif -#ifdef CONFIG_SYS_SCCR_TSEC2CM /* TSEC2 clock mode */ - (CONFIG_SYS_SCCR_TSEC2CM << SCCR_TSEC2CM_SHIFT) | +#ifdef CFG_SYS_SCCR_TSEC2CM /* TSEC2 clock mode */ + (CFG_SYS_SCCR_TSEC2CM << SCCR_TSEC2CM_SHIFT) | #endif #ifdef CONFIG_SYS_SCCR_TSEC1ON /* TSEC1 clock switch */ (CONFIG_SYS_SCCR_TSEC1ON << SCCR_TSEC1ON_SHIFT) | @@ -130,11 +130,11 @@ void cpu_init_f (volatile immap_t * im) #ifdef CONFIG_SYS_SCCR_USBMPHCM /* USB MPH clock mode */ (CONFIG_SYS_SCCR_USBMPHCM << SCCR_USBMPHCM_SHIFT) | #endif -#ifdef CONFIG_SYS_SCCR_USBDRCM /* USB DR clock mode */ - (CONFIG_SYS_SCCR_USBDRCM << SCCR_USBDRCM_SHIFT) | +#ifdef CFG_SYS_SCCR_USBDRCM /* USB DR clock mode */ + (CFG_SYS_SCCR_USBDRCM << SCCR_USBDRCM_SHIFT) | #endif -#ifdef CONFIG_SYS_SCCR_SATACM /* SATA controller clock mode */ - (CONFIG_SYS_SCCR_SATACM << SCCR_SATACM_SHIFT) | +#ifdef CFG_SYS_SCCR_SATACM /* SATA controller clock mode */ + (CFG_SYS_SCCR_SATACM << SCCR_SATACM_SHIFT) | #endif 0; @@ -175,26 +175,26 @@ void cpu_init_f (volatile immap_t * im) setbits_be32(&im->sysconf.spcr, SPCR_TBEN); /* System General Purpose Register */ -#ifdef CONFIG_SYS_SICRH +#ifdef CFG_SYS_SICRH #if defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC8313) /* regarding to MPC34x manual rev.1 bits 28..29 must be preserved */ - __raw_writel((im->sysconf.sicrh & 0x0000000C) | CONFIG_SYS_SICRH, + __raw_writel((im->sysconf.sicrh & 0x0000000C) | CFG_SYS_SICRH, &im->sysconf.sicrh); #else - __raw_writel(CONFIG_SYS_SICRH, &im->sysconf.sicrh); + __raw_writel(CFG_SYS_SICRH, &im->sysconf.sicrh); #endif #endif -#ifdef CONFIG_SYS_SICRL - __raw_writel(CONFIG_SYS_SICRL, &im->sysconf.sicrl); +#ifdef CFG_SYS_SICRL + __raw_writel(CFG_SYS_SICRL, &im->sysconf.sicrl); #endif -#ifdef CONFIG_SYS_GPR1 - __raw_writel(CONFIG_SYS_GPR1, &im->sysconf.gpr1); +#ifdef CFG_SYS_GPR1 + __raw_writel(CFG_SYS_GPR1, &im->sysconf.gpr1); #endif -#ifdef CONFIG_SYS_DDRCDR /* DDR control driver register */ - __raw_writel(CONFIG_SYS_DDRCDR, &im->sysconf.ddrcdr); +#ifdef CFG_SYS_DDRCDR /* DDR control driver register */ + __raw_writel(CFG_SYS_DDRCDR, &im->sysconf.ddrcdr); #endif -#ifdef CONFIG_SYS_OBIR /* Output buffer impedance register */ - __raw_writel(CONFIG_SYS_OBIR, &im->sysconf.obir); +#ifdef CFG_SYS_OBIR /* Output buffer impedance register */ + __raw_writel(CFG_SYS_OBIR, &im->sysconf.obir); #endif #if !defined(CONFIG_PINCTRL) diff --git a/arch/powerpc/cpu/mpc83xx/elbc/elbc.h b/arch/powerpc/cpu/mpc83xx/elbc/elbc.h index e795cd10cb..b0b9a1e99e 100644 --- a/arch/powerpc/cpu/mpc83xx/elbc/elbc.h +++ b/arch/powerpc/cpu/mpc83xx/elbc/elbc.h @@ -1,16 +1,16 @@ #if defined(CONFIG_ELBC_BR_OR_NAND_PRELIM_0) -#define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR0_PRELIM -#define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR0_PRELIM +#define CFG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR0_PRELIM +#define CFG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR0_PRELIM #elif defined(CONFIG_ELBC_BR_OR_NAND_PRELIM_1) -#define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR1_PRELIM -#define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR1_PRELIM +#define CFG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR1_PRELIM +#define CFG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR1_PRELIM #elif defined(CONFIG_ELBC_BR_OR_NAND_PRELIM_2) -#define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR2_PRELIM -#define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR2_PRELIM +#define CFG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR2_PRELIM +#define CFG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR2_PRELIM #elif defined(CONFIG_ELBC_BR_OR_NAND_PRELIM_3) -#define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR3_PRELIM -#define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR3_PRELIM +#define CFG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR3_PRELIM +#define CFG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR3_PRELIM #elif defined(CONFIG_ELBC_BR_OR_NAND_PRELIM_4) -#define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR4_PRELIM -#define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR4_PRELIM +#define CFG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR4_PRELIM +#define CFG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR4_PRELIM #endif diff --git a/arch/powerpc/cpu/mpc83xx/pcie.c b/arch/powerpc/cpu/mpc83xx/pcie.c index d2b6b05bda..47ca74c5c3 100644 --- a/arch/powerpc/cpu/mpc83xx/pcie.c +++ b/arch/powerpc/cpu/mpc83xx/pcie.c @@ -24,13 +24,13 @@ static struct { u32 size; } mpc83xx_pcie_cfg_space[] = { { - .base = CONFIG_SYS_PCIE1_CFG_BASE, - .size = CONFIG_SYS_PCIE1_CFG_SIZE, + .base = CFG_SYS_PCIE1_CFG_BASE, + .size = CFG_SYS_PCIE1_CFG_SIZE, }, -#if defined(CONFIG_SYS_PCIE2_CFG_BASE) && defined(CONFIG_SYS_PCIE2_CFG_SIZE) +#if defined(CFG_SYS_PCIE2_CFG_BASE) && defined(CFG_SYS_PCIE2_CFG_SIZE) { - .base = CONFIG_SYS_PCIE2_CFG_BASE, - .size = CONFIG_SYS_PCIE2_CFG_SIZE, + .base = CFG_SYS_PCIE2_CFG_BASE, + .size = CFG_SYS_PCIE2_CFG_SIZE, }, #endif }; diff --git a/arch/powerpc/cpu/mpc83xx/serdes.c b/arch/powerpc/cpu/mpc83xx/serdes.c index bb963ee5e2..d4848b2ec4 100644 --- a/arch/powerpc/cpu/mpc83xx/serdes.c +++ b/arch/powerpc/cpu/mpc83xx/serdes.c @@ -8,8 +8,6 @@ * Author: Li Yang <leoli@freescale.com> */ -#ifndef CONFIG_MPC83XX_SERDES - #include <config.h> #include <common.h> #include <asm/io.h> @@ -151,5 +149,3 @@ void fsl_setup_serdes(u32 offset, char proto, u32 rfcks, char vdd) tmp |= FSL_SRDSRSTCTL_RST; out_be32(regs + FSL_SRDSRSTCTL_OFFS, tmp); } - -#endif /* !CONFIG_MPC83XX_SERDES */ diff --git a/arch/powerpc/cpu/mpc83xx/spd_sdram.c b/arch/powerpc/cpu/mpc83xx/spd_sdram.c index e12043b260..4f982b8303 100644 --- a/arch/powerpc/cpu/mpc83xx/spd_sdram.c +++ b/arch/powerpc/cpu/mpc83xx/spd_sdram.c @@ -59,9 +59,9 @@ void board_add_ram_info(int use_default) printf(", %s MHz)", strmhz(buf, gd->mem_clk)); -#if defined(CONFIG_SYS_LB_SDRAM) && defined(CONFIG_SYS_LBC_SDRAM_SIZE) +#if defined(CONFIG_SYS_LB_SDRAM) && defined(CFG_SYS_LBC_SDRAM_SIZE) puts("\nSDRAM: "); - print_size (CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, " (local bus)"); + print_size (CFG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, " (local bus)"); #endif } @@ -204,12 +204,12 @@ long int spd_sdram() return 0; } -#ifdef CONFIG_SYS_DDRCDR_VALUE +#ifdef CFG_SYS_DDRCDR_VALUE /* * Adjust DDR II IO voltage biasing. It just makes it work. */ if(spd.mem_type == SPD_MEMTYPE_DDR2) { - immap->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE; + immap->sysconf.ddrcdr = CFG_SYS_DDRCDR_VALUE; } udelay(50000); #endif @@ -288,7 +288,7 @@ long int spd_sdram() /* * Set up LAWBAR for all of DDR. */ - ecm->bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000; + ecm->bar = CFG_SYS_SDRAM_BASE & 0xfffff000; ecm->ar = (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & law_size)); debug("DDR:bar=0x%08x\n", ecm->bar); debug("DDR:ar=0x%08x\n", ecm->ar); @@ -693,7 +693,7 @@ long int spd_sdram() ddr->sdram_mode = (0 | (1 << (16 + 10)) /* DQS Differential disable */ -#ifdef CONFIG_SYS_DDR_MODE_WEAK +#ifdef CFG_SYS_DDR_MODE_WEAK | (1 << (16 + 1)) /* weak driver (~60%) */ #endif | (add_lat << (16 + 3)) /* Additive Latency in EMRS1 */ @@ -767,8 +767,8 @@ long int spd_sdram() debug("DDR: sdram_cfg2 = 0x%08x\n", ddr->sdram_cfg2); } -#ifdef CONFIG_SYS_DDR_SDRAM_CLK_CNTL /* Optional platform specific value */ - ddr->sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL; +#ifdef CFG_SYS_DDR_SDRAM_CLK_CNTL /* Optional platform specific value */ + ddr->sdram_clk_cntl = CFG_SYS_DDR_SDRAM_CLK_CNTL; #endif debug("DDR:sdram_clk_cntl=0x%08x\n", ddr->sdram_clk_cntl); diff --git a/arch/powerpc/cpu/mpc83xx/spl_minimal.c b/arch/powerpc/cpu/mpc83xx/spl_minimal.c index d8f6cfe2b4..7cc0383afb 100644 --- a/arch/powerpc/cpu/mpc83xx/spl_minimal.c +++ b/arch/powerpc/cpu/mpc83xx/spl_minimal.c @@ -54,12 +54,12 @@ void cpu_init_f (volatile immap_t * im) im->sysconf.spcr |= SPCR_TBEN; /* DDR control driver register */ -#ifdef CONFIG_SYS_DDRCDR - im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR; +#ifdef CFG_SYS_DDRCDR + im->sysconf.ddrcdr = CFG_SYS_DDRCDR; #endif /* Output buffer impedance register */ -#ifdef CONFIG_SYS_OBIR - im->sysconf.obir = CONFIG_SYS_OBIR; +#ifdef CFG_SYS_OBIR + im->sysconf.obir = CFG_SYS_OBIR; #endif /* @@ -71,16 +71,16 @@ void cpu_init_f (volatile immap_t * im) * has been determined */ -#if defined(CONFIG_SYS_NAND_BR_PRELIM) \ - && defined(CONFIG_SYS_NAND_OR_PRELIM) \ +#if defined(CFG_SYS_NAND_BR_PRELIM) \ + && defined(CFG_SYS_NAND_OR_PRELIM) \ && defined(CONFIG_SYS_NAND_LBLAWBAR_PRELIM) \ && defined(CONFIG_SYS_NAND_LBLAWAR_PRELIM) - set_lbc_br(0, CONFIG_SYS_NAND_BR_PRELIM); - set_lbc_or(0, CONFIG_SYS_NAND_OR_PRELIM); + set_lbc_br(0, CFG_SYS_NAND_BR_PRELIM); + set_lbc_or(0, CFG_SYS_NAND_OR_PRELIM); im->sysconf.lblaw[0].bar = CONFIG_SYS_NAND_LBLAWBAR_PRELIM; im->sysconf.lblaw[0].ar = CONFIG_SYS_NAND_LBLAWAR_PRELIM; #else -#error CONFIG_SYS_NAND_BR_PRELIM, CONFIG_SYS_NAND_OR_PRELIM, CONFIG_SYS_NAND_LBLAWBAR_PRELIM & CONFIG_SYS_NAND_LBLAWAR_PRELIM must be defined +#error CFG_SYS_NAND_BR_PRELIM, CFG_SYS_NAND_OR_PRELIM, CONFIG_SYS_NAND_LBLAWBAR_PRELIM & CONFIG_SYS_NAND_LBLAWAR_PRELIM must be defined #endif } diff --git a/arch/powerpc/cpu/mpc83xx/start.S b/arch/powerpc/cpu/mpc83xx/start.S index 8a351b927c..52326f0ec1 100644 --- a/arch/powerpc/cpu/mpc83xx/start.S +++ b/arch/powerpc/cpu/mpc83xx/start.S @@ -246,7 +246,7 @@ in_flash: #if CONFIG_VAL(SYS_MALLOC_F_LEN) -#if CONFIG_VAL(SYS_MALLOC_F_LEN) + GENERATED_GBL_DATA_SIZE > CONFIG_SYS_INIT_RAM_SIZE +#if CONFIG_VAL(SYS_MALLOC_F_LEN) + GENERATED_GBL_DATA_SIZE > CFG_SYS_INIT_RAM_SIZE #error "SYS_MALLOC_F_LEN too large to fit into initial RAM." #endif @@ -486,7 +486,7 @@ init_e300_core: /* time t 10 */ #if defined(CONFIG_WATCHDOG) /* Initialise the Watchdog values and reset it (if req) */ /*------------------------------------------------------*/ - lis r4, CONFIG_SYS_WATCHDOG_VALUE + lis r4, CFG_SYS_WATCHDOG_VALUE ori r4, r4, (SWCRR_SWEN | SWCRR_SWRI | SWCRR_SWPR) stw r4, SWCRR(r3) @@ -1048,10 +1048,10 @@ trap_init: lock_ram_in_cache: /* Allocate Initial RAM in data cache. */ - lis r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@h - ori r3, r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@l - li r4, ((CONFIG_SYS_INIT_RAM_SIZE & ~31) + \ - (CONFIG_SYS_INIT_RAM_ADDR & 31) + 31) / 32 + lis r3, (CFG_SYS_INIT_RAM_ADDR & ~31)@h + ori r3, r3, (CFG_SYS_INIT_RAM_ADDR & ~31)@l + li r4, ((CFG_SYS_INIT_RAM_SIZE & ~31) + \ + (CFG_SYS_INIT_RAM_ADDR & 31) + 31) / 32 mtctr r4 1: dcbz r0, r3 @@ -1070,10 +1070,10 @@ lock_ram_in_cache: .globl unlock_ram_in_cache unlock_ram_in_cache: /* invalidate the INIT_RAM section */ - lis r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@h - ori r3, r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@l - li r4, ((CONFIG_SYS_INIT_RAM_SIZE & ~31) + \ - (CONFIG_SYS_INIT_RAM_ADDR & 31) + 31) / 32 + lis r3, (CFG_SYS_INIT_RAM_ADDR & ~31)@h + ori r3, r3, (CFG_SYS_INIT_RAM_ADDR & ~31)@l + li r4, ((CFG_SYS_INIT_RAM_SIZE & ~31) + \ + (CFG_SYS_INIT_RAM_ADDR & 31) + 31) / 32 mtctr r4 1: icbi r0, r3 dcbi r0, r3 @@ -1122,14 +1122,14 @@ map_flash_by_law1: * LBIU Local Access Widow 0 will not cover this memory space. So, we * need another window to map in it. */ - lis r4, (CONFIG_SYS_FLASH_BASE)@h - ori r4, r4, (CONFIG_SYS_FLASH_BASE)@l - stw r4, LBLAWBAR1(r3) /* LBLAWBAR1 <= CONFIG_SYS_FLASH_BASE */ + lis r4, (CFG_SYS_FLASH_BASE)@h + ori r4, r4, (CFG_SYS_FLASH_BASE)@l + stw r4, LBLAWBAR1(r3) /* LBLAWBAR1 <= CFG_SYS_FLASH_BASE */ - /* Store 0x80000012 + log2(CONFIG_SYS_FLASH_SIZE) into LBLAWAR1 */ + /* Store 0x80000012 + log2(CFG_SYS_FLASH_SIZE) into LBLAWAR1 */ lis r4, (0x80000012)@h ori r4, r4, (0x80000012)@l - li r5, CONFIG_SYS_FLASH_SIZE + li r5, CFG_SYS_FLASH_SIZE 1: srawi. r5, r5, 1 /* r5 = r5 >> 1 */ addi r4, r4, 1 bne 1b @@ -1150,24 +1150,24 @@ remap_flash_by_law0: lwz r4, BR0(r3) li r5, 0x7FFF and r4, r4, r5 - lis r5, (CONFIG_SYS_FLASH_BASE & 0xFFFF8000)@h - ori r5, r5, (CONFIG_SYS_FLASH_BASE & 0xFFFF8000)@l + lis r5, (CFG_SYS_FLASH_BASE & 0xFFFF8000)@h + ori r5, r5, (CFG_SYS_FLASH_BASE & 0xFFFF8000)@l or r5, r5, r4 - stw r5, BR0(r3) /* r5 <= (CONFIG_SYS_FLASH_BASE & 0xFFFF8000) | (BR0 & 0x00007FFF) */ + stw r5, BR0(r3) /* r5 <= (CFG_SYS_FLASH_BASE & 0xFFFF8000) | (BR0 & 0x00007FFF) */ lwz r4, OR0(r3) - lis r5, ~((CONFIG_SYS_FLASH_SIZE << 4) - 1) + lis r5, ~((CFG_SYS_FLASH_SIZE << 4) - 1) or r4, r4, r5 stw r4, OR0(r3) - lis r4, (CONFIG_SYS_FLASH_BASE)@h - ori r4, r4, (CONFIG_SYS_FLASH_BASE)@l - stw r4, LBLAWBAR0(r3) /* LBLAWBAR0 <= CONFIG_SYS_FLASH_BASE */ + lis r4, (CFG_SYS_FLASH_BASE)@h + ori r4, r4, (CFG_SYS_FLASH_BASE)@l + stw r4, LBLAWBAR0(r3) /* LBLAWBAR0 <= CFG_SYS_FLASH_BASE */ - /* Store 0x80000012 + log2(CONFIG_SYS_FLASH_SIZE) into LBLAWAR0 */ + /* Store 0x80000012 + log2(CFG_SYS_FLASH_SIZE) into LBLAWAR0 */ lis r4, (0x80000012)@h ori r4, r4, (0x80000012)@l - li r5, CONFIG_SYS_FLASH_SIZE + li r5, CFG_SYS_FLASH_SIZE 1: srawi. r5, r5, 1 /* r5 = r5 >> 1 */ addi r4, r4, 1 bne 1b diff --git a/arch/powerpc/cpu/mpc83xx/sysio/sysio.h b/arch/powerpc/cpu/mpc83xx/sysio/sysio.h index f8c2f104c1..b2f98074fc 100644 --- a/arch/powerpc/cpu/mpc83xx/sysio/sysio.h +++ b/arch/powerpc/cpu/mpc83xx/sysio/sysio.h @@ -1,7 +1,7 @@ #ifdef CONFIG_ARCH_MPC8308 -#ifndef CONFIG_SYS_SICRL -#define CONFIG_SYS_SICRL (\ +#ifndef CFG_SYS_SICRL +#define CFG_SYS_SICRL (\ CONFIG_SICRL_SPI |\ CONFIG_SICRL_UART |\ CONFIG_SICRL_IRQ |\ @@ -10,8 +10,8 @@ ) #endif -#ifndef CONFIG_SYS_SICRH -#define CONFIG_SYS_SICRH (\ +#ifndef CFG_SYS_SICRH +#define CFG_SYS_SICRH (\ CONFIG_SICRH_ESDHC_A |\ CONFIG_SICRH_ESDHC_B |\ CONFIG_SICRH_ESDHC_C |\ diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig index 687c51a8c6..1b180481a4 100644 --- a/arch/powerpc/cpu/mpc85xx/Kconfig +++ b/arch/powerpc/cpu/mpc85xx/Kconfig @@ -1,6 +1,19 @@ menu "mpc85xx CPU" depends on MPC85xx +config PPC_SPINTABLE_COMPATIBLE + depends on MP + def_bool y + help + To comply with ePAPR 1.1, the spin table has been moved to + cache-enabled memory. Old OS may not work with this change. A patch + is waiting to be accepted for Linux kernel. Other OS needs similar + fix to spin table. For OSes with old spin table code, we can enable + this temporary fix by setting environmental variable + "spin_table_compat". For new OSes, set "spin_table_compat=no". After + Linux is fixed, we can remove this macro and related code. For now, + it is enabled by default. + config SYS_CPU default "mpc85xx" @@ -188,14 +201,6 @@ config TARGET_T1024RDB imply CMD_EEPROM imply PANIC_HANG -config TARGET_T1042RDB - bool "Support T1042RDB" - select ARCH_T1042 - select BOARD_LATE_INIT if CHAIN_OF_TRUST - select SUPPORT_SPL - select PHYS_64BIT - select SYS_L3_SIZE_256KB - config TARGET_T1042D4RDB bool "Support T1042D4RDB" select ARCH_T1042 @@ -205,15 +210,6 @@ config TARGET_T1042D4RDB select SYS_L3_SIZE_256KB imply PANIC_HANG -config TARGET_T1042RDB_PI - bool "Support T1042RDB_PI" - select ARCH_T1042 - select BOARD_LATE_INIT if CHAIN_OF_TRUST - select SUPPORT_SPL - select PHYS_64BIT - select SYS_L3_SIZE_256KB - imply PANIC_HANG - config TARGET_T2080QDS bool "Support T2080QDS" select ARCH_T2080 @@ -253,6 +249,8 @@ config TARGET_KMCENT2 bool "Support kmcent2" select VENDOR_KM select FSL_CORENET + select SYS_DPAA_FMAN + select SYS_DPAA_PME select SYS_L3_SIZE_256KB endchoice @@ -619,6 +617,9 @@ config ARCH_P2041 select E500MC select FSL_LAW select SYS_CACHE_SHIFT_6 + select SYS_DPAA_FMAN + select SYS_DPAA_PME + select SYS_DPAA_RMAN select SYS_FSL_ERRATUM_A004510 select SYS_FSL_ERRATUM_A004849 select SYS_FSL_ERRATUM_A005275 @@ -763,6 +764,7 @@ config ARCH_T1024 select FSL_CORENET select FSL_LAW select SYS_CACHE_SHIFT_6 + select SYS_DPAA_FMAN select SYS_FSL_DDR_VER_50 select SYS_FSL_ERRATUM_A008378 select SYS_FSL_ERRATUM_A008109 @@ -793,6 +795,8 @@ config ARCH_T1040 select FSL_CORENET select FSL_LAW select SYS_CACHE_SHIFT_6 + select SYS_DPAA_FMAN + select SYS_DPAA_PME select SYS_FSL_DDR_VER_50 select SYS_FSL_ERRATUM_A008044 select SYS_FSL_ERRATUM_A008378 @@ -823,6 +827,8 @@ config ARCH_T1042 select FSL_CORENET select FSL_LAW select SYS_CACHE_SHIFT_6 + select SYS_DPAA_FMAN + select SYS_DPAA_PME select SYS_FSL_DDR_VER_50 select SYS_FSL_ERRATUM_A008044 select SYS_FSL_ERRATUM_A008378 @@ -852,6 +858,10 @@ config ARCH_T2080 select FSL_CORENET select FSL_LAW select SYS_CACHE_SHIFT_6 + select SYS_DPAA_DCE if !NOBQFMAN + select SYS_DPAA_FMAN if !NOBQFMAN + select SYS_DPAA_PME if !NOBQFMAN + select SYS_DPAA_RMAN if !NOBQFMAN select SYS_FSL_DDR_VER_47 select SYS_FSL_ERRATUM_A006379 select SYS_FSL_ERRATUM_A006593 @@ -872,6 +882,7 @@ config ARCH_T2080 select SYS_FSL_SRIO_LIODN select SYS_FSL_QMAN_V3 if SYS_DPAA_QBMAN select SYS_FSL_USB_DUAL_PHY_ENABLE + select SYS_PMAN if !NOBQFMAN select SYS_PPC64 select FSL_IFC imply CMD_SATA @@ -887,6 +898,10 @@ config ARCH_T4240 select FSL_CORENET select FSL_LAW select SYS_CACHE_SHIFT_6 + select SYS_DPAA_DCE if !NOBQFMAN + select SYS_DPAA_FMAN if !NOBQFMAN + select SYS_DPAA_PME if !NOBQFMAN + select SYS_DPAA_RMAN if !NOBQFMAN select SYS_FSL_DDR_VER_47 select SYS_FSL_ERRATUM_A004468 select SYS_FSL_ERRATUM_A005871 @@ -908,6 +923,7 @@ config ARCH_T4240 select SYS_FSL_SRIO_LIODN select SYS_FSL_QMAN_V3 if SYS_DPAA_QBMAN select SYS_FSL_USB_DUAL_PHY_ENABLE + select SYS_PMAN if !NOBQFMAN select SYS_PPC64 select FSL_IFC imply CMD_SATA @@ -916,7 +932,7 @@ config ARCH_T4240 imply FSL_SATA config MPC85XX_HAVE_RESET_VECTOR - bool "Indicate reset vector at CONFIG_RESET_VECTOR_ADDRESS - 0xffc" + bool "Indicate reset vector at CFG_RESET_VECTOR_ADDRESS - 0xffc" depends on MPC85xx config BTB @@ -948,6 +964,9 @@ config E6500 help Enable PowerPC E6500 core +config NOBQFMAN + bool + config FSL_LAW bool help @@ -1020,6 +1039,15 @@ config SYS_CCSRBAR_DEFAULT if changed by pre-boot regime. The value here must match the current value in SoC. If not sure, do not change. +config SYS_DPAA_PME + bool + +config SYS_DPAA_DCE + bool + +config SYS_DPAA_RMAN + bool + config A003399_NOR_WORKAROUND bool help @@ -1196,6 +1224,9 @@ config FSL_PCIE_DISABLE_ASPM config FSL_PCIE_RESET bool +config SYS_PMAN + bool + config SYS_FSL_RAID_ENGINE bool @@ -1263,6 +1294,9 @@ config SYS_NUM_TLBCAMS Number of TLB CAM entries for Book-E chips. 64 for E500MC, 16 for other E500 SoCs. +config L2_CACHE + bool "Enable L2 cache support" + if HETROGENOUS_CLUSTERS config SYS_MAPLE @@ -1290,6 +1324,11 @@ config SYS_ULB_CLK config SYS_ETVPE_CLK int default 1 + +config MAX_DSP_CPUS + int + default 12 if ARCH_B4860 + default 2 if ARCH_B4420 endif config SYS_L2_SIZE_256KB diff --git a/arch/powerpc/cpu/mpc85xx/b4860_ids.c b/arch/powerpc/cpu/mpc85xx/b4860_ids.c index 3dccc0e106..013a171ed8 100644 --- a/arch/powerpc/cpu/mpc85xx/b4860_ids.c +++ b/arch/powerpc/cpu/mpc85xx/b4860_ids.c @@ -8,7 +8,7 @@ #include <asm/fsl_liodn.h> #ifdef CONFIG_SYS_DPAA_QBMAN -struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = { +struct qportal_info qp_info[CFG_SYS_QMAN_NUM_PORTALS] = { /* dqrr liodn, frame data liodn, liodn off, sdest */ SET_QP_INFO(1, 27, 1, 0), SET_QP_INFO(2, 28, 1, 0), diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c index ed890114ec..c7d473d4a1 100644 --- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c +++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c @@ -23,7 +23,7 @@ */ static void check_erratum_a4849(uint32_t svr) { - void __iomem *dcsr = (void *)CONFIG_SYS_DCSRBAR + 0xb0000; + void __iomem *dcsr = (void *)CFG_SYS_DCSRBAR + 0xb0000; unsigned int i; #if defined(CONFIG_ARCH_P2041) || defined(CONFIG_ARCH_P3041) @@ -120,7 +120,7 @@ static void check_erratum_a4580(uint32_t svr) */ static void check_erratum_a007212(void) { - u32 __iomem *plldgdcr = (void *)(CONFIG_SYS_DCSRBAR + 0x21c20); + u32 __iomem *plldgdcr = (void *)(CFG_SYS_DCSRBAR + 0x21c20); if (in_be32(plldgdcr) & 0x1fe) { /* check if PLL ratio is set by workaround */ diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c index 49a1aac42b..e8a3e82765 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu.c +++ b/arch/powerpc/cpu/mpc85xx/cpu.c @@ -264,7 +264,7 @@ int checkcpu (void) #endif #ifdef CONFIG_SYS_DPAA_FMAN - for (i = 0; i < CONFIG_SYS_NUM_FMAN; i++) { + for (i = 0; i < CFG_SYS_NUM_FMAN; i++) { printf(" FMAN%d: %s MHz\n", i + 1, strmhz(buf1, sysinfo.freq_fman[i])); } @@ -357,7 +357,7 @@ void init_85xx_watchdog(void) { mtspr(SPRN_TCR, (mfspr(SPRN_TCR) & ~WATCHDOG_MASK) | - TCR_WP(CONFIG_WATCHDOG_PRESC) | TCR_WRC(CONFIG_WATCHDOG_RC)); + TCR_WP(CFG_WATCHDOG_PRESC) | TCR_WRC(CFG_WATCHDOG_RC)); } void @@ -417,14 +417,14 @@ void print_reginfo(void) /* Common ddr init for non-corenet fsl 85xx platforms */ #ifndef CONFIG_FSL_CORENET #if (defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL)) && \ - !defined(CONFIG_SYS_INIT_L2_ADDR) + !defined(CFG_SYS_INIT_L2_ADDR) int dram_init(void) { #if defined(CONFIG_SPD_EEPROM) || defined(CONFIG_DDR_SPD) || \ defined(CONFIG_ARCH_QEMU_E500) gd->ram_size = fsl_ddr_sdram_size(); #else - gd->ram_size = (phys_size_t)CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; + gd->ram_size = (phys_size_t)CFG_SYS_SDRAM_SIZE * 1024 * 1024; #endif return 0; @@ -486,7 +486,7 @@ int dram_init(void) #endif /* CONFIG_SYS_RAMBOOT */ #endif -#if CONFIG_POST & CONFIG_SYS_POST_MEMORY +#if CFG_POST & CFG_SYS_POST_MEMORY /* Board-specific functions defined in each board's ddr.c */ void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd, @@ -591,7 +591,7 @@ static void dump_spd_ddr_reg(void) /* invalid the TLBs for DDR and setup new ones to cover p_addr */ static int reset_tlb(phys_addr_t p_addr, u32 size, phys_addr_t *phys_offset) { - u32 vstart = CONFIG_SYS_DDR_SDRAM_BASE; + u32 vstart = CFG_SYS_DDR_SDRAM_BASE; unsigned long epn; u32 tsize, valid, ptr; int ddr_esel; @@ -616,26 +616,26 @@ static int reset_tlb(phys_addr_t p_addr, u32 size, phys_addr_t *phys_offset) /* * slide the testing window up to test another area * for 32_bit system, the maximum testable memory is limited to - * CONFIG_MAX_MEM_MAPPED + * CFG_MAX_MEM_MAPPED */ int arch_memory_test_advance(u32 *vstart, u32 *size, phys_addr_t *phys_offset) { phys_addr_t test_cap, p_addr; - phys_size_t p_size = min(gd->ram_size, CONFIG_MAX_MEM_MAPPED); + phys_size_t p_size = min(gd->ram_size, CFG_MAX_MEM_MAPPED); #if !defined(CONFIG_PHYS_64BIT) || \ - !defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS) || \ - (CONFIG_SYS_INIT_RAM_ADDR_PHYS < 0x100000000ull) + !defined(CFG_SYS_INIT_RAM_ADDR_PHYS) || \ + (CFG_SYS_INIT_RAM_ADDR_PHYS < 0x100000000ull) test_cap = p_size; #else test_cap = gd->ram_size; #endif p_addr = (*vstart) + (*size) + (*phys_offset); if (p_addr < test_cap - 1) { - p_size = min(test_cap - p_addr, CONFIG_MAX_MEM_MAPPED); + p_size = min(test_cap - p_addr, CFG_MAX_MEM_MAPPED); if (reset_tlb(p_addr, p_size, phys_offset) == -1) return -1; - *vstart = CONFIG_SYS_DDR_SDRAM_BASE; + *vstart = CFG_SYS_DDR_SDRAM_BASE; *size = (u32) p_size; printf("Testing 0x%08llx - 0x%08llx\n", (u64)(*vstart) + (*phys_offset), @@ -649,18 +649,18 @@ int arch_memory_test_advance(u32 *vstart, u32 *size, phys_addr_t *phys_offset) /* initialization for testing area */ int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset) { - phys_size_t p_size = min(gd->ram_size, CONFIG_MAX_MEM_MAPPED); + phys_size_t p_size = min(gd->ram_size, CFG_MAX_MEM_MAPPED); - *vstart = CONFIG_SYS_DDR_SDRAM_BASE; - *size = (u32) p_size; /* CONFIG_MAX_MEM_MAPPED < 4G */ + *vstart = CFG_SYS_DDR_SDRAM_BASE; + *size = (u32) p_size; /* CFG_MAX_MEM_MAPPED < 4G */ *phys_offset = 0; #if !defined(CONFIG_PHYS_64BIT) || \ - !defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS) || \ - (CONFIG_SYS_INIT_RAM_ADDR_PHYS < 0x100000000ull) - if (gd->ram_size > CONFIG_MAX_MEM_MAPPED) { + !defined(CFG_SYS_INIT_RAM_ADDR_PHYS) || \ + (CFG_SYS_INIT_RAM_ADDR_PHYS < 0x100000000ull) + if (gd->ram_size > CFG_MAX_MEM_MAPPED) { puts("Cannot test more than "); - print_size(CONFIG_MAX_MEM_MAPPED, + print_size(CFG_MAX_MEM_MAPPED, " without proper 36BIT support.\n"); } #endif diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index 47bea512c9..f07e8ab388 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -162,10 +162,10 @@ void disable_cpc_sram(void) cpc_corenet_t *cpc = (cpc_corenet_t *)CFG_SYS_FSL_CPC_ADDR; - for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) { + for (i = 0; i < CFG_SYS_NUM_CPC; i++, cpc++) { if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN) { /* find and disable LAW of SRAM */ - struct law_entry law = find_law(CONFIG_SYS_INIT_L3_ADDR); + struct law_entry law = find_law(CFG_SYS_INIT_L3_ADDR); if (law.index == -1) { printf("\nFatal error happened\n"); @@ -232,7 +232,7 @@ void enable_cpc(void) have_hwconfig = true; } - for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) { + for (i = 0; i < CFG_SYS_NUM_CPC; i++, cpc++) { if (have_hwconfig) { sprintf(cpc_subarg, "cpc%u", i + 1); cpc_args = hwconfig_sub_f("en_cpc", cpc_subarg, buffer); @@ -273,7 +273,7 @@ static void invalidate_cpc(void) int i; cpc_corenet_t *cpc = (cpc_corenet_t *)CFG_SYS_FSL_CPC_ADDR; - for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) { + for (i = 0; i < CFG_SYS_NUM_CPC; i++, cpc++) { /* skip CPC when it used as all SRAM */ if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN) continue; @@ -315,15 +315,15 @@ void fsl_erratum_a007212_workaround(void) { ccsr_gur_t __iomem *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); u32 ddr_pll_ratio; - u32 __iomem *plldgdcr1 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c20); - u32 __iomem *plldadcr1 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c28); - u32 __iomem *dpdovrcr4 = (void *)(CONFIG_SYS_DCSRBAR + 0x21e80); + u32 __iomem *plldgdcr1 = (void *)(CFG_SYS_DCSRBAR + 0x21c20); + u32 __iomem *plldadcr1 = (void *)(CFG_SYS_DCSRBAR + 0x21c28); + u32 __iomem *dpdovrcr4 = (void *)(CFG_SYS_DCSRBAR + 0x21e80); #if (CONFIG_SYS_NUM_DDR_CTLRS >= 2) - u32 __iomem *plldgdcr2 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c40); - u32 __iomem *plldadcr2 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c48); + u32 __iomem *plldgdcr2 = (void *)(CFG_SYS_DCSRBAR + 0x21c40); + u32 __iomem *plldadcr2 = (void *)(CFG_SYS_DCSRBAR + 0x21c48); #if (CONFIG_SYS_NUM_DDR_CTLRS >= 3) - u32 __iomem *plldgdcr3 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c60); - u32 __iomem *plldadcr3 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c68); + u32 __iomem *plldgdcr3 = (void *)(CFG_SYS_DCSRBAR + 0x21c60); + u32 __iomem *plldadcr3 = (void *)(CFG_SYS_DCSRBAR + 0x21c68); #endif #endif /* @@ -378,7 +378,7 @@ void fsl_erratum_a007212_workaround(void) ulong cpu_init_f(void) { extern void m8560_cpm_reset (void); -#ifdef CONFIG_SYS_DCSRBAR_PHYS +#ifdef CFG_SYS_DCSRBAR_PHYS ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); #endif #if defined(CONFIG_NXP_ESBC) && !defined(CONFIG_SYS_RAMBOOT) @@ -403,7 +403,7 @@ ulong cpu_init_f(void) #if defined(CONFIG_NXP_ESBC) && !defined(CONFIG_SYS_RAMBOOT) /* Disable the LAW created for NOR flash by the PBI commands */ - law = find_law(CONFIG_SYS_PBI_FLASH_BASE); + law = find_law(CFG_SYS_PBI_FLASH_BASE); if (law.index != -1) disable_law(law.index); @@ -430,7 +430,7 @@ ulong cpu_init_f(void) /* Invalidate the CPC before DDR gets enabled */ invalidate_cpc(); - #ifdef CONFIG_SYS_DCSRBAR_PHYS + #ifdef CFG_SYS_DCSRBAR_PHYS /* set DCSRCR so that DCSR space is 1G */ setbits_be32(&gur->dcsrcr, FSL_CORENET_DCSR_SZ_1G); in_be32(&gur->dcsrcr); @@ -533,7 +533,7 @@ int l2cache_init(void) asm("msync;isync"); cache_ctl = l2cache->l2ctl; -#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR) +#if defined(CONFIG_SYS_RAMBOOT) && defined(CFG_SYS_INIT_L2_ADDR) if (cache_ctl & MPC85xx_L2CTL_L2E) { /* Clear L2 SRAM memory-mapped base address */ out_be32(&l2cache->l2srbar0, 0x0); @@ -590,15 +590,15 @@ int l2cache_init(void) if (l2cache->l2ctl & MPC85xx_L2CTL_L2E) { puts("already enabled"); -#if defined(CONFIG_SYS_INIT_L2_ADDR) && defined(CONFIG_SYS_FLASH_BASE) +#if defined(CFG_SYS_INIT_L2_ADDR) && defined(CFG_SYS_FLASH_BASE) u32 l2srbar = l2cache->l2srbar0; if (l2cache->l2ctl & MPC85xx_L2CTL_L2SRAM_ENTIRE - && l2srbar >= CONFIG_SYS_FLASH_BASE) { - l2srbar = CONFIG_SYS_INIT_L2_ADDR; + && l2srbar >= CFG_SYS_FLASH_BASE) { + l2srbar = CFG_SYS_INIT_L2_ADDR; l2cache->l2srbar0 = l2srbar; - printf(", moving to 0x%08x", CONFIG_SYS_INIT_L2_ADDR); + printf(", moving to 0x%08x", CFG_SYS_INIT_L2_ADDR); } -#endif /* CONFIG_SYS_INIT_L2_ADDR */ +#endif /* CFG_SYS_INIT_L2_ADDR */ puts("\n"); } else { asm("msync;isync"); @@ -625,9 +625,9 @@ int l2cache_init(void) #endif /* enable the cache */ - mtspr(SPRN_L2CSR0, CONFIG_SYS_INIT_L2CSR0); + mtspr(SPRN_L2CSR0, CFG_SYS_INIT_L2CSR0); - if (CONFIG_SYS_INIT_L2CSR0 & L2CSR0_L2E) { + if (CFG_SYS_INIT_L2CSR0 & L2CSR0_L2E) { while (!(mfspr(SPRN_L2CSR0) & L2CSR0_L2E)) ; print_size((l2cfg0 & 0x3fff) * 64 * 1024, " enabled\n"); @@ -656,7 +656,7 @@ skip_l2: int cpu_init_r(void) { __maybe_unused u32 svr = get_svr(); -#ifdef CONFIG_SYS_LBC_LCRR +#ifdef CFG_SYS_LBC_LCRR fsl_lbc_t *lbc = (void __iomem *)LBC_BASE_ADDR; #endif #if defined(CONFIG_PPC_SPINTABLE_COMPATIBLE) && defined(CONFIG_MP) @@ -763,13 +763,13 @@ int cpu_init_r(void) #ifdef CONFIG_SYS_FSL_ERRATUM_A005871 if (IS_SVR_REV(svr, 1, 0)) { int i; - __be32 *p = (void __iomem *)CONFIG_SYS_DCSRBAR + 0xb004c; + __be32 *p = (void __iomem *)CFG_SYS_DCSRBAR + 0xb004c; for (i = 0; i < 12; i++) { p += i + (i > 5 ? 11 : 0); out_be32(p, 0x2); } - p = (void __iomem *)CONFIG_SYS_DCSRBAR + 0xb0108; + p = (void __iomem *)CFG_SYS_DCSRBAR + 0xb0108; out_be32(p, 0x34); } #endif @@ -799,18 +799,18 @@ int cpu_init_r(void) { if (SVR_MAJ(svr) < 3) { void *p; - p = (void *)CONFIG_SYS_DCSRBAR + 0x20520; + p = (void *)CFG_SYS_DCSRBAR + 0x20520; setbits_be32(p, 1 << (31 - 14)); } } #endif -#ifdef CONFIG_SYS_LBC_LCRR +#ifdef CFG_SYS_LBC_LCRR /* * Modify the CLKDIV field of LCRR register to improve the writing * speed for NOR flash. */ - clrsetbits_be32(&lbc->lcrr, LCRR_CLKDIV, CONFIG_SYS_LBC_LCRR); + clrsetbits_be32(&lbc->lcrr, LCRR_CLKDIV, CFG_SYS_LBC_LCRR); __raw_readl(&lbc->lcrr); isync(); #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_LBC103 @@ -850,7 +850,7 @@ int cpu_init_r(void) */ if (IS_SVR_REV(get_svr(), 1, 0)) { struct dcsr_dcfg_regs *dcfg = (struct dcsr_dcfg_regs *) - (CONFIG_SYS_DCSRBAR + CONFIG_SYS_DCSR_DCFG_OFFSET); + (CFG_SYS_DCSRBAR + CFG_SYS_DCSR_DCFG_OFFSET); setbits_be32(&dcfg->ecccr1, (DCSR_DCFG_ECC_DISABLE_USB1 | DCSR_DCFG_ECC_DISABLE_USB2)); diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init_early.c b/arch/powerpc/cpu/mpc85xx/cpu_init_early.c index 18bfa2aed1..a67f37e3af 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init_early.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init_early.c @@ -17,15 +17,15 @@ DECLARE_GLOBAL_DATA_PTR; #ifdef CONFIG_A003399_NOR_WORKAROUND void setup_ifc(void) { - struct fsl_ifc ifc_regs = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL}; + struct fsl_ifc ifc_regs = {(void *)CFG_SYS_IFC_ADDR, (void *)NULL}; u32 _mas0, _mas1, _mas2, _mas3, _mas7; - phys_addr_t flash_phys = CONFIG_SYS_FLASH_BASE_PHYS; + phys_addr_t flash_phys = CFG_SYS_FLASH_BASE_PHYS; /* * Adjust the TLB we were running out of to match the phys addr of the * chip select we are adjusting and will return to. */ - flash_phys += (~CONFIG_SYS_AMASK0) + 1 - 4*1024*1024; + flash_phys += (~CFG_SYS_AMASK0) + 1 - 4*1024*1024; _mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(15); _mas1 = MAS1_VALID | MAS1_TID(0) | MAS1_TS | MAS1_IPROT | @@ -52,7 +52,7 @@ void setup_ifc(void) * * TLB entry is created for IVPR + IVOR15 to map on valid OP code address * bacause flash's physical address is going to change as - * CONFIG_SYS_FLASH_BASE_PHYS. + * CFG_SYS_FLASH_BASE_PHYS. */ _mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(CONFIG_SYS_PPC_E500_DEBUG_TLB); @@ -72,9 +72,9 @@ void setup_ifc(void) #endif /* Change flash's physical address */ - ifc_out32(&(ifc_regs.gregs->cspr_cs[0].cspr), CONFIG_SYS_CSPR0); - ifc_out32(&(ifc_regs.gregs->csor_cs[0].csor), CONFIG_SYS_CSOR0); - ifc_out32(&(ifc_regs.gregs->amask_cs[0].amask), CONFIG_SYS_AMASK0); + ifc_out32(&(ifc_regs.gregs->cspr_cs[0].cspr), CFG_SYS_CSPR0); + ifc_out32(&(ifc_regs.gregs->csor_cs[0].csor), CFG_SYS_CSOR0); + ifc_out32(&(ifc_regs.gregs->amask_cs[0].amask), CFG_SYS_AMASK0); return; } @@ -101,7 +101,7 @@ void cpu_init_early_f(void *fdt) #ifdef CONFIG_ARCH_QEMU_E500 /* - * CONFIG_SYS_CCSRBAR_PHYS below may use gd->fdt_blob on ePAPR systems, + * CFG_SYS_CCSRBAR_PHYS below may use gd->fdt_blob on ePAPR systems, * so we need to populate it before it accesses it. */ gd->fdt_blob = fdt; @@ -109,9 +109,9 @@ void cpu_init_early_f(void *fdt) mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(13); mas1 = MAS1_VALID | MAS1_TID(0) | MAS1_TS | MAS1_TSIZE(BOOKE_PAGESZ_1M); - mas2 = FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR, MAS2_I|MAS2_G); - mas3 = FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_PHYS, 0, MAS3_SW|MAS3_SR); - mas7 = FSL_BOOKE_MAS7(CONFIG_SYS_CCSRBAR_PHYS); + mas2 = FSL_BOOKE_MAS2(CFG_SYS_CCSRBAR, MAS2_I|MAS2_G); + mas3 = FSL_BOOKE_MAS3(CFG_SYS_CCSRBAR_PHYS, 0, MAS3_SW|MAS3_SR); + mas7 = FSL_BOOKE_MAS7(CFG_SYS_CCSRBAR_PHYS); write_tlb(mas0, mas1, mas2, mas3, mas7); diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c index 1161938d30..a7e1df104d 100644 --- a/arch/powerpc/cpu/mpc85xx/fdt.c +++ b/arch/powerpc/cpu/mpc85xx/fdt.c @@ -144,14 +144,14 @@ void ft_fixup_cpu(void *blob, u64 memory_limit) } #ifdef CONFIG_DEEP_SLEEP #ifdef CONFIG_SPL_MMC_BOOT - off = fdt_add_mem_rsv(blob, CONFIG_SYS_MMC_U_BOOT_START, - CONFIG_SYS_MMC_U_BOOT_SIZE); + off = fdt_add_mem_rsv(blob, CFG_SYS_MMC_U_BOOT_START, + CFG_SYS_MMC_U_BOOT_SIZE); if (off < 0) printf("Failed to reserve memory for SD deep sleep: %s\n", fdt_strerror(off)); #elif defined(CONFIG_SPL_SPI_BOOT) - off = fdt_add_mem_rsv(blob, CONFIG_SYS_SPI_FLASH_U_BOOT_START, - CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE); + off = fdt_add_mem_rsv(blob, CFG_SYS_SPI_FLASH_U_BOOT_START, + CFG_SYS_SPI_FLASH_U_BOOT_SIZE); if (off < 0) printf("Failed to reserve memory for SPI deep sleep: %s\n", fdt_strerror(off)); @@ -167,7 +167,7 @@ static inline void ft_fixup_l3cache(void *blob, int off) cpc_corenet_t *cpc = (void *)CFG_SYS_FSL_CPC_ADDR; u32 cfg0 = in_be32(&cpc->cpccfg0); - size = CPC_CFG0_SZ_K(cfg0) * 1024 * CONFIG_SYS_NUM_CPC; + size = CPC_CFG0_SZ_K(cfg0) * 1024 * CFG_SYS_NUM_CPC; num_ways = CPC_CFG0_NUM_WAYS(cfg0); line_size = CPC_CFG0_LINE_SZ(cfg0); num_sets = size / (line_size * num_ways); @@ -448,7 +448,7 @@ void fdt_add_enet_stashing(void *fdt) static void ft_fixup_clks(void *blob, const char *compat, u32 offset, unsigned long freq) { - phys_addr_t phys = offset + CONFIG_SYS_CCSRBAR_PHYS; + phys_addr_t phys = offset + CFG_SYS_CCSRBAR_PHYS; int off = fdt_node_offset_by_compat_reg(blob, compat, phys); if (off >= 0) { @@ -469,7 +469,7 @@ static void ft_fixup_dpaa_clks(void *blob) ft_fixup_clks(blob, "fsl,fman", CFG_SYS_FSL_FM1_OFFSET, sysinfo.freq_fman[0]); -#if (CONFIG_SYS_NUM_FMAN == 2) +#if (CFG_SYS_NUM_FMAN == 2) ft_fixup_clks(blob, "fsl,fman", CFG_SYS_FSL_FM2_OFFSET, sysinfo.freq_fman[1]); #endif @@ -649,7 +649,7 @@ void ft_cpu_setup(void *blob, struct bd_info *bd) #ifdef CONFIG_SYS_NS16550 do_fixup_by_compat_u32(blob, "ns16550", - "clock-frequency", CONFIG_SYS_NS16550_CLK, 1); + "clock-frequency", CFG_SYS_NS16550_CLK, 1); #endif #ifdef CONFIG_FSL_CORENET @@ -679,17 +679,17 @@ void ft_cpu_setup(void *blob, struct bd_info *bd) ft_fixup_dpaa_clks(blob); -#if defined(CONFIG_SYS_BMAN_MEM_PHYS) +#if defined(CFG_SYS_BMAN_MEM_PHYS) fdt_portal(blob, "fsl,bman-portal", "bman-portals", - (u64)CONFIG_SYS_BMAN_MEM_PHYS, - CONFIG_SYS_BMAN_MEM_SIZE); + (u64)CFG_SYS_BMAN_MEM_PHYS, + CFG_SYS_BMAN_MEM_SIZE); fdt_fixup_bportals(blob); #endif -#if defined(CONFIG_SYS_QMAN_MEM_PHYS) +#if defined(CFG_SYS_QMAN_MEM_PHYS) fdt_portal(blob, "fsl,qman-portal", "qman-portals", - (u64)CONFIG_SYS_QMAN_MEM_PHYS, - CONFIG_SYS_QMAN_MEM_SIZE); + (u64)CFG_SYS_QMAN_MEM_PHYS, + CFG_SYS_QMAN_MEM_SIZE); fdt_fixup_qportals(blob); #endif @@ -737,7 +737,7 @@ void ft_cpu_setup(void *blob, struct bd_info *bd) * beginning of CCSR. */ #define CCSR_VIRT_TO_PHYS(x) \ - (CONFIG_SYS_CCSRBAR_PHYS + ((x) - CONFIG_SYS_CCSRBAR)) + (CFG_SYS_CCSRBAR_PHYS + ((x) - CFG_SYS_CCSRBAR)) static void msg(const char *name, uint64_t uaddr, uint64_t daddr) { @@ -751,7 +751,7 @@ static void msg(const char *name, uint64_t uaddr, uint64_t daddr) * This function compares several CONFIG_xxx macros that contain physical * addresses with the corresponding nodes in the device tree, to see if * the physical addresses are all correct. For example, if - * CONFIG_SYS_NS16550_COM1 is defined, then it contains the virtual address + * CFG_SYS_NS16550_COM1 is defined, then it contains the virtual address * of the first UART. We convert this to a physical address and compare * that with the physical address of the first ns16550-compatible node * in the device tree. If they don't match, then we display a warning. @@ -783,8 +783,8 @@ int ft_verify_fdt(void *fdt) return 0; } - if (addr != CONFIG_SYS_CCSRBAR_PHYS) { - msg("CCSR", CONFIG_SYS_CCSRBAR_PHYS, addr); + if (addr != CFG_SYS_CCSRBAR_PHYS) { + msg("CCSR", CFG_SYS_CCSRBAR_PHYS, addr); /* No point in checking anything else */ return 0; } @@ -796,15 +796,15 @@ int ft_verify_fdt(void *fdt) */ aliases = fdt_path_offset(fdt, "/aliases"); if (aliases > 0) { -#ifdef CONFIG_SYS_NS16550_COM1 +#ifdef CFG_SYS_NS16550_COM1 if (!fdt_verify_alias_address(fdt, aliases, "serial0", - CCSR_VIRT_TO_PHYS(CONFIG_SYS_NS16550_COM1))) + CCSR_VIRT_TO_PHYS(CFG_SYS_NS16550_COM1))) return 0; #endif -#ifdef CONFIG_SYS_NS16550_COM2 +#ifdef CFG_SYS_NS16550_COM2 if (!fdt_verify_alias_address(fdt, aliases, "serial1", - CCSR_VIRT_TO_PHYS(CONFIG_SYS_NS16550_COM2))) + CCSR_VIRT_TO_PHYS(CFG_SYS_NS16550_COM2))) return 0; #endif } @@ -818,12 +818,12 @@ int ft_verify_fdt(void *fdt) * the 'reg' property to be wrong, so check it here. For now, we * only check for "fsl,elbc" nodes. */ -#ifdef CONFIG_SYS_LBC_ADDR +#ifdef CFG_SYS_LBC_ADDR off = fdt_node_offset_by_compatible(fdt, -1, "fsl,elbc"); if (off > 0) { const fdt32_t *reg = fdt_getprop(fdt, off, "reg", NULL); if (reg) { - uint64_t uaddr = CCSR_VIRT_TO_PHYS(CONFIG_SYS_LBC_ADDR); + uint64_t uaddr = CCSR_VIRT_TO_PHYS(CFG_SYS_LBC_ADDR); addr = fdt_translate_address(fdt, off, reg); if (uaddr != addr) { diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c b/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c index 3a6ce32f7e..9b6577e547 100644 --- a/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c @@ -203,7 +203,7 @@ void serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift, memset(serdes_prtcl_map, 0, sizeof(u8) * SERDES_PRCTL_COUNT); #ifdef CONFIG_SYS_FSL_ERRATUM_A007186 struct ccsr_sfp_regs __iomem *sfp_regs = - (struct ccsr_sfp_regs __iomem *)(CONFIG_SYS_SFP_ADDR); + (struct ccsr_sfp_regs __iomem *)(CFG_SYS_SFP_ADDR); u32 pll_num, pll_status, bc, dc, fc, pll_cr_upd, pll_cr0, pll_cr1; u32 bc_status, fc_status, dc_status, pll_sr2; serdes_corenet_t __iomem *srds_regs = (void *)sd_addr; diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c index 437ecde615..7c2de02c4c 100644 --- a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c @@ -264,9 +264,9 @@ void serdes_reset_rx(enum srds_prtcl device) } #endif -#ifndef CONFIG_SYS_DCSRBAR_PHYS -#define CONFIG_SYS_DCSRBAR_PHYS 0x80000000 /* Must be 1GB-aligned for rev1.0 */ -#define CONFIG_SYS_DCSRBAR 0x80000000 +#ifndef CFG_SYS_DCSRBAR_PHYS +#define CFG_SYS_DCSRBAR_PHYS 0x80000000 /* Must be 1GB-aligned for rev1.0 */ +#define CFG_SYS_DCSRBAR 0x80000000 #define __DCSR_NOT_DEFINED_BY_CONFIG #endif @@ -315,16 +315,16 @@ static void enable_bank(ccsr_gur_t *gur, int bank) */ { #ifdef __DCSR_NOT_DEFINED_BY_CONFIG - struct law_entry law = find_law(CONFIG_SYS_DCSRBAR_PHYS); + struct law_entry law = find_law(CFG_SYS_DCSRBAR_PHYS); int law_index; if (law.index == -1) - law_index = set_next_law(CONFIG_SYS_DCSRBAR_PHYS, + law_index = set_next_law(CFG_SYS_DCSRBAR_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_DCSR); else - set_law(law.index, CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_1M, + set_law(law.index, CFG_SYS_DCSRBAR_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_DCSR); #endif - u32 *p = (void *)CONFIG_SYS_DCSRBAR + 0x20114; + u32 *p = (void *)CFG_SYS_DCSRBAR + 0x20114; out_be32(p, rcw5); #ifdef __DCSR_NOT_DEFINED_BY_CONFIG if (law.index == -1) diff --git a/arch/powerpc/cpu/mpc85xx/liodn.c b/arch/powerpc/cpu/mpc85xx/liodn.c index 9ad48d440f..18790921dd 100644 --- a/arch/powerpc/cpu/mpc85xx/liodn.c +++ b/arch/powerpc/cpu/mpc85xx/liodn.c @@ -104,7 +104,7 @@ static void setup_fman_liodn_base(enum fsl_dpaa_dev dev, fm = (void *)CFG_SYS_FSL_FM1_ADDR; break; -#if (CONFIG_SYS_NUM_FMAN == 2) +#if (CFG_SYS_NUM_FMAN == 2) case FSL_HW_PORTAL_FMAN2: fm = (void *)CFG_SYS_FSL_FM2_ADDR; break; @@ -201,7 +201,7 @@ void set_liodns(void) setup_fman_liodn_base(FSL_HW_PORTAL_FMAN1, fman1_liodn_tbl, fman1_liodn_tbl_sz); -#if (CONFIG_SYS_NUM_FMAN == 2) +#if (CFG_SYS_NUM_FMAN == 2) set_fman_liodn(fman2_liodn_tbl, fman2_liodn_tbl_sz); setup_fman_liodn_base(FSL_HW_PORTAL_FMAN2, fman2_liodn_tbl, fman2_liodn_tbl_sz); @@ -337,9 +337,6 @@ static void fdt_fixup_liodn_tbl_fman(void *blob, for (i = 0; i < sz; i++) { int off; - if (tbl[i].compat == NULL) - continue; - /* Try the new compatible first. * If the node is missing, try the old. */ @@ -373,7 +370,7 @@ void fdt_fixup_liodn(void *blob) fdt_fixup_liodn_tbl(blob, liodn_tbl, liodn_tbl_sz); #ifdef CONFIG_SYS_DPAA_FMAN fdt_fixup_liodn_tbl_fman(blob, fman1_liodn_tbl, fman1_liodn_tbl_sz); -#if (CONFIG_SYS_NUM_FMAN == 2) +#if (CFG_SYS_NUM_FMAN == 2) fdt_fixup_liodn_tbl_fman(blob, fman2_liodn_tbl, fman2_liodn_tbl_sz); #endif #endif @@ -387,7 +384,7 @@ void fdt_fixup_liodn(void *blob) fdt_fixup_liodn_tbl(blob, rman_liodn_tbl, rman_liodn_tbl_sz); #endif - ccsr_pcix_t *pcix = (ccsr_pcix_t *)CONFIG_SYS_PCIE1_ADDR; + ccsr_pcix_t *pcix = (ccsr_pcix_t *)CFG_SYS_PCIE1_ADDR; int pci_ver = pcix->ipver1 & 0xffff, liodn_base = 0; if (pci_ver >= 0x0204) { diff --git a/arch/powerpc/cpu/mpc85xx/mp.c b/arch/powerpc/cpu/mpc85xx/mp.c index f109ecb9ff..7c47e415f0 100644 --- a/arch/powerpc/cpu/mpc85xx/mp.c +++ b/arch/powerpc/cpu/mpc85xx/mp.c @@ -193,9 +193,9 @@ u32 determine_mp_bootpg(unsigned int *pagesize) /* use last 4K of mapped memory */ - bootpg = ((gd->ram_size > CONFIG_MAX_MEM_MAPPED) ? - CONFIG_MAX_MEM_MAPPED : gd->ram_size) + - CONFIG_SYS_SDRAM_BASE - 4096; + bootpg = ((gd->ram_size > CFG_MAX_MEM_MAPPED) ? + CFG_MAX_MEM_MAPPED : gd->ram_size) + + CFG_SYS_SDRAM_BASE - 4096; if (pagesize) *pagesize = 4096; diff --git a/arch/powerpc/cpu/mpc85xx/p2041_ids.c b/arch/powerpc/cpu/mpc85xx/p2041_ids.c index 8a83346678..540a6e6e19 100644 --- a/arch/powerpc/cpu/mpc85xx/p2041_ids.c +++ b/arch/powerpc/cpu/mpc85xx/p2041_ids.c @@ -8,7 +8,7 @@ #include <asm/fsl_liodn.h> #ifdef CONFIG_SYS_DPAA_QBMAN -struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = { +struct qportal_info qp_info[CFG_SYS_QMAN_NUM_PORTALS] = { /* dqrr liodn, frame data liodn, liodn off, sdest */ SET_QP_INFO(1, 2, 1, 0), SET_QP_INFO(3, 4, 2, 1), @@ -66,7 +66,7 @@ struct fman_liodn_id_table fman1_liodn_tbl[] = { SET_FMAN_RX_1G_LIODN(1, 2, 12), SET_FMAN_RX_1G_LIODN(1, 3, 13), SET_FMAN_RX_1G_LIODN(1, 4, 14), -#if (CONFIG_SYS_NUM_FM1_10GEC == 1) +#if (CFG_SYS_NUM_FM1_10GEC == 1) SET_FMAN_RX_10G_LIODN(1, 0, 15), #endif }; diff --git a/arch/powerpc/cpu/mpc85xx/p3041_ids.c b/arch/powerpc/cpu/mpc85xx/p3041_ids.c index 7db05d9672..8f645258a5 100644 --- a/arch/powerpc/cpu/mpc85xx/p3041_ids.c +++ b/arch/powerpc/cpu/mpc85xx/p3041_ids.c @@ -8,7 +8,7 @@ #include <asm/fsl_liodn.h> #ifdef CONFIG_SYS_DPAA_QBMAN -struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = { +struct qportal_info qp_info[CFG_SYS_QMAN_NUM_PORTALS] = { /* dqrr liodn, frame data liodn, liodn off, sdest */ SET_QP_INFO(1, 2, 1, 0), SET_QP_INFO(3, 4, 2, 1), diff --git a/arch/powerpc/cpu/mpc85xx/p4080_ids.c b/arch/powerpc/cpu/mpc85xx/p4080_ids.c index 5b766f1d51..db41116202 100644 --- a/arch/powerpc/cpu/mpc85xx/p4080_ids.c +++ b/arch/powerpc/cpu/mpc85xx/p4080_ids.c @@ -8,7 +8,7 @@ #include <asm/fsl_liodn.h> #ifdef CONFIG_SYS_DPAA_QBMAN -struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = { +struct qportal_info qp_info[CFG_SYS_QMAN_NUM_PORTALS] = { /* dqrr liodn, frame data liodn, liodn off, sdest */ SET_QP_INFO( 1, 2, 1, 0), SET_QP_INFO( 3, 4, 2, 1), @@ -62,7 +62,7 @@ struct fman_liodn_id_table fman1_liodn_tbl[] = { }; int fman1_liodn_tbl_sz = ARRAY_SIZE(fman1_liodn_tbl); -#if (CONFIG_SYS_NUM_FMAN == 2) +#if (CFG_SYS_NUM_FMAN == 2) struct fman_liodn_id_table fman2_liodn_tbl[] = { SET_FMAN_RX_1G_LIODN(2, 0, 16), SET_FMAN_RX_1G_LIODN(2, 1, 17), @@ -101,7 +101,7 @@ struct liodn_id_table liodn_bases[] = { [FSL_HW_PORTAL_SEC] = SET_LIODN_BASE_2(96, 106), #ifdef CONFIG_SYS_DPAA_FMAN [FSL_HW_PORTAL_FMAN1] = SET_LIODN_BASE_1(32), -#if (CONFIG_SYS_NUM_FMAN == 2) +#if (CFG_SYS_NUM_FMAN == 2) [FSL_HW_PORTAL_FMAN2] = SET_LIODN_BASE_1(64), #endif #endif diff --git a/arch/powerpc/cpu/mpc85xx/p5040_ids.c b/arch/powerpc/cpu/mpc85xx/p5040_ids.c index e3d163af9e..bd05eae255 100644 --- a/arch/powerpc/cpu/mpc85xx/p5040_ids.c +++ b/arch/powerpc/cpu/mpc85xx/p5040_ids.c @@ -8,7 +8,7 @@ #include <asm/fsl_liodn.h> #ifdef CONFIG_SYS_DPAA_QBMAN -struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = { +struct qportal_info qp_info[CFG_SYS_QMAN_NUM_PORTALS] = { /* dqrr liodn, frame data liodn, liodn off, sdest */ SET_QP_INFO(1, 2, 1, 0), SET_QP_INFO(3, 4, 2, 1), @@ -57,7 +57,7 @@ struct fman_liodn_id_table fman1_liodn_tbl[] = { }; int fman1_liodn_tbl_sz = ARRAY_SIZE(fman1_liodn_tbl); -#if (CONFIG_SYS_NUM_FMAN == 2) +#if (CFG_SYS_NUM_FMAN == 2) struct fman_liodn_id_table fman2_liodn_tbl[] = { SET_FMAN_RX_1G_LIODN(2, 0, 17), SET_FMAN_RX_1G_LIODN(2, 1, 18), @@ -101,7 +101,7 @@ struct liodn_id_table liodn_bases[] = { #ifdef CONFIG_SYS_DPAA_FMAN [FSL_HW_PORTAL_FMAN1] = SET_LIODN_BASE_1(32), #endif -#if (CONFIG_SYS_NUM_FMAN == 2) +#if (CFG_SYS_NUM_FMAN == 2) [FSL_HW_PORTAL_FMAN2] = SET_LIODN_BASE_1(160), #endif #ifdef CONFIG_SYS_FSL_RAID_ENGINE diff --git a/arch/powerpc/cpu/mpc85xx/release.S b/arch/powerpc/cpu/mpc85xx/release.S index d37e1ccf1e..391751ce1e 100644 --- a/arch/powerpc/cpu/mpc85xx/release.S +++ b/arch/powerpc/cpu/mpc85xx/release.S @@ -276,8 +276,8 @@ __secondary_start_page: mtspr SPRN_L2CSR1,r3 #endif - lis r3,CONFIG_SYS_INIT_L2CSR0@h - ori r3,r3,CONFIG_SYS_INIT_L2CSR0@l + lis r3,CFG_SYS_INIT_L2CSR0@h + ori r3,r3,CFG_SYS_INIT_L2CSR0@l mtspr SPRN_L2CSR0,r3 isync 2: diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c index 31d0481927..9af40310b4 100644 --- a/arch/powerpc/cpu/mpc85xx/speed.c +++ b/arch/powerpc/cpu/mpc85xx/speed.c @@ -67,7 +67,7 @@ void get_sys_info(sys_info_t *sys_info) [14] = 4, /* CC4 PPL / 4 */ }; uint i, freq_c_pll[CONFIG_SYS_FSL_NUM_CC_PLLS]; -#if !defined(CONFIG_FM_PLAT_CLK_DIV) || !defined(CONFIG_PME_PLAT_CLK_DIV) +#if !defined(CFG_FM_PLAT_CLK_DIV) || !defined(CFG_PME_PLAT_CLK_DIV) uint rcw_tmp; #endif uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS]; @@ -206,7 +206,7 @@ void get_sys_info(sys_info_t *sys_info) #define FM1_CLK_SEL 0x1c000000 #define FM1_CLK_SHIFT 26 #endif -#if !defined(CONFIG_FM_PLAT_CLK_DIV) || !defined(CONFIG_PME_PLAT_CLK_DIV) +#if !defined(CFG_FM_PLAT_CLK_DIV) || !defined(CFG_PME_PLAT_CLK_DIV) #if defined(CONFIG_ARCH_T1024) rcw_tmp = in_be32(&gur->rcwsr[15]) - 4; #else @@ -215,25 +215,25 @@ void get_sys_info(sys_info_t *sys_info) #endif #ifdef CONFIG_SYS_DPAA_PME -#ifndef CONFIG_PME_PLAT_CLK_DIV +#ifndef CFG_PME_PLAT_CLK_DIV switch ((rcw_tmp & PME_CLK_SEL) >> PME_CLK_SHIFT) { case 1: - sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK]; + sys_info->freq_pme = freq_c_pll[CFG_SYS_PME_CLK]; break; case 2: - sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK] / 2; + sys_info->freq_pme = freq_c_pll[CFG_SYS_PME_CLK] / 2; break; case 3: - sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK] / 3; + sys_info->freq_pme = freq_c_pll[CFG_SYS_PME_CLK] / 3; break; case 4: - sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK] / 4; + sys_info->freq_pme = freq_c_pll[CFG_SYS_PME_CLK] / 4; break; case 6: - sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK + 1] / 2; + sys_info->freq_pme = freq_c_pll[CFG_SYS_PME_CLK + 1] / 2; break; case 7: - sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK + 1] / 3; + sys_info->freq_pme = freq_c_pll[CFG_SYS_PME_CLK + 1] / 3; break; default: printf("Error: Unknown PME clock select!\n"); @@ -243,16 +243,16 @@ void get_sys_info(sys_info_t *sys_info) } #else - sys_info->freq_pme = sys_info->freq_systembus / CONFIG_SYS_PME_CLK; + sys_info->freq_pme = sys_info->freq_systembus / CFG_SYS_PME_CLK; #endif #endif #ifdef CONFIG_SYS_DPAA_QBMAN -#ifndef CONFIG_QBMAN_CLK_DIV -#define CONFIG_QBMAN_CLK_DIV 2 +#ifndef CFG_QBMAN_CLK_DIV +#define CFG_QBMAN_CLK_DIV 2 #endif - sys_info->freq_qman = sys_info->freq_systembus / CONFIG_QBMAN_CLK_DIV; + sys_info->freq_qman = sys_info->freq_systembus / CFG_QBMAN_CLK_DIV; #endif #if defined(CONFIG_SYS_MAPLE) @@ -377,28 +377,28 @@ void get_sys_info(sys_info_t *sys_info) #endif #ifdef CONFIG_SYS_DPAA_FMAN -#ifndef CONFIG_FM_PLAT_CLK_DIV +#ifndef CFG_FM_PLAT_CLK_DIV switch ((rcw_tmp & FM1_CLK_SEL) >> FM1_CLK_SHIFT) { case 1: - sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK]; + sys_info->freq_fman[0] = freq_c_pll[CFG_SYS_FM1_CLK]; break; case 2: - sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK] / 2; + sys_info->freq_fman[0] = freq_c_pll[CFG_SYS_FM1_CLK] / 2; break; case 3: - sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK] / 3; + sys_info->freq_fman[0] = freq_c_pll[CFG_SYS_FM1_CLK] / 3; break; case 4: - sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK] / 4; + sys_info->freq_fman[0] = freq_c_pll[CFG_SYS_FM1_CLK] / 4; break; case 5: sys_info->freq_fman[0] = sys_info->freq_systembus; break; case 6: - sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK + 1] / 2; + sys_info->freq_fman[0] = freq_c_pll[CFG_SYS_FM1_CLK + 1] / 2; break; case 7: - sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK + 1] / 3; + sys_info->freq_fman[0] = freq_c_pll[CFG_SYS_FM1_CLK + 1] / 3; break; default: printf("Error: Unknown FMan1 clock select!\n"); @@ -406,32 +406,32 @@ void get_sys_info(sys_info_t *sys_info) sys_info->freq_fman[0] = sys_info->freq_systembus / 2; break; } -#if (CONFIG_SYS_NUM_FMAN) == 2 -#ifdef CONFIG_SYS_FM2_CLK +#if (CFG_SYS_NUM_FMAN) == 2 +#ifdef CFG_SYS_FM2_CLK #define FM2_CLK_SEL 0x00000038 #define FM2_CLK_SHIFT 3 rcw_tmp = in_be32(&gur->rcwsr[15]); switch ((rcw_tmp & FM2_CLK_SEL) >> FM2_CLK_SHIFT) { case 1: - sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1]; + sys_info->freq_fman[1] = freq_c_pll[CFG_SYS_FM2_CLK + 1]; break; case 2: - sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1] / 2; + sys_info->freq_fman[1] = freq_c_pll[CFG_SYS_FM2_CLK + 1] / 2; break; case 3: - sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1] / 3; + sys_info->freq_fman[1] = freq_c_pll[CFG_SYS_FM2_CLK + 1] / 3; break; case 4: - sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1] / 4; + sys_info->freq_fman[1] = freq_c_pll[CFG_SYS_FM2_CLK + 1] / 4; break; case 5: sys_info->freq_fman[1] = sys_info->freq_systembus; break; case 6: - sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK] / 2; + sys_info->freq_fman[1] = freq_c_pll[CFG_SYS_FM2_CLK] / 2; break; case 7: - sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK] / 3; + sys_info->freq_fman[1] = freq_c_pll[CFG_SYS_FM2_CLK] / 3; break; default: printf("Error: Unknown FMan2 clock select!\n"); @@ -440,9 +440,9 @@ void get_sys_info(sys_info_t *sys_info) break; } #endif -#endif /* CONFIG_SYS_NUM_FMAN == 2 */ +#endif /* CFG_SYS_NUM_FMAN == 2 */ #else - sys_info->freq_fman[0] = sys_info->freq_systembus / CONFIG_SYS_FM1_CLK; + sys_info->freq_fman[0] = sys_info->freq_systembus / CFG_SYS_FM1_CLK; #endif #endif @@ -491,7 +491,7 @@ void get_sys_info(sys_info_t *sys_info) } else { sys_info->freq_fman[0] = sys_info->freq_systembus / 2; } -#if (CONFIG_SYS_NUM_FMAN) == 2 +#if (CFG_SYS_NUM_FMAN) == 2 if (rcw_tmp & FM2_CLK_SEL) { if (rcw_tmp & HWA_ASYNC_DIV) sys_info->freq_fman[1] = freq_c_pll[HWA_CC_PLL] / 4; diff --git a/arch/powerpc/cpu/mpc85xx/spl_minimal.c b/arch/powerpc/cpu/mpc85xx/spl_minimal.c index 47df3c2ce1..ce2b9c2166 100644 --- a/arch/powerpc/cpu/mpc85xx/spl_minimal.c +++ b/arch/powerpc/cpu/mpc85xx/spl_minimal.c @@ -14,10 +14,10 @@ DECLARE_GLOBAL_DATA_PTR; ulong cpu_init_f(void) { -#ifdef CONFIG_SYS_INIT_L2_ADDR +#ifdef CFG_SYS_INIT_L2_ADDR ccsr_l2cache_t *l2cache = (void *)CFG_SYS_MPC85xx_L2_ADDR; - out_be32(&l2cache->l2srbar0, CONFIG_SYS_INIT_L2_ADDR); + out_be32(&l2cache->l2srbar0, CFG_SYS_INIT_L2_ADDR); /* set MBECCDIS=1, SBECCDIS=1 */ out_be32(&l2cache->l2errdis, diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S index 5341756974..562b6993b9 100644 --- a/arch/powerpc/cpu/mpc85xx/start.S +++ b/arch/powerpc/cpu/mpc85xx/start.S @@ -128,7 +128,7 @@ bootsect: .Lconf_pair_start: .long CONFIG_SYS_CCSRBAR_DEFAULT + CFG_SYS_MPC85xx_L2_OFFSET + MPC85xx_L2SRBAR0 /* Address: L2 memory-mapped SRAM base addr 0 */ - .long CONFIG_SYS_INIT_L2_ADDR + .long CFG_SYS_INIT_L2_ADDR .long CONFIG_SYS_CCSRBAR_DEFAULT + CFG_SYS_MPC85xx_L2_OFFSET + MPC85xx_L2ERRDIS /* Address: L2 cache error disable */ .long MPC85xx_L2ERRDIS_MBECC | MPC85xx_L2ERRDIS_SBECC @@ -428,12 +428,12 @@ l2_disabled: mtspr SPRN_BUCSR,r0 #endif -#if defined(CONFIG_SYS_INIT_DBCR) +#if defined(CFG_SYS_INIT_DBCR) lis r1,0xffff ori r1,r1,0xffff mtspr DBSR,r1 /* Clear all status bits */ - lis r0,CONFIG_SYS_INIT_DBCR@h /* DBCR0[IDM] must be set */ - ori r0,r0,CONFIG_SYS_INIT_DBCR@l + lis r0,CFG_SYS_INIT_DBCR@h /* DBCR0[IDM] must be set */ + ori r0,r0,CFG_SYS_INIT_DBCR@l mtspr DBCR0,r0 #endif @@ -573,34 +573,34 @@ nexti: mflr r1 /* R1 = our PC */ * As a general rule, TLB0 is used for short-term TLBs, and TLB1 is used for * long-term TLBs, so we use TLB0 here. */ -#if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR_PHYS) +#if (CONFIG_SYS_CCSRBAR_DEFAULT != CFG_SYS_CCSRBAR_PHYS) -#if !defined(CONFIG_SYS_CCSRBAR_PHYS_HIGH) || !defined(CONFIG_SYS_CCSRBAR_PHYS_LOW) -#error "CONFIG_SYS_CCSRBAR_PHYS_HIGH and CONFIG_SYS_CCSRBAR_PHYS_LOW) must be defined." +#if !defined(CFG_SYS_CCSRBAR_PHYS_HIGH) || !defined(CFG_SYS_CCSRBAR_PHYS_LOW) +#error "CFG_SYS_CCSRBAR_PHYS_HIGH and CFG_SYS_CCSRBAR_PHYS_LOW) must be defined." #endif create_ccsr_new_tlb: /* * Create a TLB for the new location of CCSR. Register R8 is reserved - * for the virtual address of this TLB (CONFIG_SYS_CCSRBAR). + * for the virtual address of this TLB (CFG_SYS_CCSRBAR). */ - lis r8, CONFIG_SYS_CCSRBAR@h - ori r8, r8, CONFIG_SYS_CCSRBAR@l - lis r9, (CONFIG_SYS_CCSRBAR + 0x1000)@h - ori r9, r9, (CONFIG_SYS_CCSRBAR + 0x1000)@l + lis r8, CFG_SYS_CCSRBAR@h + ori r8, r8, CFG_SYS_CCSRBAR@l + lis r9, (CFG_SYS_CCSRBAR + 0x1000)@h + ori r9, r9, (CFG_SYS_CCSRBAR + 0x1000)@l create_tlb0_entry 0, \ 0, BOOKE_PAGESZ_4K, \ - CONFIG_SYS_CCSRBAR, MAS2_I|MAS2_G, \ - CONFIG_SYS_CCSRBAR_PHYS_LOW, MAS3_SW|MAS3_SR, \ - CONFIG_SYS_CCSRBAR_PHYS_HIGH, r3 + CFG_SYS_CCSRBAR, MAS2_I|MAS2_G, \ + CFG_SYS_CCSRBAR_PHYS_LOW, MAS3_SW|MAS3_SR, \ + CFG_SYS_CCSRBAR_PHYS_HIGH, r3 /* * Create a TLB for the current location of CCSR. Register R9 is reserved - * for the virtual address of this TLB (CONFIG_SYS_CCSRBAR + 0x1000). + * for the virtual address of this TLB (CFG_SYS_CCSRBAR + 0x1000). */ create_ccsr_old_tlb: create_tlb0_entry 1, \ 0, BOOKE_PAGESZ_4K, \ - CONFIG_SYS_CCSRBAR + 0x1000, MAS2_I|MAS2_G, \ + CFG_SYS_CCSRBAR + 0x1000, MAS2_I|MAS2_G, \ CONFIG_SYS_CCSRBAR_DEFAULT, MAS3_SW|MAS3_SR, \ 0, r3 /* The default CCSR address is always a 32-bit number */ @@ -634,7 +634,7 @@ infinite_debug_loop: #ifdef CONFIG_FSL_CORENET -#define CCSR_LAWBARH0 (CONFIG_SYS_CCSRBAR + 0x1000) +#define CCSR_LAWBARH0 (CFG_SYS_CCSRBAR + 0x1000) #define LAW_SIZE_4K 0xb #define CCSRBAR_LAWAR (LAW_EN | (0x1e << 20) | LAW_SIZE_4K) #define CCSRAR_C 0x80000000 /* Commit */ @@ -644,10 +644,10 @@ create_temp_law: * On CoreNet systems, we create the temporary LAW using a special LAW * target ID of 0x1e. LAWBARH is at offset 0xc00 in CCSR. */ - lis r0, CONFIG_SYS_CCSRBAR_PHYS_HIGH@h - ori r0, r0, CONFIG_SYS_CCSRBAR_PHYS_HIGH@l - lis r1, CONFIG_SYS_CCSRBAR_PHYS_LOW@h - ori r1, r1, CONFIG_SYS_CCSRBAR_PHYS_LOW@l + lis r0, CFG_SYS_CCSRBAR_PHYS_HIGH@h + ori r0, r0, CFG_SYS_CCSRBAR_PHYS_HIGH@l + lis r1, CFG_SYS_CCSRBAR_PHYS_LOW@h + ori r1, r1, CFG_SYS_CCSRBAR_PHYS_LOW@l lis r2, CCSRBAR_LAWAR@h ori r2, r2, CCSRBAR_LAWAR@l @@ -683,10 +683,10 @@ read_old_ccsrbar: * instruction. */ write_new_ccsrbar: - lis r0, CONFIG_SYS_CCSRBAR_PHYS_HIGH@h - ori r0, r0, CONFIG_SYS_CCSRBAR_PHYS_HIGH@l - lis r1, CONFIG_SYS_CCSRBAR_PHYS_LOW@h - ori r1, r1, CONFIG_SYS_CCSRBAR_PHYS_LOW@l + lis r0, CFG_SYS_CCSRBAR_PHYS_HIGH@h + ori r0, r0, CFG_SYS_CCSRBAR_PHYS_HIGH@l + lis r1, CFG_SYS_CCSRBAR_PHYS_LOW@h + ori r1, r1, CFG_SYS_CCSRBAR_PHYS_LOW@l lis r2, CCSRAR_C@h ori r2, r2, CCSRAR_C@l @@ -723,9 +723,9 @@ write_new_ccsrbar: lwz r0, 0(r9) isync -/* CONFIG_SYS_CCSRBAR_PHYS right shifted by 12 */ -#define CCSRBAR_PHYS_RS12 ((CONFIG_SYS_CCSRBAR_PHYS_HIGH << 20) | \ - (CONFIG_SYS_CCSRBAR_PHYS_LOW >> 12)) +/* CFG_SYS_CCSRBAR_PHYS right shifted by 12 */ +#define CCSRBAR_PHYS_RS12 ((CFG_SYS_CCSRBAR_PHYS_HIGH << 20) | \ + (CFG_SYS_CCSRBAR_PHYS_LOW >> 12)) /* Write the new value to CCSRBAR. */ lis r0, CCSRBAR_PHYS_RS12@h @@ -752,10 +752,10 @@ write_new_ccsrbar: /* Delete the temporary TLBs */ delete_temp_tlbs: - delete_tlb0_entry 0, CONFIG_SYS_CCSRBAR, MAS2_I|MAS2_G, r3 - delete_tlb0_entry 1, CONFIG_SYS_CCSRBAR + 0x1000, MAS2_I|MAS2_G, r3 + delete_tlb0_entry 0, CFG_SYS_CCSRBAR, MAS2_I|MAS2_G, r3 + delete_tlb0_entry 1, CFG_SYS_CCSRBAR + 0x1000, MAS2_I|MAS2_G, r3 -#endif /* #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR_PHYS) */ +#endif /* #if (CONFIG_SYS_CCSRBAR_DEFAULT != CFG_SYS_CCSRBAR_PHYS) */ #if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500) create_ccsr_l2_tlb: @@ -765,14 +765,14 @@ create_ccsr_l2_tlb: */ create_tlb0_entry 0, \ 0, BOOKE_PAGESZ_4K, \ - CONFIG_SYS_CCSRBAR + 0xC20000, MAS2_I|MAS2_G, \ - CONFIG_SYS_CCSRBAR_PHYS_LOW + 0xC20000, MAS3_SW|MAS3_SR, \ - CONFIG_SYS_CCSRBAR_PHYS_HIGH, r3 + CFG_SYS_CCSRBAR + 0xC20000, MAS2_I|MAS2_G, \ + CFG_SYS_CCSRBAR_PHYS_LOW + 0xC20000, MAS3_SW|MAS3_SR, \ + CFG_SYS_CCSRBAR_PHYS_HIGH, r3 enable_l2_cluster_l2: /* enable L2 cache */ - lis r3, (CONFIG_SYS_CCSRBAR + 0xC20000)@h - ori r3, r3, (CONFIG_SYS_CCSRBAR + 0xC20000)@l + lis r3, (CFG_SYS_CCSRBAR + 0xC20000)@h + ori r3, r3, (CFG_SYS_CCSRBAR + 0xC20000)@l li r4, 33 /* stash id */ stw r4, 4(r3) lis r4, (L2CSR0_L2FI|L2CSR0_L2LFC)@h @@ -813,7 +813,7 @@ enable_l2_cluster_l2: beq 1b delete_ccsr_l2_tlb: - delete_tlb0_entry 0, CONFIG_SYS_CCSRBAR + 0xC20000, MAS2_I|MAS2_G, r3 + delete_tlb0_entry 0, CFG_SYS_CCSRBAR + 0xC20000, MAS2_I|MAS2_G, r3 #endif /* @@ -863,7 +863,7 @@ delete_ccsr_l2_tlb: andi. r1,r3,L1CSR0_DCE@l beq 2b #ifdef CONFIG_SYS_FSL_ERRATUM_A004510 -#define DCSR_LAWBARH0 (CONFIG_SYS_CCSRBAR + 0x1000) +#define DCSR_LAWBARH0 (CFG_SYS_CCSRBAR + 0x1000) #define LAW_SIZE_1M 0x13 #define DCSRBAR_LAWAR (LAW_EN | (0x1d << 20) | LAW_SIZE_1M) @@ -884,13 +884,13 @@ delete_ccsr_l2_tlb: rlwimi r0, r8, 16, MAS0_ESEL_MSK lis r1, FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)@h ori r1, r1, FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)@l - lis r7, CONFIG_SYS_CCSRBAR@h - ori r7, r7, CONFIG_SYS_CCSRBAR@l + lis r7, CFG_SYS_CCSRBAR@h + ori r7, r7, CFG_SYS_CCSRBAR@l ori r2, r7, MAS2_I|MAS2_G - lis r3, FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_PHYS_LOW, 0, (MAS3_SW|MAS3_SR))@h - ori r3, r3, FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_PHYS_LOW, 0, (MAS3_SW|MAS3_SR))@l - lis r4, CONFIG_SYS_CCSRBAR_PHYS_HIGH@h - ori r4, r4, CONFIG_SYS_CCSRBAR_PHYS_HIGH@l + lis r3, FSL_BOOKE_MAS3(CFG_SYS_CCSRBAR_PHYS_LOW, 0, (MAS3_SW|MAS3_SR))@h + ori r3, r3, FSL_BOOKE_MAS3(CFG_SYS_CCSRBAR_PHYS_LOW, 0, (MAS3_SW|MAS3_SR))@l + lis r4, CFG_SYS_CCSRBAR_PHYS_HIGH@h + ori r4, r4, CFG_SYS_CCSRBAR_PHYS_HIGH@l mtspr MAS0, r0 mtspr MAS1, r1 mtspr MAS2, r2 @@ -1132,7 +1132,7 @@ create_init_ram_area: create_tlb1_entry 15, \ 1, BOOKE_PAGESZ_1M, \ CONFIG_VAL(SYS_MONITOR_BASE) & 0xfff00000, MAS2_I|MAS2_G, \ - CONFIG_SYS_PBI_FLASH_WINDOW & 0xfff00000, MAS3_SX|MAS3_SW|MAS3_SR, \ + CFG_SYS_PBI_FLASH_WINDOW & 0xfff00000, MAS3_SX|MAS3_SW|MAS3_SR, \ 0, r6 /* @@ -1148,7 +1148,7 @@ create_init_ram_area: create_tlb1_entry 15, \ 1, BOOKE_PAGESZ_1M, \ CONFIG_VAL(SYS_MONITOR_BASE) & 0xfff00000, MAS2_I|MAS2_G, \ - CONFIG_SYS_INIT_L3_ADDR & 0xfff00000, MAS3_SX|MAS3_SW|MAS3_SR, \ + CFG_SYS_INIT_L3_ADDR & 0xfff00000, MAS3_SX|MAS3_SW|MAS3_SR, \ 0, r6 #else @@ -1164,19 +1164,19 @@ create_init_ram_area: #endif /* create a temp mapping in AS=1 to the stack */ -#if defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) && \ - defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH) +#if defined(CFG_SYS_INIT_RAM_ADDR_PHYS_LOW) && \ + defined(CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH) create_tlb1_entry 14, \ 1, BOOKE_PAGESZ_16K, \ - CONFIG_SYS_INIT_RAM_ADDR, 0, \ - CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW, MAS3_SX|MAS3_SW|MAS3_SR, \ - CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH, r6 + CFG_SYS_INIT_RAM_ADDR, 0, \ + CFG_SYS_INIT_RAM_ADDR_PHYS_LOW, MAS3_SX|MAS3_SW|MAS3_SR, \ + CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH, r6 #else create_tlb1_entry 14, \ 1, BOOKE_PAGESZ_16K, \ - CONFIG_SYS_INIT_RAM_ADDR, 0, \ - CONFIG_SYS_INIT_RAM_ADDR, MAS3_SX|MAS3_SW|MAS3_SR, \ + CFG_SYS_INIT_RAM_ADDR, 0, \ + CFG_SYS_INIT_RAM_ADDR, MAS3_SX|MAS3_SW|MAS3_SR, \ 0, r6 #endif @@ -1194,8 +1194,8 @@ switch_as: /* Allocate Initial RAM in data cache. */ - lis r3,CONFIG_SYS_INIT_RAM_ADDR@h - ori r3,r3,CONFIG_SYS_INIT_RAM_ADDR@l + lis r3,CFG_SYS_INIT_RAM_ADDR@h + ori r3,r3,CFG_SYS_INIT_RAM_ADDR@l mfspr r2, L1CFG0 andi. r2, r2, 0x1ff /* cache size * 1024 / (2 * L1 line size) */ @@ -1230,11 +1230,11 @@ switch_as: .globl _start_cont _start_cont: /* Setup the stack in initial RAM,could be L2-as-SRAM or L1 dcache*/ - lis r3,(CONFIG_SYS_INIT_RAM_ADDR)@h - ori r3,r3,((CONFIG_SYS_INIT_SP_OFFSET-16)&~0xf)@l /* Align to 16 */ + lis r3,(CFG_SYS_INIT_RAM_ADDR)@h + ori r3,r3,((CFG_SYS_INIT_SP_OFFSET-16)&~0xf)@l /* Align to 16 */ #if CONFIG_VAL(SYS_MALLOC_F_LEN) -#if CONFIG_VAL(SYS_MALLOC_F_LEN) + GENERATED_GBL_DATA_SIZE > CONFIG_SYS_INIT_RAM_SIZE +#if CONFIG_VAL(SYS_MALLOC_F_LEN) + GENERATED_GBL_DATA_SIZE > CFG_SYS_INIT_RAM_SIZE #error "SYS_MALLOC_F_LEN too large to fit into initial RAM." #endif @@ -1243,8 +1243,8 @@ _start_cont: #endif /* End of RAM */ - lis r4,(CONFIG_SYS_INIT_RAM_ADDR)@h - ori r4,r4,(CONFIG_SYS_INIT_RAM_SIZE)@l + lis r4,(CFG_SYS_INIT_RAM_ADDR)@h + ori r4,r4,(CFG_SYS_INIT_RAM_SIZE)@l li r0,0 @@ -1826,8 +1826,8 @@ trap_init: .globl unlock_ram_in_cache unlock_ram_in_cache: /* invalidate the INIT_RAM section */ - lis r3,(CONFIG_SYS_INIT_RAM_ADDR & ~(CONFIG_SYS_CACHELINE_SIZE-1))@h - ori r3,r3,(CONFIG_SYS_INIT_RAM_ADDR & ~(CONFIG_SYS_CACHELINE_SIZE-1))@l + lis r3,(CFG_SYS_INIT_RAM_ADDR & ~(CONFIG_SYS_CACHELINE_SIZE-1))@h + ori r3,r3,(CFG_SYS_INIT_RAM_ADDR & ~(CONFIG_SYS_CACHELINE_SIZE-1))@l mfspr r4,L1CFG0 andi. r4,r4,0x1ff slwi r4,r4,(10 - 1 - L1_CACHE_SHIFT) @@ -1844,8 +1844,8 @@ unlock_ram_in_cache: sync /* Invalidate the TLB entries for the cache */ - lis r3,CONFIG_SYS_INIT_RAM_ADDR@h - ori r3,r3,CONFIG_SYS_INIT_RAM_ADDR@l + lis r3,CFG_SYS_INIT_RAM_ADDR@h + ori r3,r3,CFG_SYS_INIT_RAM_ADDR@l tlbivax 0,r3 addi r3,r3,0x1000 tlbivax 0,r3 diff --git a/arch/powerpc/cpu/mpc85xx/t1024_ids.c b/arch/powerpc/cpu/mpc85xx/t1024_ids.c index d2744bb9f8..bab076b2b1 100644 --- a/arch/powerpc/cpu/mpc85xx/t1024_ids.c +++ b/arch/powerpc/cpu/mpc85xx/t1024_ids.c @@ -8,7 +8,7 @@ #include <asm/fsl_liodn.h> #ifdef CONFIG_SYS_DPAA_QBMAN -struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = { +struct qportal_info qp_info[CFG_SYS_QMAN_NUM_PORTALS] = { /* dqrr liodn, frame data liodn, liodn off, sdest */ SET_QP_INFO(1, 27, 1, 0), SET_QP_INFO(2, 28, 1, 0), diff --git a/arch/powerpc/cpu/mpc85xx/t1040_ids.c b/arch/powerpc/cpu/mpc85xx/t1040_ids.c index 99b52bacda..59f4f9c669 100644 --- a/arch/powerpc/cpu/mpc85xx/t1040_ids.c +++ b/arch/powerpc/cpu/mpc85xx/t1040_ids.c @@ -8,7 +8,7 @@ #include <asm/fsl_liodn.h> #ifdef CONFIG_SYS_DPAA_QBMAN -struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = { +struct qportal_info qp_info[CFG_SYS_QMAN_NUM_PORTALS] = { /* dqrr liodn, frame data liodn, liodn off, sdest */ SET_QP_INFO(1, 27, 1, 0), SET_QP_INFO(2, 28, 1, 0), diff --git a/arch/powerpc/cpu/mpc85xx/t2080_ids.c b/arch/powerpc/cpu/mpc85xx/t2080_ids.c index 17521dc3a4..390bb11537 100644 --- a/arch/powerpc/cpu/mpc85xx/t2080_ids.c +++ b/arch/powerpc/cpu/mpc85xx/t2080_ids.c @@ -8,7 +8,7 @@ #include <asm/fsl_liodn.h> #ifdef CONFIG_SYS_DPAA_QBMAN -struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = { +struct qportal_info qp_info[CFG_SYS_QMAN_NUM_PORTALS] = { /* dqrr liodn, frame data liodn, liodn off, sdest */ SET_QP_INFO(1, 27, 1, 0), SET_QP_INFO(2, 28, 1, 0), diff --git a/arch/powerpc/cpu/mpc85xx/t4240_ids.c b/arch/powerpc/cpu/mpc85xx/t4240_ids.c index 172dbdbe46..37ea7788cc 100644 --- a/arch/powerpc/cpu/mpc85xx/t4240_ids.c +++ b/arch/powerpc/cpu/mpc85xx/t4240_ids.c @@ -8,7 +8,7 @@ #include <asm/fsl_liodn.h> #ifdef CONFIG_SYS_DPAA_QBMAN -struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = { +struct qportal_info qp_info[CFG_SYS_QMAN_NUM_PORTALS] = { /* dqrr liodn, frame data liodn, liodn off, sdest */ SET_QP_INFO(1, 27, 1, 0), SET_QP_INFO(2, 28, 1, 0), @@ -122,7 +122,7 @@ struct fman_liodn_id_table fman1_liodn_tbl[] = { SET_FMAN_RX_10G_LIODN(1, 1, 95), }; int fman1_liodn_tbl_sz = ARRAY_SIZE(fman1_liodn_tbl); -#if (CONFIG_SYS_NUM_FMAN == 2) +#if (CFG_SYS_NUM_FMAN == 2) struct fman_liodn_id_table fman2_liodn_tbl[] = { SET_FMAN_RX_1G_LIODN(2, 0, 88), SET_FMAN_RX_1G_LIODN(2, 1, 89), @@ -175,7 +175,7 @@ struct liodn_id_table liodn_bases[] = { [FSL_HW_PORTAL_SEC] = SET_LIODN_BASE_2(462, 558), #ifdef CONFIG_SYS_DPAA_FMAN [FSL_HW_PORTAL_FMAN1] = SET_LIODN_BASE_1(973), -#if (CONFIG_SYS_NUM_FMAN == 2) +#if (CFG_SYS_NUM_FMAN == 2) [FSL_HW_PORTAL_FMAN2] = SET_LIODN_BASE_1(1069), #endif #endif diff --git a/arch/powerpc/cpu/mpc85xx/tlb.c b/arch/powerpc/cpu/mpc85xx/tlb.c index 81e60722f9..2a78f0fe50 100644 --- a/arch/powerpc/cpu/mpc85xx/tlb.c +++ b/arch/powerpc/cpu/mpc85xx/tlb.c @@ -302,16 +302,16 @@ uint64_t tlb_map_range(ulong v_addr, phys_addr_t p_addr, uint64_t size, unsigned int setup_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg) { - unsigned int ram_tlb_address = (unsigned int)CONFIG_SYS_DDR_SDRAM_BASE; + unsigned int ram_tlb_address = (unsigned int)CFG_SYS_DDR_SDRAM_BASE; u64 memsize = (u64)memsize_in_meg << 20; u64 size; - size = min(memsize, (u64)CONFIG_MAX_MEM_MAPPED); + size = min(memsize, (u64)CFG_MAX_MEM_MAPPED); size = tlb_map_range(ram_tlb_address, p_addr, size, TLB_MAP_RAM); - if (size || memsize > CONFIG_MAX_MEM_MAPPED) { - print_size(memsize > CONFIG_MAX_MEM_MAPPED ? - memsize - CONFIG_MAX_MEM_MAPPED + size : size, + if (size || memsize > CFG_MAX_MEM_MAPPED) { + print_size(memsize > CFG_MAX_MEM_MAPPED ? + memsize - CFG_MAX_MEM_MAPPED + size : size, " of DDR memory left unmapped in U-Boot\n"); #ifndef CONFIG_SPL_BUILD puts(" "); @@ -324,13 +324,13 @@ unsigned int setup_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int setup_ddr_tlbs(unsigned int memsize_in_meg) { return - setup_ddr_tlbs_phys(CONFIG_SYS_DDR_SDRAM_BASE, memsize_in_meg); + setup_ddr_tlbs_phys(CFG_SYS_DDR_SDRAM_BASE, memsize_in_meg); } /* Invalidate the DDR TLBs for the requested size */ void clear_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg) { - u32 vstart = CONFIG_SYS_DDR_SDRAM_BASE; + u32 vstart = CFG_SYS_DDR_SDRAM_BASE; unsigned long epn; u32 tsize, valid, ptr; phys_addr_t rpn = 0; @@ -351,7 +351,7 @@ void clear_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg) void clear_ddr_tlbs(unsigned int memsize_in_meg) { - clear_ddr_tlbs_phys(CONFIG_SYS_DDR_SDRAM_BASE, memsize_in_meg); + clear_ddr_tlbs_phys(CFG_SYS_DDR_SDRAM_BASE, memsize_in_meg); } diff --git a/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds b/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds index f28826c5d1..d918b4395b 100644 --- a/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds +++ b/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds @@ -64,7 +64,7 @@ SECTIONS _end = .; #if CONFIG_IS_ENABLED(SYS_MPC85XX_NO_RESETVEC) -#if defined(CONFIG_SDCARD) && !defined(CONFIG_SYS_MMC_U_BOOT_OFFS) +#if defined(CONFIG_SDCARD) && !defined(CFG_SYS_MMC_U_BOOT_OFFS) mmc_u_boot_offs = .; #endif #endif @@ -101,7 +101,7 @@ SECTIONS .resetvec IMAGE_TEXT_BASE + RESET_VECTOR_OFFSET : { KEEP(*(.resetvec)) } = 0xffff -#if defined(CONFIG_SDCARD) && !defined(CONFIG_SYS_MMC_U_BOOT_OFFS) +#if defined(CONFIG_SDCARD) && !defined(CFG_SYS_MMC_U_BOOT_OFFS) mmc_u_boot_offs = .; #endif #endif diff --git a/arch/powerpc/cpu/mpc85xx/u-boot.lds b/arch/powerpc/cpu/mpc85xx/u-boot.lds index fa3aa954cb..3af0dfdf33 100644 --- a/arch/powerpc/cpu/mpc85xx/u-boot.lds +++ b/arch/powerpc/cpu/mpc85xx/u-boot.lds @@ -5,8 +5,8 @@ #include "config.h" -#ifdef CONFIG_RESET_VECTOR_ADDRESS -#define RESET_VECTOR_ADDRESS CONFIG_RESET_VECTOR_ADDRESS +#ifdef CFG_RESET_VECTOR_ADDRESS +#define RESET_VECTOR_ADDRESS CFG_RESET_VECTOR_ADDRESS #else #define RESET_VECTOR_ADDRESS 0xfffffffc #endif diff --git a/arch/powerpc/cpu/mpc8xx/start.S b/arch/powerpc/cpu/mpc8xx/start.S index 0ebb7b33a8..1f1107e61d 100644 --- a/arch/powerpc/cpu/mpc8xx/start.S +++ b/arch/powerpc/cpu/mpc8xx/start.S @@ -141,8 +141,8 @@ in_flash: mtspr DER, r2 /* set up the stack on top of internal DPRAM */ - lis r3, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE)@h - ori r3, r3, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE)@l + lis r3, (CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_RAM_SIZE)@h + ori r3, r3, (CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_RAM_SIZE)@l stw r0, -4(r3) stw r0, -8(r3) addi r1, r3, -8 diff --git a/arch/powerpc/cpu/mpc8xxx/cpu.c b/arch/powerpc/cpu/mpc8xxx/cpu.c index 7f20190922..73d28f2a4e 100644 --- a/arch/powerpc/cpu/mpc8xxx/cpu.c +++ b/arch/powerpc/cpu/mpc8xxx/cpu.c @@ -343,29 +343,3 @@ int fixup_cpu(void) #endif return 0; } - -#ifndef CONFIG_DM_ETH -/* - * Initializes on-chip ethernet controllers. - * to override, implement board_eth_init() - */ -int cpu_eth_init(struct bd_info *bis) -{ -#if defined(CONFIG_UEC_ETH) - uec_standard_init(bis); -#endif - -#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_MPC85XX_FEC) - tsec_standard_init(bis); -#endif - -#ifdef CONFIG_FMAN_ENET - fm_standard_init(bis); -#endif - -#ifdef CONFIG_VSC9953 - vsc9953_init(bis); -#endif - return 0; -} -#endif diff --git a/arch/powerpc/cpu/mpc8xxx/fsl_pamu.c b/arch/powerpc/cpu/mpc8xxx/fsl_pamu.c index 1101b9138f..1c051d1898 100644 --- a/arch/powerpc/cpu/mpc8xxx/fsl_pamu.c +++ b/arch/powerpc/cpu/mpc8xxx/fsl_pamu.c @@ -230,7 +230,7 @@ static int pamu_config_spaace(uint32_t liodn, int pamu_init(void) { - u32 base_addr = CONFIG_SYS_PAMU_ADDR; + u32 base_addr = CFG_SYS_PAMU_ADDR; struct ccsr_pamu *regs; u32 i = 0; u64 ppaact_phys, ppaact_lim, ppaact_size; @@ -292,7 +292,7 @@ int pamu_init(void) void pamu_enable(void) { u32 i = 0; - u32 base_addr = CONFIG_SYS_PAMU_ADDR; + u32 base_addr = CFG_SYS_PAMU_ADDR; for (i = 0; i < CONFIG_NUM_PAMU; i++) { setbits_be32((void *)base_addr + PAMU_PCR_OFFSET, PAMU_PCR_PE); @@ -304,7 +304,7 @@ void pamu_enable(void) void pamu_reset(void) { u32 i = 0; - u32 base_addr = CONFIG_SYS_PAMU_ADDR; + u32 base_addr = CFG_SYS_PAMU_ADDR; struct ccsr_pamu *regs; for (i = 0; i < CONFIG_NUM_PAMU; i++) { @@ -328,7 +328,7 @@ void pamu_reset(void) void pamu_disable(void) { u32 i = 0; - u32 base_addr = CONFIG_SYS_PAMU_ADDR; + u32 base_addr = CFG_SYS_PAMU_ADDR; for (i = 0; i < CONFIG_NUM_PAMU; i++) { diff --git a/arch/powerpc/cpu/mpc8xxx/law.c b/arch/powerpc/cpu/mpc8xxx/law.c index dd274166c0..35409dc882 100644 --- a/arch/powerpc/cpu/mpc8xxx/law.c +++ b/arch/powerpc/cpu/mpc8xxx/law.c @@ -309,42 +309,42 @@ void init_laws(void) */ switch ((bootloc & FSL_CORENET_RCWSR6_BOOT_LOC) >> 23) { case 0x0: /* boot from PCIE1 */ - set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS, + set_next_law(CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCIE_1); - set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS, + set_next_law(CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCIE_1); break; case 0x1: /* boot from PCIE2 */ - set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS, + set_next_law(CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCIE_2); - set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS, + set_next_law(CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCIE_2); break; case 0x2: /* boot from PCIE3 */ - set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS, + set_next_law(CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCIE_3); - set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS, + set_next_law(CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCIE_3); break; case 0x8: /* boot from SRIO1 */ - set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS, + set_next_law(CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_RIO_1); - set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS, + set_next_law(CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_RIO_1); break; case 0x9: /* boot from SRIO2 */ - set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS, + set_next_law(CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_RIO_2); - set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS, + set_next_law(CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_RIO_2); break; diff --git a/arch/powerpc/cpu/mpc8xxx/pamu_table.c b/arch/powerpc/cpu/mpc8xxx/pamu_table.c index d917e9dfb6..b906279226 100644 --- a/arch/powerpc/cpu/mpc8xxx/pamu_table.c +++ b/arch/powerpc/cpu/mpc8xxx/pamu_table.c @@ -16,22 +16,22 @@ void construct_pamu_addr_table(struct pamu_addr_tbl *tbl, int *num_entries) int j; tbl->start_addr[i] = - (uint64_t)virt_to_phys((void *)CONFIG_SYS_SDRAM_BASE); - tbl->size[i] = (phys_size_t)(min(gd->ram_size, CONFIG_MAX_MEM_MAPPED)); + (uint64_t)virt_to_phys((void *)CFG_SYS_SDRAM_BASE); + tbl->size[i] = (phys_size_t)(min(gd->ram_size, CFG_MAX_MEM_MAPPED)); tbl->end_addr[i] = tbl->start_addr[i] + tbl->size[i] - 1; i++; -#ifdef CONFIG_SYS_FLASH_BASE_PHYS +#ifdef CFG_SYS_FLASH_BASE_PHYS tbl->start_addr[i] = - (uint64_t)virt_to_phys((void *)CONFIG_SYS_FLASH_BASE_PHYS); + (uint64_t)virt_to_phys((void *)CFG_SYS_FLASH_BASE_PHYS); tbl->size[i] = 256 * 1024 * 1024; /* 256MB flash */ tbl->end_addr[i] = tbl->start_addr[i] + tbl->size[i] - 1; i++; #endif -#if (defined(CONFIG_SPL_BUILD) && (CONFIG_SYS_INIT_L3_VADDR)) +#if (defined(CONFIG_SPL_BUILD) && (CFG_SYS_INIT_L3_VADDR)) tbl->start_addr[i] = - (uint64_t)virt_to_phys((void *)CONFIG_SYS_INIT_L3_VADDR); + (uint64_t)virt_to_phys((void *)CFG_SYS_INIT_L3_VADDR); tbl->size[i] = 256 * 1024; /* 256K CPC flash */ tbl->end_addr[i] = tbl->start_addr[i] + tbl->size[i] - 1; diff --git a/arch/powerpc/cpu/mpc8xxx/srio.c b/arch/powerpc/cpu/mpc8xxx/srio.c index c815d19384..c0b4a1217d 100644 --- a/arch/powerpc/cpu/mpc8xxx/srio.c +++ b/arch/powerpc/cpu/mpc8xxx/srio.c @@ -33,17 +33,17 @@ #define _DEVDISR_SRIO2 FSL_CORENET_DEVDISR_SRIO2 #endif #define _DEVDISR_RMU FSL_CORENET_DEVDISR_RMU - #define CONFIG_SYS_MPC8xxx_GUTS_ADDR CFG_SYS_MPC85xx_GUTS_ADDR + #define CFG_SYS_MPC8xxx_GUTS_ADDR CFG_SYS_MPC85xx_GUTS_ADDR #elif defined(CONFIG_MPC85xx) #define _DEVDISR_SRIO1 MPC85xx_DEVDISR_SRIO #define _DEVDISR_SRIO2 MPC85xx_DEVDISR_SRIO #define _DEVDISR_RMU MPC85xx_DEVDISR_RMSG - #define CONFIG_SYS_MPC8xxx_GUTS_ADDR CFG_SYS_MPC85xx_GUTS_ADDR + #define CFG_SYS_MPC8xxx_GUTS_ADDR CFG_SYS_MPC85xx_GUTS_ADDR #elif defined(CONFIG_MPC86xx) #define _DEVDISR_SRIO1 MPC86xx_DEVDISR_SRIO #define _DEVDISR_SRIO2 MPC86xx_DEVDISR_SRIO #define _DEVDISR_RMU MPC86xx_DEVDISR_RMSG - #define CONFIG_SYS_MPC8xxx_GUTS_ADDR \ + #define CFG_SYS_MPC8xxx_GUTS_ADDR \ (&((immap_t *)CONFIG_SYS_IMMR)->im_gur) #else #error "No defines for DEVDISR_SRIO" @@ -230,7 +230,7 @@ host_ok: void srio_init(void) { - ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC8xxx_GUTS_ADDR; + ccsr_gur_t *gur = (void *)CFG_SYS_MPC8xxx_GUTS_ADDR; int srio1_used = 0, srio2_used = 0; u32 *devdisr; @@ -240,8 +240,8 @@ void srio_init(void) devdisr = &gur->devdisr; #endif if (is_serdes_configured(SRIO1)) { - set_next_law(CONFIG_SYS_SRIO1_MEM_PHYS, - law_size_bits(CONFIG_SYS_SRIO1_MEM_SIZE), + set_next_law(CFG_SYS_SRIO1_MEM_PHYS, + law_size_bits(CFG_SYS_SRIO1_MEM_SIZE), LAW_TRGT_IF_RIO_1); srio1_used = 1; #ifdef CONFIG_SYS_FSL_ERRATUM_SRIO_A004034 @@ -256,8 +256,8 @@ void srio_init(void) #ifdef CONFIG_SRIO2 if (is_serdes_configured(SRIO2)) { - set_next_law(CONFIG_SYS_SRIO2_MEM_PHYS, - law_size_bits(CONFIG_SYS_SRIO2_MEM_SIZE), + set_next_law(CFG_SYS_SRIO2_MEM_PHYS, + law_size_bits(CFG_SYS_SRIO2_MEM_SIZE), LAW_TRGT_IF_RIO_2); srio2_used = 1; #ifdef CONFIG_SYS_FSL_ERRATUM_SRIO_A004034 @@ -301,44 +301,44 @@ void srio_boot_master(int port) /* configure inbound window for slave's u-boot image */ debug("SRIOBOOT - MASTER: Inbound window for slave's image; " "Local = 0x%llx, Srio = 0x%llx, Size = 0x%x\n", - (u64)CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS, - (u64)CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1, - CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE); + (u64)CFG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS, + (u64)CFG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1, + CFG_SRIO_PCIE_BOOT_IMAGE_SIZE); out_be32((void *)&srio->atmu.port[port - 1].inbw[0].riwtar, - CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS >> 12); + CFG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS >> 12); out_be32((void *)&srio->atmu.port[port - 1].inbw[0].riwbar, - CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 >> 12); + CFG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 >> 12); out_be32((void *)&srio->atmu.port[port - 1].inbw[0].riwar, SRIO_IB_ATMU_AR - | atmu_size_mask(CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE)); + | atmu_size_mask(CFG_SRIO_PCIE_BOOT_IMAGE_SIZE)); /* configure inbound window for slave's u-boot image */ debug("SRIOBOOT - MASTER: Inbound window for slave's image; " "Local = 0x%llx, Srio = 0x%llx, Size = 0x%x\n", - (u64)CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS, - (u64)CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2, - CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE); + (u64)CFG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS, + (u64)CFG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2, + CFG_SRIO_PCIE_BOOT_IMAGE_SIZE); out_be32((void *)&srio->atmu.port[port - 1].inbw[1].riwtar, - CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS >> 12); + CFG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS >> 12); out_be32((void *)&srio->atmu.port[port - 1].inbw[1].riwbar, - CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 >> 12); + CFG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 >> 12); out_be32((void *)&srio->atmu.port[port - 1].inbw[1].riwar, SRIO_IB_ATMU_AR - | atmu_size_mask(CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE)); + | atmu_size_mask(CFG_SRIO_PCIE_BOOT_IMAGE_SIZE)); /* configure inbound window for slave's ucode and ENV */ debug("SRIOBOOT - MASTER: Inbound window for slave's ucode and ENV; " "Local = 0x%llx, Srio = 0x%llx, Size = 0x%x\n", - (u64)CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS, - (u64)CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS, - CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE); + (u64)CFG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS, + (u64)CFG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS, + CFG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE); out_be32((void *)&srio->atmu.port[port - 1].inbw[2].riwtar, - CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS >> 12); + CFG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS >> 12); out_be32((void *)&srio->atmu.port[port - 1].inbw[2].riwbar, - CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS >> 12); + CFG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS >> 12); out_be32((void *)&srio->atmu.port[port - 1].inbw[2].riwar, SRIO_IB_ATMU_AR - | atmu_size_mask(CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE)); + | atmu_size_mask(CFG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE)); } void srio_boot_master_release_slave(int port) @@ -368,11 +368,11 @@ void srio_boot_master_release_slave(int port) if (port - 1) out_be32((void *)&srio->atmu.port[port - 1] .outbw[1].rowbar, - CONFIG_SYS_SRIO2_MEM_PHYS >> 12); + CFG_SYS_SRIO2_MEM_PHYS >> 12); else out_be32((void *)&srio->atmu.port[port - 1] .outbw[1].rowbar, - CONFIG_SYS_SRIO1_MEM_PHYS >> 12); + CFG_SYS_SRIO1_MEM_PHYS >> 12); out_be32((void *)&srio->atmu.port[port - 1] .outbw[1].rowar, SRIO_OB_ATMU_AR_MAINT @@ -390,12 +390,12 @@ void srio_boot_master_release_slave(int port) if (port - 1) out_be32((void *)&srio->atmu.port[port - 1] .outbw[2].rowbar, - (CONFIG_SYS_SRIO2_MEM_PHYS + (CFG_SYS_SRIO2_MEM_PHYS + SRIO_MAINT_WIN_SIZE) >> 12); else out_be32((void *)&srio->atmu.port[port - 1] .outbw[2].rowbar, - (CONFIG_SYS_SRIO1_MEM_PHYS + (CFG_SYS_SRIO1_MEM_PHYS + SRIO_MAINT_WIN_SIZE) >> 12); out_be32((void *)&srio->atmu.port[port - 1] .outbw[2].rowar, @@ -407,10 +407,10 @@ void srio_boot_master_release_slave(int port) * by the maint-outbound window */ if (port - 1) { - out_be32((void *)CONFIG_SYS_SRIO2_MEM_VIRT + out_be32((void *)CFG_SYS_SRIO2_MEM_VIRT + SRIO_LCSBA1CSR_OFFSET, SRIO_LCSBA1CSR); - while (in_be32((void *)CONFIG_SYS_SRIO2_MEM_VIRT + while (in_be32((void *)CFG_SYS_SRIO2_MEM_VIRT + SRIO_LCSBA1CSR_OFFSET) != SRIO_LCSBA1CSR) ; @@ -418,15 +418,15 @@ void srio_boot_master_release_slave(int port) * And then set the BRR register * to release slave core */ - out_be32((void *)CONFIG_SYS_SRIO2_MEM_VIRT + out_be32((void *)CFG_SYS_SRIO2_MEM_VIRT + SRIO_MAINT_WIN_SIZE - + CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET, - CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK); + + CFG_SRIO_PCIE_BOOT_BRR_OFFSET, + CFG_SRIO_PCIE_BOOT_RELEASE_MASK); } else { - out_be32((void *)CONFIG_SYS_SRIO1_MEM_VIRT + out_be32((void *)CFG_SYS_SRIO1_MEM_VIRT + SRIO_LCSBA1CSR_OFFSET, SRIO_LCSBA1CSR); - while (in_be32((void *)CONFIG_SYS_SRIO1_MEM_VIRT + while (in_be32((void *)CFG_SYS_SRIO1_MEM_VIRT + SRIO_LCSBA1CSR_OFFSET) != SRIO_LCSBA1CSR) ; @@ -434,10 +434,10 @@ void srio_boot_master_release_slave(int port) * And then set the BRR register * to release slave core */ - out_be32((void *)CONFIG_SYS_SRIO1_MEM_VIRT + out_be32((void *)CFG_SYS_SRIO1_MEM_VIRT + SRIO_MAINT_WIN_SIZE - + CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET, - CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK); + + CFG_SRIO_PCIE_BOOT_BRR_OFFSET, + CFG_SRIO_PCIE_BOOT_RELEASE_MASK); } debug("SRIOBOOT - MASTER: " "Release slave successfully! Now the slave should start up!\n"); diff --git a/arch/powerpc/dts/kmcent2-u-boot.dtsi b/arch/powerpc/dts/kmcent2-u-boot.dtsi index 28f303b749..d027762764 100644 --- a/arch/powerpc/dts/kmcent2-u-boot.dtsi +++ b/arch/powerpc/dts/kmcent2-u-boot.dtsi @@ -74,24 +74,6 @@ compatible = "fsl,pcie-t104x"; law_trgt_if = <0>; }; - - binman { - filename = "u-boot.bin"; - skip-at-start = <CONFIG_TEXT_BASE>; - sort-by-offset; - pad-byte = <0xff>; - size = <CONFIG_SYS_MONITOR_LEN>; - - u-boot-with-ucode-ptr { - offset = <CONFIG_TEXT_BASE>; - optional-ucode; - }; - - u-boot-dtb-with-ucode { - align = <256>; - }; - powerpc-mpc85xx-bootpg-resetvec { - offset = <(CONFIG_RESET_VECTOR_ADDRESS - 0xffc)>; - }; - }; }; + +#include "u-boot.dtsi" diff --git a/arch/powerpc/dts/u-boot.dtsi b/arch/powerpc/dts/u-boot.dtsi index b4b5257362..6b7375cff2 100644 --- a/arch/powerpc/dts/u-boot.dtsi +++ b/arch/powerpc/dts/u-boot.dtsi @@ -23,11 +23,11 @@ u-boot-dtb-with-ucode { align = <4>; }; -#ifndef CONFIG_RESET_VECTOR_ADDRESS -#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc +#ifndef CFG_RESET_VECTOR_ADDRESS +#define CFG_RESET_VECTOR_ADDRESS 0xfffffffc #endif powerpc-mpc85xx-bootpg-resetvec { - offset = <(CONFIG_RESET_VECTOR_ADDRESS - 0xffc)>; + offset = <(CFG_RESET_VECTOR_ADDRESS - 0xffc)>; }; }; }; diff --git a/arch/powerpc/include/asm/config.h b/arch/powerpc/include/asm/config.h index 79fe567b58..f0702cab14 100644 --- a/arch/powerpc/include/asm/config.h +++ b/arch/powerpc/include/asm/config.h @@ -14,13 +14,13 @@ #define HWCONFIG_BUFFER_SIZE 256 #endif -#ifndef CONFIG_MAX_MEM_MAPPED +#ifndef CFG_MAX_MEM_MAPPED #if defined(CONFIG_E500) || \ defined(CONFIG_MPC86xx) || \ defined(CONFIG_E300) -#define CONFIG_MAX_MEM_MAPPED ((phys_size_t)2 << 30) +#define CFG_MAX_MEM_MAPPED ((phys_size_t)2 << 30) #else -#define CONFIG_MAX_MEM_MAPPED (256 << 20) +#define CFG_MAX_MEM_MAPPED (256 << 20) #endif #endif @@ -32,14 +32,6 @@ #define BPTR_VIRT_ADDR 0xfffff000 #endif -/* Since so many PPC SOCs have a semi-common LBC, define this here */ -#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) || \ - defined(CONFIG_MPC83xx) -#if !defined(CONFIG_FSL_IFC) -#define CONFIG_FSL_LBC -#endif -#endif - /* The TSEC driver uses the PHYLIB infrastructure */ #if defined(CONFIG_TSEC_ENET) && defined(CONFIG_PHYLIB) #include <config_phylib_all_drivers.h> @@ -52,7 +44,7 @@ * TODO: Convert this to a clock driver exists that can give us the UART * clock here. */ -#define CONFIG_SYS_NS16550_CLK get_serial_clock() +#define CFG_SYS_NS16550_CLK get_serial_clock() #endif #endif /* _ASM_CONFIG_H_ */ diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 25d1b48617..d731ac3f4d 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -8,12 +8,6 @@ /* SoC specific defines for Freescale MPC85xx (PQ3) and QorIQ processors */ -/* - * This macro should be removed when we no longer care about backwards - * compatibility with older operating systems. - */ -#define CONFIG_PPC_SPINTABLE_COMPATIBLE - #include <fsl_ddrc_version.h> #if defined(CONFIG_ARCH_MPC8548) @@ -23,37 +17,22 @@ #define CFG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 #elif defined(CONFIG_ARCH_P1010) -#define CONFIG_FSL_SDHC_V2_3 -#define CONFIG_TSECV2 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4 -/* P1011 is single core version of P1020 */ -#elif defined(CONFIG_ARCH_P1011) -#define CONFIG_TSECV2 - -#elif defined(CONFIG_ARCH_P1020) -#define CONFIG_TSECV2 - #elif defined(CONFIG_ARCH_P1021) -#define CONFIG_TSECV2 #define QE_MURAM_SIZE 0x6000UL #define MAX_QE_RISC 1 #define QE_NUM_OF_SNUM 28 #elif defined(CONFIG_ARCH_P1023) -#define CONFIG_SYS_NUM_FMAN 1 -#define CONFIG_SYS_NUM_FM1_DTSEC 2 -#define CONFIG_SYS_QMAN_NUM_PORTALS 3 -#define CONFIG_SYS_BMAN_NUM_PORTALS 3 -#define CONFIG_SYS_FM_MURAM_SIZE 0x10000 - -/* P1024 is lower end variant of P1020 */ -#elif defined(CONFIG_ARCH_P1024) -#define CONFIG_TSECV2 +#define CFG_SYS_NUM_FMAN 1 +#define CFG_SYS_NUM_FM1_DTSEC 2 +#define CFG_SYS_QMAN_NUM_PORTALS 3 +#define CFG_SYS_BMAN_NUM_PORTALS 3 +#define CFG_SYS_FM_MURAM_SIZE 0x10000 /* P1025 is lower end variant of P1021 */ #elif defined(CONFIG_ARCH_P1025) -#define CONFIG_TSECV2 #define QE_MURAM_SIZE 0x6000UL #define MAX_QE_RISC 1 #define QE_NUM_OF_SNUM 28 @@ -65,32 +44,32 @@ #define CFG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 #elif defined(CONFIG_ARCH_P2041) /* also supports P2040 */ -#define CONFIG_SYS_NUM_FMAN 1 -#define CONFIG_SYS_NUM_FM1_DTSEC 5 -#define CONFIG_SYS_NUM_FM1_10GEC 1 -#define CONFIG_SYS_FM_MURAM_SIZE 0x28000 +#define CFG_SYS_NUM_FMAN 1 +#define CFG_SYS_NUM_FM1_DTSEC 5 +#define CFG_SYS_NUM_FM1_10GEC 1 +#define CFG_SYS_FM_MURAM_SIZE 0x28000 #define CFG_SYS_FSL_SRIO_MAX_PORTS 2 #define CFG_SYS_FSL_SRIO_OB_WIN_NUM 9 #define CFG_SYS_FSL_SRIO_IB_WIN_NUM 5 #define CFG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000 #elif defined(CONFIG_ARCH_P3041) -#define CONFIG_SYS_NUM_FMAN 1 -#define CONFIG_SYS_NUM_FM1_DTSEC 5 -#define CONFIG_SYS_NUM_FM1_10GEC 1 -#define CONFIG_SYS_FM_MURAM_SIZE 0x28000 +#define CFG_SYS_NUM_FMAN 1 +#define CFG_SYS_NUM_FM1_DTSEC 5 +#define CFG_SYS_NUM_FM1_10GEC 1 +#define CFG_SYS_FM_MURAM_SIZE 0x28000 #define CFG_SYS_FSL_SRIO_MAX_PORTS 2 #define CFG_SYS_FSL_SRIO_OB_WIN_NUM 9 #define CFG_SYS_FSL_SRIO_IB_WIN_NUM 5 #define CFG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000 #elif defined(CONFIG_ARCH_P4080) /* also supports P4040 */ -#define CONFIG_SYS_NUM_FMAN 2 -#define CONFIG_SYS_NUM_FM1_DTSEC 4 -#define CONFIG_SYS_NUM_FM2_DTSEC 4 -#define CONFIG_SYS_NUM_FM1_10GEC 1 -#define CONFIG_SYS_NUM_FM2_10GEC 1 -#define CONFIG_SYS_FM_MURAM_SIZE 0x28000 +#define CFG_SYS_NUM_FMAN 2 +#define CFG_SYS_NUM_FM1_DTSEC 4 +#define CFG_SYS_NUM_FM2_DTSEC 4 +#define CFG_SYS_NUM_FM1_10GEC 1 +#define CFG_SYS_NUM_FM2_10GEC 1 +#define CFG_SYS_FM_MURAM_SIZE 0x28000 #define CFG_SYS_FSL_SRIO_MAX_PORTS 2 #define CFG_SYS_FSL_SRIO_OB_WIN_NUM 9 #define CFG_SYS_FSL_SRIO_IB_WIN_NUM 5 @@ -98,47 +77,43 @@ #define CFG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xff000000 #elif defined(CONFIG_ARCH_P5040) -#define CONFIG_SYS_NUM_FMAN 2 -#define CONFIG_SYS_NUM_FM1_DTSEC 5 -#define CONFIG_SYS_NUM_FM1_10GEC 1 -#define CONFIG_SYS_NUM_FM2_DTSEC 5 -#define CONFIG_SYS_NUM_FM2_10GEC 1 -#define CONFIG_SYS_FM_MURAM_SIZE 0x28000 +#define CFG_SYS_NUM_FMAN 2 +#define CFG_SYS_NUM_FM1_DTSEC 5 +#define CFG_SYS_NUM_FM1_10GEC 1 +#define CFG_SYS_NUM_FM2_DTSEC 5 +#define CFG_SYS_NUM_FM2_10GEC 1 +#define CFG_SYS_FM_MURAM_SIZE 0x28000 #define CFG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000 #elif defined(CONFIG_ARCH_BSC9131) -#define CONFIG_FSL_SDHC_V2_3 -#define CONFIG_TSECV2 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 3 #elif defined(CONFIG_ARCH_BSC9132) -#define CONFIG_FSL_SDHC_V2_3 -#define CONFIG_TSECV2 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 3 #elif defined(CONFIG_ARCH_T4240) #ifdef CONFIG_ARCH_T4240 #define CFG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4 } -#define CONFIG_SYS_NUM_FM1_DTSEC 8 -#define CONFIG_SYS_NUM_FM1_10GEC 2 -#define CONFIG_SYS_NUM_FM2_DTSEC 8 -#define CONFIG_SYS_NUM_FM2_10GEC 2 +#define CFG_SYS_NUM_FM1_DTSEC 8 +#define CFG_SYS_NUM_FM1_10GEC 2 +#define CFG_SYS_NUM_FM2_DTSEC 8 +#define CFG_SYS_NUM_FM2_10GEC 2 #else -#define CONFIG_SYS_NUM_FM1_DTSEC 6 -#define CONFIG_SYS_NUM_FM1_10GEC 1 -#define CONFIG_SYS_NUM_FM2_DTSEC 8 -#define CONFIG_SYS_NUM_FM2_10GEC 1 +#define CFG_SYS_NUM_FM1_DTSEC 6 +#define CFG_SYS_NUM_FM1_10GEC 1 +#define CFG_SYS_NUM_FM2_DTSEC 8 +#define CFG_SYS_NUM_FM2_10GEC 1 #endif #define CONFIG_SYS_FSL_SRDS_1 #define CONFIG_SYS_FSL_SRDS_2 #define CFG_SYS_FSL_SRDS_3 #define CFG_SYS_FSL_SRDS_4 -#define CONFIG_SYS_NUM_FMAN 2 -#define CONFIG_SYS_PME_CLK 0 +#define CFG_SYS_NUM_FMAN 2 +#define CFG_SYS_PME_CLK 0 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 -#define CONFIG_SYS_FM1_CLK 3 -#define CONFIG_SYS_FM2_CLK 3 -#define CONFIG_SYS_FM_MURAM_SIZE 0x60000 +#define CFG_SYS_FM1_CLK 3 +#define CFG_SYS_FM2_CLK 3 +#define CFG_SYS_FM_MURAM_SIZE 0x60000 #define CFG_SYS_FSL_SRIO_MAX_PORTS 2 #define CFG_SYS_FSL_SRIO_OB_WIN_NUM 9 #define CFG_SYS_FSL_SRIO_IB_WIN_NUM 5 @@ -146,38 +121,35 @@ #elif defined(CONFIG_ARCH_B4860) || defined(CONFIG_ARCH_B4420) #define CONFIG_SYS_FSL_SRDS_1 #define CONFIG_SYS_FSL_SRDS_2 -#define CONFIG_SYS_NUM_FMAN 1 -#define CONFIG_SYS_FM1_CLK 0 +#define CFG_SYS_NUM_FMAN 1 +#define CFG_SYS_FM1_CLK 0 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4 -#define CONFIG_SYS_FM_MURAM_SIZE 0x60000 +#define CFG_SYS_FM_MURAM_SIZE 0x60000 #ifdef CONFIG_ARCH_B4860 -#define CONFIG_MAX_DSP_CPUS 12 -#define CONFIG_NUM_DSP_CPUS 6 #define CFG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 } -#define CONFIG_SYS_NUM_FM1_DTSEC 6 -#define CONFIG_SYS_NUM_FM1_10GEC 2 +#define CFG_SYS_NUM_FM1_DTSEC 6 +#define CFG_SYS_NUM_FM1_10GEC 2 #define CFG_SYS_FSL_SRIO_MAX_PORTS 2 #define CFG_SYS_FSL_SRIO_OB_WIN_NUM 9 #define CFG_SYS_FSL_SRIO_IB_WIN_NUM 5 #else -#define CONFIG_MAX_DSP_CPUS 2 #define CFG_SYS_FSL_CLUSTER_CLOCKS { 1, 4 } -#define CONFIG_SYS_NUM_FM1_DTSEC 4 -#define CONFIG_SYS_NUM_FM1_10GEC 0 +#define CFG_SYS_NUM_FM1_DTSEC 4 +#define CFG_SYS_NUM_FM1_10GEC 0 #endif #elif defined(CONFIG_ARCH_T1040) || defined(CONFIG_ARCH_T1042) #define CFG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 } #define CONFIG_SYS_FSL_SRDS_1 -#define CONFIG_SYS_NUM_FMAN 1 -#define CONFIG_SYS_NUM_FM1_DTSEC 5 -#define CONFIG_PME_PLAT_CLK_DIV 2 -#define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV +#define CFG_SYS_NUM_FMAN 1 +#define CFG_SYS_NUM_FM1_DTSEC 5 +#define CFG_PME_PLAT_CLK_DIV 2 +#define CFG_SYS_PME_CLK CFG_PME_PLAT_CLK_DIV #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 -#define CONFIG_FM_PLAT_CLK_DIV 1 -#define CONFIG_SYS_FM1_CLK CONFIG_FM_PLAT_CLK_DIV -#define CONFIG_SYS_FM_MURAM_SIZE 0x30000 +#define CFG_FM_PLAT_CLK_DIV 1 +#define CFG_SYS_FM1_CLK CFG_FM_PLAT_CLK_DIV +#define CFG_SYS_FM_MURAM_SIZE 0x30000 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE #define QE_MURAM_SIZE 0x6000UL #define MAX_QE_RISC 1 @@ -186,42 +158,39 @@ #elif defined(CONFIG_ARCH_T1024) #define CFG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 } #define CONFIG_SYS_FSL_SRDS_1 -#define CONFIG_SYS_NUM_FMAN 1 -#define CONFIG_SYS_NUM_FM1_DTSEC 4 -#define CONFIG_SYS_NUM_FM1_10GEC 1 -#define CONFIG_FSL_FM_10GEC_REGULAR_NOTATION +#define CFG_SYS_NUM_FMAN 1 +#define CFG_SYS_NUM_FM1_DTSEC 4 +#define CFG_SYS_NUM_FM1_10GEC 1 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 -#define CONFIG_SYS_FM1_CLK 0 -#define CONFIG_QBMAN_CLK_DIV 1 -#define CONFIG_SYS_FM_MURAM_SIZE 0x30000 +#define CFG_SYS_FM1_CLK 0 +#define CFG_QBMAN_CLK_DIV 1 +#define CFG_SYS_FM_MURAM_SIZE 0x30000 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE #define QE_MURAM_SIZE 0x6000UL #define MAX_QE_RISC 1 #define QE_NUM_OF_SNUM 28 #elif defined(CONFIG_ARCH_T2080) -#define CONFIG_SYS_NUM_FMAN 1 +#define CFG_SYS_NUM_FMAN 1 #define CFG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 } #define CONFIG_SYS_FSL_SRDS_1 #if defined(CONFIG_ARCH_T2080) -#define CONFIG_SYS_NUM_FM1_DTSEC 8 -#define CONFIG_SYS_NUM_FM1_10GEC 4 +#define CFG_SYS_NUM_FM1_DTSEC 8 +#define CFG_SYS_NUM_FM1_10GEC 4 #define CONFIG_SYS_FSL_SRDS_2 #define CFG_SYS_FSL_SRIO_MAX_PORTS 2 #define CFG_SYS_FSL_SRIO_OB_WIN_NUM 9 #define CFG_SYS_FSL_SRIO_IB_WIN_NUM 5 #endif -#define CONFIG_PME_PLAT_CLK_DIV 1 -#define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV -#define CONFIG_SYS_FM1_CLK 0 +#define CFG_PME_PLAT_CLK_DIV 1 +#define CFG_SYS_PME_CLK CFG_PME_PLAT_CLK_DIV +#define CFG_SYS_FM1_CLK 0 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 -#define CONFIG_SYS_FM_MURAM_SIZE 0x28000 +#define CFG_SYS_FM_MURAM_SIZE 0x28000 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE #elif defined(CONFIG_ARCH_C29X) -#define CONFIG_FSL_SDHC_V2_3 -#define CONFIG_TSECV2_1 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 #define CFG_SYS_FSL_SEC_IDX_OFFSET 0x20000 diff --git a/arch/powerpc/include/asm/fsl_dma.h b/arch/powerpc/include/asm/fsl_dma.h index 727f4a7e92..1459db74be 100644 --- a/arch/powerpc/include/asm/fsl_dma.h +++ b/arch/powerpc/include/asm/fsl_dma.h @@ -117,7 +117,7 @@ typedef struct fsl_dma { void dma_init(void); int dmacpy(phys_addr_t dest, phys_addr_t src, phys_size_t n); #if (defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)) -void dma_meminit(uint val, uint size); +void dma_meminit(uint size); #endif #endif diff --git a/arch/powerpc/include/asm/fsl_lbc.h b/arch/powerpc/include/asm/fsl_lbc.h index 5038cb9f59..a03f091c30 100644 --- a/arch/powerpc/include/asm/fsl_lbc.h +++ b/arch/powerpc/include/asm/fsl_lbc.h @@ -469,7 +469,7 @@ extern void print_lbc_regs(void); extern void init_early_memctl_regs(void); extern void upmconfig(uint upm, uint *table, uint size); -#define LBC_BASE_ADDR ((fsl_lbc_t *)CONFIG_SYS_LBC_ADDR) +#define LBC_BASE_ADDR ((fsl_lbc_t *)CFG_SYS_LBC_ADDR) #define get_lbc_lcrr() (in_be32(&(LBC_BASE_ADDR)->lcrr)) #define get_lbc_lbcr() (in_be32(&(LBC_BASE_ADDR)->lbcr)) #define get_lbc_br(i) (in_be32(&(LBC_BASE_ADDR)->bank[i].br)) diff --git a/arch/powerpc/include/asm/fsl_liodn.h b/arch/powerpc/include/asm/fsl_liodn.h index de85bcfdcf..0af3d8902a 100644 --- a/arch/powerpc/include/asm/fsl_liodn.h +++ b/arch/powerpc/include/asm/fsl_liodn.h @@ -18,15 +18,15 @@ struct srio_liodn_id_table { #define SET_SRIO_LIODN_1(port, idA) \ { .id = { idA }, .num_ids = 1, .portid = port, \ .reg_offset[0] = offsetof(ccsr_gur_t, rio##port##liodnr) \ - + CFG_SYS_MPC85xx_GUTS_OFFSET + CONFIG_SYS_CCSRBAR, \ + + CFG_SYS_MPC85xx_GUTS_OFFSET + CFG_SYS_CCSRBAR, \ } #define SET_SRIO_LIODN_2(port, idA, idB) \ { .id = { idA, idB }, .num_ids = 2, .portid = port, \ .reg_offset[0] = offsetof(ccsr_gur_t, rio##port##liodnr) \ - + CFG_SYS_MPC85xx_GUTS_OFFSET + CONFIG_SYS_CCSRBAR, \ + + CFG_SYS_MPC85xx_GUTS_OFFSET + CFG_SYS_CCSRBAR, \ .reg_offset[1] = offsetof(ccsr_gur_t, rio##port##maintliodnr) \ - + CFG_SYS_MPC85xx_GUTS_OFFSET + CONFIG_SYS_CCSRBAR, \ + + CFG_SYS_MPC85xx_GUTS_OFFSET + CFG_SYS_CCSRBAR, \ } #define SET_SRIO_LIODN_BASE(port, id_a) \ @@ -70,22 +70,22 @@ extern void fdt_fixup_liodn(void *blob); { .compat[0] = name1, \ .compat[1] = name2, \ .id = { idA }, .num_ids = 1, \ - .reg_offset = off + CONFIG_SYS_CCSRBAR, \ - .compat_offset = compatoff + CONFIG_SYS_CCSRBAR_PHYS, \ + .reg_offset = off + CFG_SYS_CCSRBAR, \ + .compat_offset = compatoff + CFG_SYS_CCSRBAR_PHYS, \ } #define SET_LIODN_ENTRY_1(name, idA, off, compatoff) \ { .compat = name, \ .id = { idA }, .num_ids = 1, \ - .reg_offset = off + CONFIG_SYS_CCSRBAR, \ - .compat_offset = compatoff + CONFIG_SYS_CCSRBAR_PHYS, \ + .reg_offset = off + CFG_SYS_CCSRBAR, \ + .compat_offset = compatoff + CFG_SYS_CCSRBAR_PHYS, \ } #define SET_LIODN_ENTRY_2(name, idA, idB, off, compatoff) \ { .compat = name, \ .id = { idA, idB }, .num_ids = 2, \ - .reg_offset = off + CONFIG_SYS_CCSRBAR, \ - .compat_offset = compatoff + CONFIG_SYS_CCSRBAR_PHYS, \ + .reg_offset = off + CFG_SYS_CCSRBAR, \ + .compat_offset = compatoff + CFG_SYS_CCSRBAR_PHYS, \ } #define SET_GUTS_LIODN(compat, liodn, name, compatoff) \ diff --git a/arch/powerpc/include/asm/fsl_pci.h b/arch/powerpc/include/asm/fsl_pci.h index 06f9bfb8ac..809ab1d418 100644 --- a/arch/powerpc/include/asm/fsl_pci.h +++ b/arch/powerpc/include/asm/fsl_pci.h @@ -193,35 +193,35 @@ int fsl_pcie_init_board(int busno); #define SET_STD_PCI_INFO(x, num) \ { \ - x.regs = CONFIG_SYS_PCI##num##_ADDR; \ - x.mem_bus = CONFIG_SYS_PCI##num##_MEM_BUS; \ - x.mem_phys = CONFIG_SYS_PCI##num##_MEM_PHYS; \ - x.mem_size = CONFIG_SYS_PCI##num##_MEM_SIZE; \ - x.io_bus = CONFIG_SYS_PCI##num##_IO_BUS; \ - x.io_phys = CONFIG_SYS_PCI##num##_IO_PHYS; \ - x.io_size = CONFIG_SYS_PCI##num##_IO_SIZE; \ + x.regs = CFG_SYS_PCI##num##_ADDR; \ + x.mem_bus = CFG_SYS_PCI##num##_MEM_BUS; \ + x.mem_phys = CFG_SYS_PCI##num##_MEM_PHYS; \ + x.mem_size = CFG_SYS_PCI##num##_MEM_SIZE; \ + x.io_bus = CFG_SYS_PCI##num##_IO_BUS; \ + x.io_phys = CFG_SYS_PCI##num##_IO_PHYS; \ + x.io_size = CFG_SYS_PCI##num##_IO_SIZE; \ x.law = LAW_TRGT_IF_PCI_##num; \ x.pci_num = num; \ } #define SET_STD_PCIE_INFO(x, num) \ { \ - x.regs = CONFIG_SYS_PCIE##num##_ADDR; \ - x.mem_bus = CONFIG_SYS_PCIE##num##_MEM_BUS; \ - x.mem_phys = CONFIG_SYS_PCIE##num##_MEM_PHYS; \ - x.mem_size = CONFIG_SYS_PCIE##num##_MEM_SIZE; \ - x.io_bus = CONFIG_SYS_PCIE##num##_IO_BUS; \ - x.io_phys = CONFIG_SYS_PCIE##num##_IO_PHYS; \ - x.io_size = CONFIG_SYS_PCIE##num##_IO_SIZE; \ + x.regs = CFG_SYS_PCIE##num##_ADDR; \ + x.mem_bus = CFG_SYS_PCIE##num##_MEM_BUS; \ + x.mem_phys = CFG_SYS_PCIE##num##_MEM_PHYS; \ + x.mem_size = CFG_SYS_PCIE##num##_MEM_SIZE; \ + x.io_bus = CFG_SYS_PCIE##num##_IO_BUS; \ + x.io_phys = CFG_SYS_PCIE##num##_IO_PHYS; \ + x.io_size = CFG_SYS_PCIE##num##_IO_SIZE; \ x.law = LAW_TRGT_IF_PCIE_##num; \ x.pci_num = num; \ } #define __FT_FSL_PCI_SETUP(blob, compat, num) \ - ft_fsl_pci_setup(blob, compat, CONFIG_SYS_PCI##num##_ADDR) + ft_fsl_pci_setup(blob, compat, CFG_SYS_PCI##num##_ADDR) #define __FT_FSL_PCIE_SETUP(blob, compat, num) \ - ft_fsl_pci_setup(blob, compat, CONFIG_SYS_PCIE##num##_ADDR) + ft_fsl_pci_setup(blob, compat, CFG_SYS_PCIE##num##_ADDR) #define FT_FSL_PCI1_SETUP __FT_FSL_PCI_SETUP(blob, FSL_PCI_COMPAT, 1) #define FT_FSL_PCI2_SETUP __FT_FSL_PCI_SETUP(blob, FSL_PCI_COMPAT, 2) diff --git a/arch/powerpc/include/asm/fsl_portals.h b/arch/powerpc/include/asm/fsl_portals.h index b1fd6bd5ce..54ef4fb629 100644 --- a/arch/powerpc/include/asm/fsl_portals.h +++ b/arch/powerpc/include/asm/fsl_portals.h @@ -11,7 +11,7 @@ enum fsl_dpaa_dev { FSL_HW_PORTAL_SEC, #ifdef CONFIG_SYS_DPAA_FMAN FSL_HW_PORTAL_FMAN1, -#if (CONFIG_SYS_NUM_FMAN == 2) +#if (CFG_SYS_NUM_FMAN == 2) FSL_HW_PORTAL_FMAN2, #endif #endif diff --git a/arch/powerpc/include/asm/fsl_secure_boot.h b/arch/powerpc/include/asm/fsl_secure_boot.h index 3e707600f2..236098e718 100644 --- a/arch/powerpc/include/asm/fsl_secure_boot.h +++ b/arch/powerpc/include/asm/fsl_secure_boot.h @@ -9,50 +9,30 @@ #ifdef CONFIG_NXP_ESBC #if defined(CONFIG_FSL_CORENET) -#define CONFIG_SYS_PBI_FLASH_BASE 0xc0000000 +#define CFG_SYS_PBI_FLASH_BASE 0xc0000000 #else -#define CONFIG_SYS_PBI_FLASH_BASE 0xce000000 +#define CFG_SYS_PBI_FLASH_BASE 0xce000000 #endif -#define CONFIG_SYS_PBI_FLASH_WINDOW 0xcff80000 +#define CFG_SYS_PBI_FLASH_WINDOW 0xcff80000 #if defined(CONFIG_TARGET_T2080QDS) || \ defined(CONFIG_TARGET_T2080RDB) || \ - defined(CONFIG_TARGET_T1042RDB) || \ defined(CONFIG_TARGET_T1042D4RDB) || \ - defined(CONFIG_TARGET_T1042RDB_PI) || \ defined(CONFIG_ARCH_T1024) -#undef CONFIG_SYS_INIT_L3_ADDR -#define CONFIG_SYS_INIT_L3_ADDR 0xbff00000 +#undef CFG_SYS_INIT_L3_ADDR +#define CFG_SYS_INIT_L3_ADDR 0xbff00000 #endif #if defined(CONFIG_RAMBOOT_PBL) -#undef CONFIG_SYS_INIT_L3_ADDR -#ifdef CONFIG_SYS_INIT_L3_VADDR -#define CONFIG_SYS_INIT_L3_ADDR \ - (CONFIG_SYS_INIT_L3_VADDR & ~0xFFF00000) | \ +#undef CFG_SYS_INIT_L3_ADDR +#ifdef CFG_SYS_INIT_L3_VADDR +#define CFG_SYS_INIT_L3_ADDR \ + (CFG_SYS_INIT_L3_VADDR & ~0xFFF00000) | \ 0xbff00000 #else -#define CONFIG_SYS_INIT_L3_ADDR 0xbff00000 +#define CFG_SYS_INIT_L3_ADDR 0xbff00000 #endif #endif - -#if defined(CONFIG_ARCH_P3041) || \ - defined(CONFIG_ARCH_P4080) || \ - defined(CONFIG_ARCH_P5040) || \ - defined(CONFIG_ARCH_P2041) - #define CONFIG_FSL_TRUST_ARCH_v1 -#endif - -#if defined(CONFIG_FSL_CORENET) && !defined(CONFIG_SYS_RAMBOOT) -/* The key used for verification of next level images - * is picked up from an Extension Table which has - * been verified by the ISBC (Internal Secure boot Code) - * in boot ROM of the SoC. - * The feature is only applicable in case of NOR boot and is - * not applicable in case of RAMBOOT (NAND, SD, SPI). - */ -#define CONFIG_FSL_ISBC_KEY_EXT -#endif #endif /* #ifdef CONFIG_NXP_ESBC */ #ifdef CONFIG_CHAIN_OF_TRUST diff --git a/arch/powerpc/include/asm/immap_83xx.h b/arch/powerpc/include/asm/immap_83xx.h index 8e18202670..24bd438c14 100644 --- a/arch/powerpc/include/asm/immap_83xx.h +++ b/arch/powerpc/include/asm/immap_83xx.h @@ -871,11 +871,6 @@ struct ccsr_gpio { #define CFG_SYS_MPC83xx_ESDHC_ADDR \ (CONFIG_SYS_IMMR + CFG_SYS_MPC83xx_ESDHC_OFFSET) -#define CONFIG_SYS_LBC_ADDR (&((immap_t *)CONFIG_SYS_IMMR)->im_lbc) +#define CFG_SYS_LBC_ADDR (&((immap_t *)CONFIG_SYS_IMMR)->im_lbc) -#define CONFIG_SYS_TSEC1_OFFSET 0x24000 -#define CONFIG_SYS_MDIO1_OFFSET 0x24000 - -#define TSEC_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET) -#define MDIO_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MDIO1_OFFSET) #endif /* __IMMAP_83xx__ */ diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index c9ced5474c..7293720fb3 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -2445,10 +2445,10 @@ struct ccsr_pman { #ifdef CONFIG_SYS_FSL_SFP_VER_3_0 /* In SFPv3, OSPR register is now at offset 0x200. * * So directly mapping sfp register map to this address */ -#define CONFIG_SYS_OSPR_OFFSET 0x200 -#define CONFIG_SYS_SFP_OFFSET (0xE8000 + CONFIG_SYS_OSPR_OFFSET) +#define CFG_SYS_OSPR_OFFSET 0x200 +#define CFG_SYS_SFP_OFFSET (0xE8000 + CFG_SYS_OSPR_OFFSET) #else -#define CONFIG_SYS_SFP_OFFSET 0xE8000 +#define CFG_SYS_SFP_OFFSET 0xE8000 #endif #define CFG_SYS_FSL_CORENET_SERDES_OFFSET 0xEA000 #define CFG_SYS_FSL_CORENET_SERDES2_OFFSET 0xEB000 @@ -2489,7 +2489,7 @@ struct ccsr_pman { #define CFG_SYS_MPC85xx_SATA2_OFFSET 0x221000 #define CFG_SYS_FSL_SEC_OFFSET 0x300000 #define CFG_SYS_FSL_JR0_OFFSET 0x301000 -#define CONFIG_SYS_SEC_MON_OFFSET 0x314000 +#define CFG_SYS_SEC_MON_OFFSET 0x314000 #define CFG_SYS_FSL_CORENET_PME_OFFSET 0x316000 #define CFG_SYS_FSL_QMAN_OFFSET 0x318000 #define CFG_SYS_FSL_BMAN_OFFSET 0x31a000 @@ -2541,14 +2541,7 @@ struct ccsr_pman { #define CFG_SYS_MPC85xx_USB2_OFFSET 0x23000 #define CFG_SYS_MPC85xx_USB1_PHY_OFFSET 0xE5000 #define CFG_SYS_MPC85xx_USB2_PHY_OFFSET 0xE5100 -#ifdef CONFIG_TSECV2 -#define CONFIG_SYS_TSEC1_OFFSET 0xB0000 -#elif defined(CONFIG_TSECV2_1) -#define CONFIG_SYS_TSEC1_OFFSET 0x10000 -#else -#define CONFIG_SYS_TSEC1_OFFSET 0x24000 -#endif -#define CONFIG_SYS_MDIO1_OFFSET 0x24000 +#define CFG_SYS_MDIO1_OFFSET 0x24000 #define CFG_SYS_MPC85xx_ESDHC_OFFSET 0x2e000 #if defined(CONFIG_ARCH_C29X) #define CFG_SYS_FSL_SEC_OFFSET 0x80000 @@ -2559,8 +2552,8 @@ struct ccsr_pman { #endif #define CFG_SYS_MPC85xx_SERDES2_OFFSET 0xE3100 #define CFG_SYS_MPC85xx_SERDES1_OFFSET 0xE3000 -#define CONFIG_SYS_SEC_MON_OFFSET 0xE6000 -#define CONFIG_SYS_SFP_OFFSET 0xE7000 +#define CFG_SYS_SEC_MON_OFFSET 0xE6000 +#define CFG_SYS_SFP_OFFSET 0xE7000 #define CFG_SYS_FSL_QMAN_OFFSET 0x88000 #define CFG_SYS_FSL_BMAN_OFFSET 0x8a000 #define CFG_SYS_FSL_FM1_OFFSET 0x100000 @@ -2574,9 +2567,9 @@ struct ccsr_pman { #define CFG_SYS_FSL_SRIO_OFFSET 0xC0000 #define CFG_SYS_FSL_CPC_ADDR \ - (CONFIG_SYS_CCSRBAR + CFG_SYS_FSL_CPC_OFFSET) + (CFG_SYS_CCSRBAR + CFG_SYS_FSL_CPC_OFFSET) #define CFG_SYS_FSL_SCFG_ADDR \ - (CONFIG_SYS_CCSRBAR + CFG_SYS_FSL_SCFG_OFFSET) + (CFG_SYS_CCSRBAR + CFG_SYS_FSL_SCFG_OFFSET) #define CFG_SYS_FSL_QMAN_ADDR \ (CONFIG_SYS_IMMR + CFG_SYS_FSL_QMAN_OFFSET) #define CFG_SYS_FSL_BMAN_ADDR \ @@ -2603,9 +2596,9 @@ struct ccsr_pman { (CONFIG_SYS_IMMR + CFG_SYS_MPC8xxx_DDR2_OFFSET) #define CFG_SYS_FSL_DDR3_ADDR \ (CONFIG_SYS_IMMR + CFG_SYS_MPC8xxx_DDR3_OFFSET) -#define CONFIG_SYS_LBC_ADDR \ +#define CFG_SYS_LBC_ADDR \ (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_LBC_OFFSET) -#define CONFIG_SYS_IFC_ADDR \ +#define CFG_SYS_IFC_ADDR \ (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_IFC_OFFSET) #define CFG_SYS_MPC85xx_ESPI_ADDR \ (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_ESPI_OFFSET) @@ -2659,30 +2652,21 @@ struct ccsr_pman { (CONFIG_SYS_IMMR + CFG_SYS_FSL_FM2_OFFSET) #define CFG_SYS_FSL_SRIO_ADDR \ (CONFIG_SYS_IMMR + CFG_SYS_FSL_SRIO_OFFSET) -#define CONFIG_SYS_PAMU_ADDR \ +#define CFG_SYS_PAMU_ADDR \ (CONFIG_SYS_IMMR + CFG_SYS_FSL_PAMU_OFFSET) -#define CONFIG_SYS_PCI1_ADDR \ - (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_PCI1_OFFSET) -#define CONFIG_SYS_PCI2_ADDR \ - (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_PCI2_OFFSET) -#define CONFIG_SYS_PCIE1_ADDR \ +#define CFG_SYS_PCIE1_ADDR \ (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_PCIE1_OFFSET) -#define CONFIG_SYS_PCIE2_ADDR \ +#define CFG_SYS_PCIE2_ADDR \ (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_PCIE2_OFFSET) -#define CONFIG_SYS_PCIE3_ADDR \ - (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_PCIE3_OFFSET) -#define CONFIG_SYS_PCIE4_ADDR \ - (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_PCIE4_OFFSET) -#define CONFIG_SYS_SFP_ADDR \ - (CONFIG_SYS_IMMR + CONFIG_SYS_SFP_OFFSET) +#define CFG_SYS_SFP_ADDR \ + (CONFIG_SYS_IMMR + CFG_SYS_SFP_OFFSET) -#define CONFIG_SYS_SEC_MON_ADDR \ - (CONFIG_SYS_IMMR + CONFIG_SYS_SEC_MON_OFFSET) +#define CFG_SYS_SEC_MON_ADDR \ + (CONFIG_SYS_IMMR + CFG_SYS_SEC_MON_OFFSET) -#define TSEC_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET) -#define MDIO_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MDIO1_OFFSET) +#define MDIO_BASE_ADDR (CONFIG_SYS_IMMR + CFG_SYS_MDIO1_OFFSET) #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 struct ccsr_cluster_l2 { @@ -2743,7 +2727,7 @@ struct ccsr_cluster_l2 { (CONFIG_SYS_IMMR + CFG_SYS_FSL_CLUSTER_1_L2_OFFSET) #endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */ -#define CONFIG_SYS_DCSR_DCFG_OFFSET 0X20000 +#define CFG_SYS_DCSR_DCFG_OFFSET 0X20000 struct dcsr_dcfg_regs { u8 res_0[0x520]; u32 ecccr1; diff --git a/arch/powerpc/lib/bootm.c b/arch/powerpc/lib/bootm.c index 8ae8d8a3e7..1df0822e9d 100644 --- a/arch/powerpc/lib/bootm.c +++ b/arch/powerpc/lib/bootm.c @@ -126,7 +126,7 @@ void arch_lmb_reserve(struct lmb *lmb) #ifdef DEBUG if (((u64)bootmap_base + bootm_size) > - (CONFIG_SYS_SDRAM_BASE + (u64)gd->ram_size)) + (CFG_SYS_SDRAM_BASE + (u64)gd->ram_size)) puts("WARNING: bootm_low + bootm_size exceed total memory\n"); if ((bootmap_base + bootm_size) > get_effective_memsize()) puts("WARNING: bootm_low + bootm_size exceed eff. memory\n"); diff --git a/arch/powerpc/lib/spl.c b/arch/powerpc/lib/spl.c index d4a6057527..b638ea7be6 100644 --- a/arch/powerpc/lib/spl.c +++ b/arch/powerpc/lib/spl.c @@ -23,7 +23,7 @@ void __noreturn jump_to_image_linux(struct spl_image_info *spl_image) image_entry_arg_t image_entry = (image_entry_arg_t)spl_image->entry_point; - image_entry(spl_image->arg, 0, 0, EPAPR_MAGIC, CONFIG_SYS_BOOTMAPSZ, + image_entry(spl_image->arg, 0, 0, EPAPR_MAGIC, CFG_SYS_BOOTMAPSZ, 0, 0); } #endif /* CONFIG_SPL_OS_BOOT */ diff --git a/arch/riscv/config.mk b/arch/riscv/config.mk index 1ebce5bd67..a8ed3faf28 100644 --- a/arch/riscv/config.mk +++ b/arch/riscv/config.mk @@ -23,8 +23,6 @@ KBUILD_LDFLAGS += -m $(64bit-emul) EFI_LDS := elf_riscv64_efi.lds endif -CONFIG_STANDALONE_LOAD_ADDR ?= 0x00000000 - PLATFORM_CPPFLAGS += -ffixed-gp -fpic PLATFORM_RELFLAGS += -fno-common -gdwarf-2 -ffunction-sections \ -fdata-sections diff --git a/arch/sandbox/Kconfig b/arch/sandbox/Kconfig index 96b3402b47..0ce77de2fc 100644 --- a/arch/sandbox/Kconfig +++ b/arch/sandbox/Kconfig @@ -47,6 +47,13 @@ config HOST_32BIT config HOST_64BIT def_bool $(cc-define,_LP64) +config HOST_HAS_SDL + def_bool $(success,sdl2-config --version) + +config SANDBOX_SDL + bool "Enable SDL2 support in sandbox" + default HOST_HAS_SDL + config SANDBOX_CRASH_RESET bool "Reset on crash" help diff --git a/arch/sandbox/config.mk b/arch/sandbox/config.mk index 3e2c7f9ebe..1284ef390b 100644 --- a/arch/sandbox/config.mk +++ b/arch/sandbox/config.mk @@ -8,9 +8,7 @@ SDL_CONFIG ?= sdl2-config # Define this to avoid linking with SDL, which requires SDL libraries # This can solve 'sdl-config: Command not found' errors -ifneq ($(NO_SDL),) -PLATFORM_CPPFLAGS += -DSANDBOX_NO_SDL -else +ifeq ($(CONFIG_SANDBOX_SDL),y) PLATFORM_LIBS += $(shell $(SDL_CONFIG) --libs) PLATFORM_CPPFLAGS += $(shell $(SDL_CONFIG) --cflags) endif diff --git a/arch/sandbox/cpu/start.c b/arch/sandbox/cpu/start.c index 622df41f54..234652872e 100644 --- a/arch/sandbox/cpu/start.c +++ b/arch/sandbox/cpu/start.c @@ -535,7 +535,7 @@ int sandbox_main(int argc, char *argv[]) } #if CONFIG_VAL(SYS_MALLOC_F_LEN) - gd->malloc_base = CONFIG_MALLOC_F_ADDR; + gd->malloc_base = CFG_MALLOC_F_ADDR; #endif #if CONFIG_IS_ENABLED(LOG) gd->default_log_level = state->default_log_level; diff --git a/arch/sandbox/cpu/state.c b/arch/sandbox/cpu/state.c index a681e472ab..dd7978cfce 100644 --- a/arch/sandbox/cpu/state.c +++ b/arch/sandbox/cpu/state.c @@ -448,7 +448,7 @@ int state_init(void) { state = &main_state; - state->ram_size = CONFIG_SYS_SDRAM_SIZE; + state->ram_size = CFG_SYS_SDRAM_SIZE; state->ram_buf = os_malloc(state->ram_size); if (!state->ram_buf) { printf("Out of memory\n"); diff --git a/arch/sandbox/dts/sandbox.dts b/arch/sandbox/dts/sandbox.dts index 2051207f0b..88b57bfb7e 100644 --- a/arch/sandbox/dts/sandbox.dts +++ b/arch/sandbox/dts/sandbox.dts @@ -25,7 +25,7 @@ }; memory { - reg = <0 CONFIG_SYS_SDRAM_SIZE>; + reg = <0 CFG_SYS_SDRAM_SIZE>; }; reserved-memory { diff --git a/arch/sandbox/dts/sandbox64.dts b/arch/sandbox/dts/sandbox64.dts index 3eb0457089..a9cd7908f8 100644 --- a/arch/sandbox/dts/sandbox64.dts +++ b/arch/sandbox/dts/sandbox64.dts @@ -21,7 +21,7 @@ }; memory { - reg = /bits/ 64 <0 CONFIG_SYS_SDRAM_SIZE>; + reg = /bits/ 64 <0 CFG_SYS_SDRAM_SIZE>; }; reserved-memory { diff --git a/arch/sandbox/include/asm/config.h b/arch/sandbox/include/asm/config.h index 50215b35d7..87b9d23b37 100644 --- a/arch/sandbox/include/asm/config.h +++ b/arch/sandbox/include/asm/config.h @@ -6,14 +6,4 @@ #ifndef _ASM_CONFIG_H_ #define _ASM_CONFIG_H_ -#define CONFIG_SANDBOX_ARCH - -/* Used by drivers/spi/sandbox_spi.c and arch/sandbox/include/asm/state.h */ -#ifndef CONFIG_SANDBOX_SPI_MAX_BUS -#define CONFIG_SANDBOX_SPI_MAX_BUS 1 -#endif -#ifndef CONFIG_SANDBOX_SPI_MAX_CS -#define CONFIG_SANDBOX_SPI_MAX_CS 10 -#endif - #endif diff --git a/arch/sh/config.mk b/arch/sh/config.mk index 78bb2660e1..a408264d4b 100644 --- a/arch/sh/config.mk +++ b/arch/sh/config.mk @@ -3,7 +3,6 @@ # (C) Copyright 2000-2002 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. -CONFIG_STANDALONE_LOAD_ADDR ?= 0x8C000000 ifeq ($(CPU),sh2) LDFLAGS_STANDALONE += -EB endif diff --git a/arch/sh/cpu/u-boot.lds b/arch/sh/cpu/u-boot.lds index 85ee547b4a..c31deecec6 100644 --- a/arch/sh/cpu/u-boot.lds +++ b/arch/sh/cpu/u-boot.lds @@ -18,7 +18,7 @@ OUTPUT_ARCH(sh) MEMORY { - ram : ORIGIN = CONFIG_SYS_SDRAM_BASE, LENGTH = CONFIG_SYS_SDRAM_SIZE + ram : ORIGIN = CFG_SYS_SDRAM_BASE, LENGTH = CFG_SYS_SDRAM_SIZE } ENTRY(_start) @@ -35,7 +35,7 @@ SECTIONS .text : { KEEP(*/start.o (.text)) - KEEP(CONFIG_BOARDDIR/lowlevel_init.o (.text .spiboot1.text)) + KEEP(CFG_BOARDDIR/lowlevel_init.o (.text .spiboot1.text)) KEEP(*(.spiboot2.text)) . = ALIGN(8192); #ifdef CONFIG_ENV_IS_IN_FLASH diff --git a/arch/sh/include/asm/config.h b/arch/sh/include/asm/config.h index 09a15da485..03c196fec3 100644 --- a/arch/sh/include/asm/config.h +++ b/arch/sh/include/asm/config.h @@ -9,8 +9,7 @@ #include <asm/processor.h> /* Timer */ -#define CONFIG_SYS_TIMER_COUNTS_DOWN -#define CONFIG_SYS_TIMER_COUNTER (TMU_BASE + 0xc) /* TCNT0 */ -#define CONFIG_SYS_TIMER_RATE (get_board_sys_clk() / 4) +#define CFG_SYS_TIMER_COUNTER (TMU_BASE + 0xc) /* TCNT0 */ +#define CFG_SYS_TIMER_RATE (get_board_sys_clk() / 4) #endif diff --git a/arch/sh/lib/board.c b/arch/sh/lib/board.c index 3fa093a02e..b31fa6d703 100644 --- a/arch/sh/lib/board.c +++ b/arch/sh/lib/board.c @@ -11,8 +11,8 @@ DECLARE_GLOBAL_DATA_PTR; int dram_init(void) { - gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, - CONFIG_SYS_SDRAM_SIZE); + gd->ram_size = get_ram_size((long *)CFG_SYS_SDRAM_BASE, + CFG_SYS_SDRAM_SIZE); return 0; } diff --git a/arch/sh/lib/bootm.c b/arch/sh/lib/bootm.c index a5fad6c46c..b205e5e3db 100644 --- a/arch/sh/lib/bootm.c +++ b/arch/sh/lib/bootm.c @@ -88,7 +88,7 @@ int do_bootm_linux(int flag, int argc, char *const argv[], set_sh_linux_param((unsigned long)param + ORIG_ROOT_DEV, 0x0200); set_sh_linux_param((unsigned long)param + LOADER_TYPE, 0x0001); set_sh_linux_param((unsigned long)param + INITRD_START, - GET_INITRD_START(images->rd_start, CONFIG_SYS_SDRAM_BASE)); + GET_INITRD_START(images->rd_start, CFG_SYS_SDRAM_BASE)); set_sh_linux_param((unsigned long)param + INITRD_SIZE, images->rd_end - images->rd_start); } diff --git a/arch/x86/config.mk b/arch/x86/config.mk index 889497b6bd..a4a694ddf3 100644 --- a/arch/x86/config.mk +++ b/arch/x86/config.mk @@ -3,8 +3,6 @@ # (C) Copyright 2000-2002 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. -CONFIG_STANDALONE_LOAD_ADDR ?= 0x40000 - PLATFORM_CPPFLAGS += -fomit-frame-pointer PF_CPPFLAGS_X86 := $(call cc-option, -fno-toplevel-reorder, \ $(call cc-option, -fno-unit-at-a-time)) diff --git a/arch/x86/cpu/broadwell/refcode.c b/arch/x86/cpu/broadwell/refcode.c index 94c2e05346..df2df7972e 100644 --- a/arch/x86/cpu/broadwell/refcode.c +++ b/arch/x86/cpu/broadwell/refcode.c @@ -78,7 +78,7 @@ static int cpu_run_reference_code(void) int ret, dummy; int size; - hdr = (struct rmodule_header *)CONFIG_X86_REFCODE_ADDR; + hdr = (struct rmodule_header *)CFG_X86_REFCODE_ADDR; debug("Extracting code from rmodule at %p\n", hdr); if (hdr->magic != RMODULE_MAGIC) { debug("Invalid rmodule magic\n"); @@ -99,7 +99,7 @@ static int cpu_run_reference_code(void) pei_data->saved_data = (void *)&dummy; src = (char *)hdr + hdr->payload_begin_offset; - dest = (char *)CONFIG_X86_REFCODE_RUN_ADDR; + dest = (char *)CFG_X86_REFCODE_RUN_ADDR; size = hdr->payload_end_offset - hdr->payload_begin_offset; debug("Copying refcode from %p to %p, size %x\n", src, dest, size); @@ -112,7 +112,7 @@ static int cpu_run_reference_code(void) func = (asmlinkage int (*)(void *))dest; debug("Running reference code at %p\n", func); #ifdef DEBUG - print_buffer(CONFIG_X86_REFCODE_RUN_ADDR, (void *)func, 1, 0x40, 0); + print_buffer(CFG_X86_REFCODE_RUN_ADDR, (void *)func, 1, 0x40, 0); #endif ret = func(pei_data); if (ret != 0) { diff --git a/arch/x86/cpu/intel_common/mrc.c b/arch/x86/cpu/intel_common/mrc.c index a4918fbad6..69405d740b 100644 --- a/arch/x86/cpu/intel_common/mrc.c +++ b/arch/x86/cpu/intel_common/mrc.c @@ -200,7 +200,7 @@ static int sdram_initialise(struct udevice *dev, struct udevice *me_dev, debug("PEI data at %p:\n", pei_data); - data = (char *)CONFIG_X86_MRC_ADDR; + data = (char *)CFG_X86_MRC_ADDR; if (data) { int rv; ulong start; diff --git a/arch/x86/dts/u-boot.dtsi b/arch/x86/dts/u-boot.dtsi index 24e692f988..e0de331809 100644 --- a/arch/x86/dts/u-boot.dtsi +++ b/arch/x86/dts/u-boot.dtsi @@ -86,7 +86,7 @@ #endif #ifdef CONFIG_HAVE_MRC intel-mrc { - offset = <CONFIG_X86_MRC_ADDR>; + offset = <CFG_X86_MRC_ADDR>; }; #endif #ifdef CONFIG_FSP_VERSION1 @@ -149,7 +149,7 @@ #endif #ifdef CONFIG_HAVE_REFCODE intel-refcode { - offset = <CONFIG_X86_REFCODE_ADDR>; + offset = <CFG_X86_REFCODE_ADDR>; }; #endif #ifdef CONFIG_TPL diff --git a/arch/x86/lib/fsp/fsp_common.c b/arch/x86/lib/fsp/fsp_common.c index 82f7d3ab5f..8f2977a807 100644 --- a/arch/x86/lib/fsp/fsp_common.c +++ b/arch/x86/lib/fsp/fsp_common.c @@ -61,6 +61,7 @@ void board_final_init(void) debug("OK\n"); } +#if CONFIG_IS_ENABLED(DM_RTC) int fsp_save_s3_stack(void) { struct udevice *dev; @@ -84,3 +85,4 @@ int fsp_save_s3_stack(void) return 0; } +#endif diff --git a/arch/x86/lib/physmem.c b/arch/x86/lib/physmem.c index c11101b44e..1eb97ac5bb 100644 --- a/arch/x86/lib/physmem.c +++ b/arch/x86/lib/physmem.c @@ -144,7 +144,7 @@ static void x86_phys_memset_page(phys_addr_t map_addr, uintptr_t offset, int c, /* Make sure the window is below U-Boot. */ assert(window + LARGE_PAGE_SIZE < - gd->relocaddr - CONFIG_SYS_MALLOC_LEN - CONFIG_SYS_STACK_SIZE); + gd->relocaddr - CONFIG_SYS_MALLOC_LEN - CFG_SYS_STACK_SIZE); /* Map the page into the window and then memset the appropriate part. */ x86_phys_map_page(window, map_addr, 1); memset((void *)(window + offset), c, size); diff --git a/arch/xtensa/cpu/cpu.c b/arch/xtensa/cpu/cpu.c index a09e103fc1..98d9753b7e 100644 --- a/arch/xtensa/cpu/cpu.c +++ b/arch/xtensa/cpu/cpu.c @@ -45,7 +45,7 @@ int print_cpuinfo(void) int arch_cpu_init(void) { - gd->ram_size = CONFIG_SYS_SDRAM_SIZE; + gd->ram_size = CFG_SYS_SDRAM_SIZE; return 0; } diff --git a/arch/xtensa/include/asm/addrspace.h b/arch/xtensa/include/asm/addrspace.h index 3b27f9308a..920b5fd26b 100644 --- a/arch/xtensa/include/asm/addrspace.h +++ b/arch/xtensa/include/asm/addrspace.h @@ -22,8 +22,8 @@ * The actual location of memory and IO is the board property. */ -#define IOADDR(x) (CONFIG_SYS_IO_BASE + (x)) -#define MEMADDR(x) (CONFIG_SYS_MEMORY_BASE + (x)) +#define IOADDR(x) (CFG_SYS_IO_BASE + (x)) +#define MEMADDR(x) (CFG_SYS_MEMORY_BASE + (x)) #define PHYSADDR(x) ((x) - XCHAL_VECBASE_RESET_VADDR + \ XCHAL_VECBASE_RESET_PADDR) diff --git a/arch/xtensa/include/asm/config.h b/arch/xtensa/include/asm/config.h index a1096ab196..268c5688b3 100644 --- a/arch/xtensa/include/asm/config.h +++ b/arch/xtensa/include/asm/config.h @@ -14,8 +14,7 @@ * restricting used physical memory to the first 128MB. */ #if XCHAL_HAVE_PTP_MMU -#define CONFIG_VERY_BIG_RAM -#define CONFIG_MAX_MEM_MAPPED (128 << 20) +#define CFG_MAX_MEM_MAPPED (128 << 20) #endif #endif |