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| author | Shengyu Qu <wiagn233@outlook.com> | 2023-08-09 16:11:31 +0300 |
|---|---|---|
| committer | Leo Yu-Chi Liang <ycliang@andestech.com> | 2023-08-10 05:58:12 +0300 |
| commit | d365f6646aa4ecaabc58c07ecc432a3177f13138 (patch) | |
| tree | f483d31ac436a9f89fab68c9b67179995d88c0ea /arch | |
| parent | 7d79bed00c9e02187a09e74e90c5bd5a927a6a61 (diff) | |
| download | u-boot-d365f6646aa4ecaabc58c07ecc432a3177f13138.tar.xz | |
riscv: Kconfig: Add SPL_ZERO_MEM_BEFORE_USE
Add a Kconfig item to allow SPL to clear stack/GD/malloc area before
using them.
Signed-off-by: Bo Gan <ganboing@gmail.com>
Signed-off-by: Shengyu Qu <wiagn233@outlook.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/riscv/Kconfig | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 867cbcbe74..6771d8d919 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -64,6 +64,14 @@ config SPL_SYS_DCACHE_OFF help Do not enable data cache in SPL. +config SPL_ZERO_MEM_BEFORE_USE + bool "Zero memory before use" + depends on SPL + default n + help + Zero stack/GD/malloc area in SPL before using them, this is needed for + Sifive core devices that uses L2 cache to store SPL. + # board-specific options below source "board/AndesTech/ae350/Kconfig" source "board/emulation/qemu-riscv/Kconfig" |