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| author | Pali Rohár <pali@kernel.org> | 2021-09-24 23:59:22 +0300 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2021-10-08 09:33:52 +0300 |
| commit | de7293043329c6d230b7f81861867c6a645f4dc7 (patch) | |
| tree | 9201bb21ad1fafa51521b792c9bb3089a9dec6ec /arch | |
| parent | 28c935b5ee3ab8d437f28df739c0ea1027db6b5c (diff) | |
| download | u-boot-de7293043329c6d230b7f81861867c6a645f4dc7.tar.xz | |
arm: mvebu: a38x: serdes: Update comment about PCIE*_ENABLE_* defines
These are part of SOC_CONTROL_REG1 register, not PEX_CAPABILITIES_REG.
Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/mach-mvebu/serdes/a38x/ctrl_pex.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/mach-mvebu/serdes/a38x/ctrl_pex.h b/arch/arm/mach-mvebu/serdes/a38x/ctrl_pex.h index 55a4c267c4..64193d5288 100644 --- a/arch/arm/mach-mvebu/serdes/a38x/ctrl_pex.h +++ b/arch/arm/mach-mvebu/serdes/a38x/ctrl_pex.h @@ -12,7 +12,7 @@ /* Direct access to PEX0 Root Port's PCIe Capability structure */ #define PEX0_RP_PCIE_CFG_OFFSET (0x00080000 + 0x60) -/* PEX_CAPABILITIES_REG fields */ +/* SOC_CONTROL_REG1 fields */ #define PCIE0_ENABLE_OFFS 0 #define PCIE0_ENABLE_MASK (0x1 << PCIE0_ENABLE_OFFS) #define PCIE1_ENABLE_OFFS 1 |