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authorJonas Karlman <jonas@kwiboo.se>2023-07-28 14:38:38 +0300
committerKever Yang <kever.yang@rock-chips.com>2023-07-31 12:34:43 +0300
commitee75f168680669180b1e2eb14de71b8c6e3f7973 (patch)
treea7b8959352fdf58aad58f44cb151a58bacf99025 /arch
parent263f81d3a509e09289c3eba2f7cd0b49eb9f5145 (diff)
downloadu-boot-ee75f168680669180b1e2eb14de71b8c6e3f7973.tar.xz
rockchip: rk3399-roc-pc: Fix SPL max size and SPI flash payload offset
TPL max size is limited to 184 KB, SPL is loaded to 0x0 and TF-A is loaded to 0x40000, this limit SPL max size to 256 KB. With BootRom only reading first 2 KB per 4 KB page of SPI flash, 880 KB may be needed for TPL+SPL in a worst-case scenario. (184 KB + 256 KB) x 2 = 880 KB Use 0xE0000 (896 KB) as the payload offset in SPI flash, this allows for a payload of 3168 KB before env offset start to overlap. Also add CONFIG_ROCKCHIP_SPI_IMAGE=y to build a bootable SPI flash image, u-boot-rockchip-spi.bin. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Quentin Schulz <foss+u-boot@0leil.net> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/dts/rk3399-roc-pc-u-boot.dtsi4
1 files changed, 0 insertions, 4 deletions
diff --git a/arch/arm/dts/rk3399-roc-pc-u-boot.dtsi b/arch/arm/dts/rk3399-roc-pc-u-boot.dtsi
index f85e7b62d9..c8f4418a73 100644
--- a/arch/arm/dts/rk3399-roc-pc-u-boot.dtsi
+++ b/arch/arm/dts/rk3399-roc-pc-u-boot.dtsi
@@ -11,10 +11,6 @@
u-boot,spl-boot-order = "same-as-spl", &spi_flash, &sdhci, &sdmmc;
};
- config {
- u-boot,spl-payload-offset = <0x60000>; /* @ 384KB */
- };
-
vcc_hub_en: vcc_hub_en-regulator {
compatible = "regulator-fixed";
enable-active-high;