diff options
| author | yanhong.wang <yanhong.wang@starfivetech.com> | 2022-05-15 09:55:55 +0300 |
|---|---|---|
| committer | Yanhong Wang <yanhong.wang@linux.starfivetech.com> | 2022-10-18 11:24:35 +0300 |
| commit | 0eddcac0de54ba6d7b73f4cef8fffc9ce86582e0 (patch) | |
| tree | 193e98cd80a7969cd780dc61625c450593857f83 /arch | |
| parent | b8ceeb8238c4db755c2a3e5fe178568bd2d4c568 (diff) | |
| download | u-boot-0eddcac0de54ba6d7b73f4cef8fffc9ce86582e0.tar.xz | |
board:starfive: add clk init
Add clk init for ddr on JH7110 board
Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
Diffstat (limited to 'arch')
| -rwxr-xr-x | arch/riscv/include/asm/arch-jh7110/jh7110-regs.h | 32 |
1 files changed, 27 insertions, 5 deletions
diff --git a/arch/riscv/include/asm/arch-jh7110/jh7110-regs.h b/arch/riscv/include/asm/arch-jh7110/jh7110-regs.h index 89724813d8..4f7bcc5ee1 100755 --- a/arch/riscv/include/asm/arch-jh7110/jh7110-regs.h +++ b/arch/riscv/include/asm/arch-jh7110/jh7110-regs.h @@ -9,11 +9,13 @@ #define __STARFIVE_JH7110_REGS_H /*system control register*/ -#define STG_SYSCON_BASE 0x10240000 -#define SYS_SYSCON_BASE 0x13030000 -#define SYS_IOMUX_BASE 0x13040000 -#define AON_SYSCON_BASE 0x17010000 -#define SYS_CRG_BASE 0x13020000 +#define STG_SYSCON_BASE 0x10240000 +#define SYS_SYSCON_BASE 0x13030000 +#define SYS_IOMUX_BASE 0x13040000 +#define AON_SYSCON_BASE 0x17010000 +#define SYS_CRG_BASE 0x13020000 +#define AON_CRG_BASE 0x17000000 +#define STG_CRG_BASE 0x10230000 #define CLK_ENABLE_MASK 0x80000000U #define SYS_CRG_RESET_ASSERT3_SHIFT 0X304U #define SYS_CRG_RESET_STATUS3_SHIFT 0X314U @@ -57,5 +59,25 @@ #define TIMER_RSTN_TIMER2_SHIFT 24 #define TIMER_RSTN_TIMER3_SHIFT 25 +#define CLK_CPU_ROOT_OFFSET 0x0 +#define CLK_CPU_ROOT_SW_SHIFT 24 +#define CLK_CPU_ROOT_SW_MASK 0x1000000U + +#define CLK_BUS_ROOT_OFFSET 0x14 +#define CLK_BUS_ROOT_SW_SHIFT 24 +#define CLK_BUS_ROOT_SW_MASK 0x1000000U + +#define CLK_NOC_BUS_STG_AXI_OFFSET 0x180 +#define CLK_NOC_BUS_STG_AXI_EN_SHIFT 31 +#define CLK_NOC_BUS_STG_AXI_EN_MASK 0x80000000U + +#define CLK_AON_APB_FUNC_OFFSET 0x4 +#define CLK_AON_APB_FUNC_SW_SHIFT 24 +#define CLK_AON_APB_FUNC_SW_MASK 0x1000000U + +#define CLK_QSPI_REF_OFFSET 0x168 +#define CLK_QSPI_REF_SW_SHIFT 24 +#define CLK_QSPI_REF_SW_MASK 0x1000000U + #endif /* __STARFIVE_JH7110_REGS_H */ |