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authorSamin Guo <samin.guo@starfivetech.com>2023-06-16 05:05:59 +0300
committerSamin Guo <samin.guo@starfivetech.com>2023-06-25 04:33:32 +0300
commit496d25d55c6e90cabe38395f8faa5ff5d7d9473a (patch)
tree089ae91762561a8ebcfdcdc4788a68ffcedf3fd1 /arch
parenta9822ef7831528c3673dd63168684e1011851c8f (diff)
downloadu-boot-496d25d55c6e90cabe38395f8faa5ff5d7d9473a.tar.xz
dram: jh7110: Add resize DDR info from EEPROM.
sync from vf2 and add resize DDR info from EEPROM Signed-off-by: Samin Guo <samin.guo@starfivetech.com>
Diffstat (limited to 'arch')
-rw-r--r--arch/riscv/cpu/jh7110/dram.c49
1 files changed, 47 insertions, 2 deletions
diff --git a/arch/riscv/cpu/jh7110/dram.c b/arch/riscv/cpu/jh7110/dram.c
index 1dc77efeca..ad8baeba93 100644
--- a/arch/riscv/cpu/jh7110/dram.c
+++ b/arch/riscv/cpu/jh7110/dram.c
@@ -4,20 +4,65 @@
*/
#include <common.h>
+#include <asm/arch/eeprom.h>
#include <fdtdec.h>
#include <init.h>
#include <linux/sizes.h>
DECLARE_GLOBAL_DATA_PTR;
+static bool check_eeprom_dram_info(phys_size_t size)
+{
+ switch (size) {
+ case 0x80000000:
+ case 0x100000000:
+ case 0x200000000:
+ case 0x400000000:
+ return true;
+ default:
+ return false;
+ }
+}
+
int dram_init(void)
{
- return fdtdec_setup_mem_size_base();
+ int ret;
+ u8 data;
+ u32 len;
+ u32 offset;
+ phys_size_t size;
+
+ data = 0;
+ len = 1;
+ offset = 91; /*offset of memory size stored in eeprom*/
+ ret = fdtdec_setup_mem_size_base();
+ if (ret)
+ goto err;
+
+ /*read memory size info*/
+ ret = get_data_from_eeprom(offset, len, &data);
+ if (ret == len) {
+ size = ((phys_size_t)hextoul(&data, NULL)) << 30;
+ if (check_eeprom_dram_info(size))
+ gd->ram_size = size;
+ }
+
+ ret = 0;
+err:
+ return ret;
}
int dram_init_banksize(void)
{
- return fdtdec_setup_memory_banksize();
+ int ret;
+
+ ret = fdtdec_setup_memory_banksize();
+ if (ret)
+ return ret;
+
+ gd->bd->bi_dram[0].size = gd->ram_size;
+
+ return 0;
}
ulong board_get_usable_ram_top(ulong total_size)