Merge branch '2021-07-06-platform-updates'

- mpc8379erdb DM_USB, DM_PCI and DM_ETH support.
- Drop PCI support from the integrator family of boards
- Add synquacer support
- Assorted lpc32xx updates and improvements
- snapdragon (and related) fixes, Broadcom iproc update

19 files changed, 1793 insertions, 31 deletions

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 0448787b8b..03529d7b46 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -90,6 +90,9 @@ config HAS_VBAR
 config HAS_THUMB2
 	bool
 
+config GPIO_EXTRA_HEADER
+	bool
+
 # Used for compatibility with asm files copied from the kernel
 config ARM_ASM_UNIFIED
 	bool
@@ -518,25 +521,30 @@ choice
 
 config ARCH_AT91
 	bool "Atmel AT91"
+	select GPIO_EXTRA_HEADER
 	select SPL_BOARD_INIT if SPL && !TARGET_SMARTWEB
 	select SPL_SEPARATE_BSS if SPL
 
 config TARGET_EDB93XX
 	bool "Support edb93xx"
 	select CPU_ARM920T
+	select GPIO_EXTRA_HEADER
 	select PL010_SERIAL
 
 config TARGET_ASPENITE
 	bool "Support aspenite"
 	select CPU_ARM926EJS
+	select GPIO_EXTRA_HEADER
 
 config TARGET_GPLUGD
 	bool "Support gplugd"
 	select CPU_ARM926EJS
+	select GPIO_EXTRA_HEADER
 
 config ARCH_DAVINCI
 	bool "TI DaVinci"
 	select CPU_ARM926EJS
+	select GPIO_EXTRA_HEADER
 	select SPL_DM_SPI if SPL
 	imply CMD_SAVES
 	help
@@ -547,6 +555,7 @@ config ARCH_KIRKWOOD
 	select ARCH_MISC_INIT
 	select BOARD_EARLY_INIT_F
 	select CPU_ARM926EJS
+	select GPIO_EXTRA_HEADER
 
 config ARCH_MVEBU
 	bool "Marvell MVEBU family (Armada XP/375/38x/3700/7K/8K)"
@@ -555,6 +564,7 @@ config ARCH_MVEBU
 	select DM_SERIAL
 	select DM_SPI
 	select DM_SPI_FLASH
+	select GPIO_EXTRA_HEADER
 	select SPL_DM_SPI if SPL
 	select SPL_DM_SPI_FLASH if SPL
 	select OF_CONTROL
@@ -565,11 +575,13 @@ config ARCH_MVEBU
 config ARCH_ORION5X
 	bool "Marvell Orion"
 	select CPU_ARM926EJS
+	select GPIO_EXTRA_HEADER
 
 config TARGET_SPEAR300
 	bool "Support spear300"
 	select BOARD_EARLY_INIT_F
 	select CPU_ARM926EJS
+	select GPIO_EXTRA_HEADER
 	select PL011_SERIAL
 	imply CMD_SAVES
 
@@ -577,6 +589,7 @@ config TARGET_SPEAR310
 	bool "Support spear310"
 	select BOARD_EARLY_INIT_F
 	select CPU_ARM926EJS
+	select GPIO_EXTRA_HEADER
 	select PL011_SERIAL
 	imply CMD_SAVES
 
@@ -584,6 +597,7 @@ config TARGET_SPEAR320
 	bool "Support spear320"
 	select BOARD_EARLY_INIT_F
 	select CPU_ARM926EJS
+	select GPIO_EXTRA_HEADER
 	select PL011_SERIAL
 	imply CMD_SAVES
 
@@ -591,6 +605,7 @@ config TARGET_SPEAR600
 	bool "Support spear600"
 	select BOARD_EARLY_INIT_F
 	select CPU_ARM926EJS
+	select GPIO_EXTRA_HEADER
 	select PL011_SERIAL
 	imply CMD_SAVES
 
@@ -601,6 +616,7 @@ config TARGET_STV0991
 	select DM_SERIAL
 	select DM_SPI
 	select DM_SPI_FLASH
+	select GPIO_EXTRA_HEADER
 	select PL01X_SERIAL
 	select SPI
 	select SPI_FLASH
@@ -610,18 +626,21 @@ config TARGET_X600
 	bool "Support x600"
 	select BOARD_LATE_INIT
 	select CPU_ARM926EJS
+	select GPIO_EXTRA_HEADER
 	select PL011_SERIAL
 	select SUPPORT_SPL
 
 config TARGET_FLEA3
 	bool "Support flea3"
 	select CPU_ARM1136
+	select GPIO_EXTRA_HEADER
 
 config ARCH_BCM283X
 	bool "Broadcom BCM283X family"
 	select DM
 	select DM_GPIO
 	select DM_SERIAL
+	select GPIO_EXTRA_HEADER
 	select OF_CONTROL
 	select PL01X_SERIAL
 	select SERIAL_SEARCH_ALL
@@ -650,6 +669,7 @@ config ARCH_BCMSTB
 	bool "Broadcom BCM7XXX family"
 	select CPU_V7A
 	select DM
+	select GPIO_EXTRA_HEADER
 	select OF_CONTROL
 	select OF_PRIOR_STAGE
 	imply CMD_DM
@@ -660,6 +680,7 @@ config ARCH_BCMSTB
 config TARGET_BCMCYGNUS
 	bool "Support bcmcygnus"
 	select CPU_V7A
+	select GPIO_EXTRA_HEADER
 	imply BCM_SF2_ETH
 	imply BCM_SF2_ETH_GMAC
 	imply CMD_HASH
@@ -671,6 +692,7 @@ config TARGET_BCMCYGNUS
 config TARGET_BCMNS2
 	bool "Support Broadcom Northstar2"
 	select ARM64
+	select GPIO_EXTRA_HEADER
 	help
 	  Support for Broadcom Northstar 2 SoCs.  NS2 is a quad-core 64-bit
 	  ARMv8 Cortex-A57 processors targeting a broad range of networking
@@ -695,6 +717,7 @@ config ARCH_EXYNOS
 	select DM_SPI
 	select DM_SPI_FLASH
 	select SPI
+	select GPIO_EXTRA_HEADER
 	imply SYS_THUMB_BUILD
 	imply CMD_DM
 	imply FAT_WRITE
@@ -706,6 +729,7 @@ config ARCH_S5PC1XX
 	select DM_GPIO
 	select DM_I2C
 	select DM_SERIAL
+	select GPIO_EXTRA_HEADER
 	imply CMD_DM
 
 config ARCH_HIGHBANK
@@ -726,6 +750,7 @@ config ARCH_INTEGRATOR
 	bool "ARM Ltd. Integrator family"
 	select DM
 	select DM_SERIAL
+	select GPIO_EXTRA_HEADER
 	select PL01X_SERIAL
 	imply CMD_DM
 
@@ -736,6 +761,7 @@ config ARCH_IPQ40XX
 	select DM_GPIO
 	select DM_SERIAL
 	select DM_RESET
+	select GPIO_EXTRA_HEADER
 	select MSM_SMEM
 	select PINCTRL
 	select CLK
@@ -747,6 +773,7 @@ config ARCH_KEYSTONE
 	bool "TI Keystone"
 	select CMD_POWEROFF
 	select CPU_V7A
+	select GPIO_EXTRA_HEADER
 	select SUPPORT_SPL
 	select SYS_ARCH_TIMER
 	select SYS_THUMB_BUILD
@@ -763,6 +790,7 @@ config ARCH_K3
 config ARCH_OMAP2PLUS
 	bool "TI OMAP2+"
 	select CPU_V7A
+	select GPIO_EXTRA_HEADER
 	select SPL_BOARD_INIT if SPL
 	select SPL_STACK_R if SPL
 	select SUPPORT_SPL
@@ -771,6 +799,7 @@ config ARCH_OMAP2PLUS
 
 config ARCH_MESON
 	bool "Amlogic Meson"
+	select GPIO_EXTRA_HEADER
 	imply DISTRO_DEFAULTS
 	imply DM_RNG
 	help
@@ -781,6 +810,7 @@ config ARCH_MESON
 config ARCH_MEDIATEK
 	bool "MediaTek SoCs"
 	select DM
+	select GPIO_EXTRA_HEADER
 	select OF_CONTROL
 	select SPL_DM if SPL
 	select SPL_LIBCOMMON_SUPPORT if SPL
@@ -797,6 +827,7 @@ config ARCH_LPC32XX
 	select DM
 	select DM_GPIO
 	select DM_SERIAL
+	select GPIO_EXTRA_HEADER
 	select SPL_DM if SPL
 	select SUPPORT_SPL
 	imply CMD_DM
@@ -805,12 +836,14 @@ config ARCH_IMX8
 	bool "NXP i.MX8 platform"
 	select ARM64
 	select DM
+	select GPIO_EXTRA_HEADER
 	select OF_CONTROL
 	select ENABLE_ARM_SOC_BOOT0_HOOK
 
 config ARCH_IMX8M
 	bool "NXP i.MX8M platform"
 	select ARM64
+	select GPIO_EXTRA_HEADER
 	select SYS_FSL_HAS_SEC if IMX_HAB
 	select SYS_FSL_SEC_COMPAT_4
 	select SYS_FSL_SEC_LE
@@ -823,33 +856,39 @@ config ARCH_IMXRT
 	select CPU_V7M
 	select DM
 	select DM_SERIAL
+	select GPIO_EXTRA_HEADER
 	select SUPPORT_SPL
 	imply CMD_DM
 
 config ARCH_MX23
 	bool "NXP i.MX23 family"
 	select CPU_ARM926EJS
+	select GPIO_EXTRA_HEADER
 	select PL011_SERIAL
 	select SUPPORT_SPL
 
 config ARCH_MX25
 	bool "NXP MX25"
 	select CPU_ARM926EJS
+	select GPIO_EXTRA_HEADER
 	imply MXC_GPIO
 
 config ARCH_MX28
 	bool "NXP i.MX28 family"
 	select CPU_ARM926EJS
+	select GPIO_EXTRA_HEADER
 	select PL011_SERIAL
 	select SUPPORT_SPL
 
 config ARCH_MX31
 	bool "NXP i.MX31 family"
 	select CPU_ARM1136
+	select GPIO_EXTRA_HEADER
 
 config ARCH_MX7ULP
 	bool "NXP MX7ULP"
 	select CPU_V7A
+	select GPIO_EXTRA_HEADER
 	select SYS_FSL_HAS_SEC if IMX_HAB
 	select SYS_FSL_SEC_COMPAT_4
 	select SYS_FSL_SEC_LE
@@ -861,6 +900,7 @@ config ARCH_MX7
 	bool "Freescale MX7"
 	select ARCH_MISC_INIT
 	select CPU_V7A
+	select GPIO_EXTRA_HEADER
 	select SYS_FSL_HAS_SEC if IMX_HAB
 	select SYS_FSL_SEC_COMPAT_4
 	select SYS_FSL_SEC_LE
@@ -871,6 +911,7 @@ config ARCH_MX7
 config ARCH_MX6
 	bool "Freescale MX6"
 	select CPU_V7A
+	select GPIO_EXTRA_HEADER
 	select SYS_FSL_HAS_SEC
 	select SYS_FSL_SEC_COMPAT_4
 	select SYS_FSL_SEC_LE
@@ -886,18 +927,21 @@ config ARCH_MX5
 	bool "Freescale MX5"
 	select BOARD_EARLY_INIT_F
 	select CPU_V7A
+	select GPIO_EXTRA_HEADER
 	imply MXC_GPIO
 
 config ARCH_NEXELL
 	bool "Nexell S5P4418/S5P6818 SoC"
 	select ENABLE_ARM_SOC_BOOT0_HOOK
 	select DM
+	select GPIO_EXTRA_HEADER
 
 config ARCH_OWL
 	bool "Actions Semi OWL SoCs"
 	select DM
 	select DM_ETH
 	select DM_SERIAL
+	select GPIO_EXTRA_HEADER
 	select OWL_SERIAL
 	select CLK
 	select CLK_OWL
@@ -920,6 +964,7 @@ config ARCH_RMOBILE
 	bool "Renesas ARM SoCs"
 	select DM
 	select DM_SERIAL
+	select GPIO_EXTRA_HEADER
 	imply BOARD_EARLY_INIT_F
 	imply CMD_DM
 	imply FAT_WRITE
@@ -932,6 +977,7 @@ config ARCH_SNAPDRAGON
 	select DM
 	select DM_GPIO
 	select DM_SERIAL
+	select GPIO_EXTRA_HEADER
 	select MSM_SMEM
 	select OF_CONTROL
 	select OF_SEPARATE
@@ -947,6 +993,7 @@ config ARCH_SOCFPGA
 	select CPU_V7A if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
 	select DM
 	select DM_SERIAL
+	select GPIO_EXTRA_HEADER
 	select ENABLE_ARM_SOC_BOOT0_HOOK if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
 	select OF_CONTROL
 	select SPL_DM_RESET if DM_RESET
@@ -998,6 +1045,7 @@ config ARCH_SUNXI
 	select DM_SCSI if SCSI
 	select DM_SERIAL
 	select DM_USB if DISTRO_DEFAULTS
+	select GPIO_EXTRA_HEADER
 	select OF_BOARD_SETUP
 	select OF_CONTROL
 	select OF_SEPARATE
@@ -1057,6 +1105,7 @@ config ARCH_VERSAL
 	select DM_ETH if NET
 	select DM_MMC if MMC
 	select DM_SERIAL
+	select GPIO_EXTRA_HEADER
 	select OF_CONTROL
 	imply BOARD_LATE_INIT
 	imply ENV_VARS_UBOOT_RUNTIME_CONFIG
@@ -1064,6 +1113,7 @@ config ARCH_VERSAL
 config ARCH_VF610
 	bool "Freescale Vybrid"
 	select CPU_V7A
+	select GPIO_EXTRA_HEADER
 	select SYS_FSL_ERRATUM_ESDHC111
 	imply CMD_MTDPARTS
 	imply MTD_RAW_NAND
@@ -1080,6 +1130,7 @@ config ARCH_ZYNQ
 	select DM_SPI
 	select DM_SPI_FLASH
 	select DM_USB if USB
+	select GPIO_EXTRA_HEADER
 	select OF_CONTROL
 	select SPI
 	select SPL_BOARD_INIT if SPL
@@ -1106,6 +1157,7 @@ config ARCH_ZYNQMP_R5
 	select DM_ETH if NET
 	select DM_MMC if MMC
 	select DM_SERIAL
+	select GPIO_EXTRA_HEADER
 	select OF_CONTROL
 	imply CMD_DM
 	imply DM_USB_GADGET
@@ -1123,6 +1175,7 @@ config ARCH_ZYNQMP
 	select DM_SPI_FLASH if DM_SPI
 	select DM_USB if USB
 	select FIRMWARE
+	select GPIO_EXTRA_HEADER
 	select OF_CONTROL
 	select SPL_BOARD_INIT if SPL
 	select SPL_CLK if SPL
@@ -1143,23 +1196,27 @@ config ARCH_ZYNQMP
 
 config ARCH_TEGRA
 	bool "NVIDIA Tegra"
+	select GPIO_EXTRA_HEADER
 	imply DISTRO_DEFAULTS
 	imply FAT_WRITE
 
 config TARGET_VEXPRESS64_AEMV8A
 	bool "Support vexpress_aemv8a"
 	select ARM64
+	select GPIO_EXTRA_HEADER
 	select PL01X_SERIAL
 
 config TARGET_VEXPRESS64_BASE_FVP
 	bool "Support Versatile Express ARMv8a FVP BASE model"
 	select ARM64
+	select GPIO_EXTRA_HEADER
 	select PL01X_SERIAL
 	select SEMIHOSTING
 
 config TARGET_VEXPRESS64_JUNO
 	bool "Support Versatile Express Juno Development Platform"
 	select ARM64
+	select GPIO_EXTRA_HEADER
 	select PL01X_SERIAL
 	select DM
 	select OF_CONTROL
@@ -1188,6 +1245,7 @@ config TARGET_LS2080A_EMU
 	select ARM64
 	select ARMV8_MULTIENTRY
 	select FSL_DDR_SYNC_REFRESH
+	select GPIO_EXTRA_HEADER
 	help
 	  Support for Freescale LS2080A_EMU platform.
 	  The LS2080A Development System (EMULATOR) is a pre-silicon
@@ -1201,6 +1259,7 @@ config TARGET_LS1088AQDS
 	select ARMV8_MULTIENTRY
 	select ARCH_SUPPORT_TFABOOT
 	select BOARD_LATE_INIT
+	select GPIO_EXTRA_HEADER
 	select SUPPORT_SPL
 	select FSL_DDR_INTERACTIVE if !SD_BOOT
 	help
@@ -1216,6 +1275,7 @@ config TARGET_LS2080AQDS
 	select ARMV8_MULTIENTRY
 	select ARCH_SUPPORT_TFABOOT
 	select BOARD_LATE_INIT
+	select GPIO_EXTRA_HEADER
 	select SUPPORT_SPL
 	imply SCSI
 	imply SCSI_AHCI
@@ -1237,6 +1297,7 @@ config TARGET_LS2080ARDB
 	select SUPPORT_SPL
 	select FSL_DDR_BIST
 	select FSL_DDR_INTERACTIVE if !SPL
+	select GPIO_EXTRA_HEADER
 	imply SCSI
 	imply SCSI_AHCI
 	help
@@ -1251,6 +1312,7 @@ config TARGET_LS2081ARDB
 	select ARM64
 	select ARMV8_MULTIENTRY
 	select BOARD_LATE_INIT
+	select GPIO_EXTRA_HEADER
 	select SUPPORT_SPL
 	help
 	  Support for Freescale LS2081ARDB platform.
@@ -1265,6 +1327,7 @@ config TARGET_LX2160ARDB
 	select ARMV8_MULTIENTRY
 	select ARCH_SUPPORT_TFABOOT
 	select BOARD_LATE_INIT
+	select GPIO_EXTRA_HEADER
 	help
 	  Support for NXP LX2160ARDB platform.
 	  The lx2160ardb (LX2160A Reference design board (RDB)
@@ -1278,6 +1341,7 @@ config TARGET_LX2160AQDS
 	select ARMV8_MULTIENTRY
 	select ARCH_SUPPORT_TFABOOT
 	select BOARD_LATE_INIT
+	select GPIO_EXTRA_HEADER
 	help
 	  Support for NXP LX2160AQDS platform.
 	  The lx2160aqds (LX2160A QorIQ Development System (QDS)
@@ -1292,6 +1356,7 @@ config TARGET_LX2162AQDS
 	select ARMV8_MULTIENTRY
 	select ARCH_SUPPORT_TFABOOT
 	select BOARD_LATE_INIT
+	select GPIO_EXTRA_HEADER
 	help
 	  Support for NXP LX2162AQDS platform.
 	  The lx2162aqds support is based on LX2160A Layerscape Architecture processor.
@@ -1302,6 +1367,7 @@ config TARGET_HIKEY
 	select DM
 	select DM_GPIO
 	select DM_SERIAL
+	select GPIO_EXTRA_HEADER
 	select OF_CONTROL
 	select PL01X_SERIAL
 	select SPECIFY_CONSOLE_INDEX
@@ -1315,6 +1381,7 @@ config TARGET_HIKEY960
 	select ARM64
 	select DM
 	select DM_SERIAL
+	select GPIO_EXTRA_HEADER
 	select OF_CONTROL
 	select PL01X_SERIAL
 	imply CMD_DM
@@ -1328,6 +1395,7 @@ config TARGET_POPLAR
 	select DM
 	select DM_SERIAL
 	select DM_USB
+	select GPIO_EXTRA_HEADER
 	select OF_CONTROL
 	select PL01X_SERIAL
 	imply CMD_DM
@@ -1343,6 +1411,7 @@ config TARGET_LS1012AQDS
 	select ARM64
 	select ARCH_SUPPORT_TFABOOT
 	select BOARD_LATE_INIT
+	select GPIO_EXTRA_HEADER
 	help
 	  Support for Freescale LS1012AQDS platform.
 	  The LS1012A Development System (QDS) is a high-performance
@@ -1355,6 +1424,7 @@ config TARGET_LS1012ARDB
 	select ARM64
 	select ARCH_SUPPORT_TFABOOT
 	select BOARD_LATE_INIT
+	select GPIO_EXTRA_HEADER
 	imply SCSI
 	imply SCSI_AHCI
 	help
@@ -1369,6 +1439,7 @@ config TARGET_LS1012A2G5RDB
 	select ARM64
 	select ARCH_SUPPORT_TFABOOT
 	select BOARD_LATE_INIT
+	select GPIO_EXTRA_HEADER
 	imply SCSI
 	help
 	  Support for Freescale LS1012A2G5RDB platform.
@@ -1382,6 +1453,7 @@ config TARGET_LS1012AFRWY
 	select ARM64
 	select ARCH_SUPPORT_TFABOOT
 	select BOARD_LATE_INIT
+	select GPIO_EXTRA_HEADER
 	imply SCSI
 	imply SCSI_AHCI
 	help
@@ -1395,6 +1467,7 @@ config TARGET_LS1012AFRDM
 	select ARCH_LS1012A
 	select ARM64
 	select ARCH_SUPPORT_TFABOOT
+	select GPIO_EXTRA_HEADER
 	help
 	  Support for Freescale LS1012AFRDM platform.
 	  The LS1012A Freedom  board (FRDM) is a high-performance
@@ -1408,6 +1481,7 @@ config TARGET_LS1028AQDS
 	select ARMV8_MULTIENTRY
 	select ARCH_SUPPORT_TFABOOT
 	select BOARD_LATE_INIT
+	select GPIO_EXTRA_HEADER
 	help
 	  Support for Freescale LS1028AQDS platform
 	  The LS1028A Development System (QDS) is a high-performance
@@ -1421,6 +1495,7 @@ config TARGET_LS1028ARDB
 	select ARMV8_MULTIENTRY
 	select ARCH_SUPPORT_TFABOOT
 	select BOARD_LATE_INIT
+	select GPIO_EXTRA_HEADER
 	help
 	  Support for Freescale LS1028ARDB platform
 	  The LS1028A Development System (RDB) is a high-performance
@@ -1436,6 +1511,7 @@ config TARGET_LS1088ARDB
 	select BOARD_LATE_INIT
 	select SUPPORT_SPL
 	select FSL_DDR_INTERACTIVE if !SD_BOOT
+	select GPIO_EXTRA_HEADER
 	help
 	  Support for NXP LS1088ARDB platform.
 	  The LS1088A Reference design board (RDB) is a high-performance
@@ -1456,6 +1532,7 @@ config TARGET_LS1021AQDS
 	select SYS_FSL_DDR
 	select FSL_DDR_INTERACTIVE
 	select DM_SPI_FLASH if FSL_DSPI || FSL_QSPI
+	select GPIO_EXTRA_HEADER
 	select SPI_FLASH_DATAFLASH if FSL_DSPI || FSL_QSPI
 	imply SCSI
 
@@ -1471,6 +1548,7 @@ config TARGET_LS1021ATWR
 	select LS1_DEEP_SLEEP
 	select SUPPORT_SPL
 	select DM_SPI_FLASH if FSL_DSPI || FSL_QSPI
+	select GPIO_EXTRA_HEADER
 	imply SCSI
 
 config TARGET_PG_WCOM_SELI8
@@ -1484,6 +1562,7 @@ config TARGET_PG_WCOM_SELI8
 	select CPU_V7_HAS_VIRT
 	select SYS_FSL_DDR
 	select FSL_DDR_INTERACTIVE
+	select GPIO_EXTRA_HEADER
 	select VENDOR_KM
 	imply SCSI
 	help
@@ -1520,6 +1599,7 @@ config TARGET_LS1021ATSN
 	select CPU_V7_HAS_VIRT
 	select LS1_DEEP_SLEEP
 	select SUPPORT_SPL
+	select GPIO_EXTRA_HEADER
 	imply SCSI
 
 config TARGET_LS1021AIOT
@@ -1532,6 +1612,7 @@ config TARGET_LS1021AIOT
 	select CPU_V7_HAS_VIRT
 	select SUPPORT_SPL
 	select DM_SPI_FLASH if FSL_DSPI || FSL_QSPI
+	select GPIO_EXTRA_HEADER
 	imply SCSI
 	help
 	  Support for Freescale LS1021AIOT platform.
@@ -1551,6 +1632,7 @@ config TARGET_LS1043AQDS
 	select FSL_DDR_INTERACTIVE if !SPL
 	select FSL_DSPI if !SPL_NO_DSPI
 	select DM_SPI_FLASH if FSL_DSPI
+	select GPIO_EXTRA_HEADER
 	imply SCSI
 	imply SCSI_AHCI
 	help
@@ -1567,6 +1649,7 @@ config TARGET_LS1043ARDB
 	select SUPPORT_SPL
 	select FSL_DSPI if !SPL_NO_DSPI
 	select DM_SPI_FLASH if FSL_DSPI
+	select GPIO_EXTRA_HEADER
 	help
 	  Support for Freescale LS1043ARDB platform.
 
@@ -1583,6 +1666,7 @@ config TARGET_LS1046AQDS
 	select FSL_DDR_BIST if !SPL
 	select FSL_DDR_INTERACTIVE  if !SPL
 	select FSL_DDR_INTERACTIVE if !SPL
+	select GPIO_EXTRA_HEADER
 	imply SCSI
 	help
 	  Support for Freescale LS1046AQDS platform.
@@ -1603,6 +1687,7 @@ config TARGET_LS1046ARDB
 	select SUPPORT_SPL
 	select FSL_DDR_BIST
 	select FSL_DDR_INTERACTIVE if !SPL
+	select GPIO_EXTRA_HEADER
 	imply SCSI
 	help
 	  Support for Freescale LS1046ARDB platform.
@@ -1619,6 +1704,7 @@ config TARGET_LS1046AFRWY
 	select BOARD_EARLY_INIT_F
 	select BOARD_LATE_INIT
 	select DM_SPI_FLASH if DM_SPI
+	select GPIO_EXTRA_HEADER
 	imply SCSI
 	help
 	  Support for Freescale LS1046AFRWY platform.
@@ -1647,6 +1733,7 @@ config TARGET_SL28
 	select DM_SERIAL
 	select DM_SPI
 	select DM_USB
+	select GPIO_EXTRA_HEADER
 	select SPL_DM if SPL
 	select SPL_DM_SPI if SPL
 	select SPL_DM_SPI_FLASH if SPL
@@ -1659,6 +1746,7 @@ config TARGET_SL28
 config TARGET_COLIBRI_PXA270
 	bool "Support colibri_pxa270"
 	select CPU_PXA
+	select GPIO_EXTRA_HEADER
 
 config ARCH_UNIPHIER
 	bool "Socionext UniPhier SoCs"
@@ -1690,11 +1778,25 @@ config ARCH_UNIPHIER
 	  Support for UniPhier SoC family developed by Socionext Inc.
 	  (formerly, System LSI Business Division of Panasonic Corporation)
 
+config ARCH_SYNQUACER
+	bool "Socionext SynQuacer SoCs"
+	select ARM64
+	select DM
+	select GIC_V3
+	select PSCI_RESET
+	select SYSRESET
+	select SYSRESET_PSCI
+	select OF_CONTROL
+	help
+	  Support for SynQuacer SoC family developed by Socionext Inc.
+	  This SoC is used on 96boards EE DeveloperBox.
+
 config ARCH_STM32
 	bool "Support STMicroelectronics STM32 MCU with cortex M"
 	select CPU_V7M
 	select DM
 	select DM_SERIAL
+	select GPIO_EXTRA_HEADER
 	imply CMD_DM
 
 config ARCH_STI
@@ -1720,6 +1822,7 @@ config ARCH_STM32MP
 	select DM_GPIO
 	select DM_RESET
 	select DM_SERIAL
+	select GPIO_EXTRA_HEADER
 	select MISC
 	select OF_CONTROL
 	select OF_LIBFDT
@@ -1782,6 +1885,7 @@ config ARCH_OCTEONTX
 	bool "Support OcteonTX SoCs"
 	select CLK
 	select DM
+	select GPIO_EXTRA_HEADER
 	select ARM64
 	select OF_CONTROL
 	select OF_LIVE
@@ -1792,6 +1896,7 @@ config ARCH_OCTEONTX2
 	bool "Support OcteonTX2 SoCs"
 	select CLK
 	select DM
+	select GPIO_EXTRA_HEADER
 	select ARM64
 	select OF_CONTROL
 	select OF_LIVE
@@ -1801,6 +1906,7 @@ config ARCH_OCTEONTX2
 config TARGET_THUNDERX_88XX
 	bool "Support ThunderX 88xx"
 	select ARM64
+	select GPIO_EXTRA_HEADER
 	select OF_CONTROL
 	select PL01X_SERIAL
 	select SYS_CACHE_SHIFT_7
@@ -1814,6 +1920,7 @@ config ARCH_ASPEED
 config TARGET_DURIAN
 	bool "Support Phytium Durian Platform"
 	select ARM64
+	select GPIO_EXTRA_HEADER
 	help
 	  Support for durian platform.
 	  It has 2GB Sdram, uart and pcie.
@@ -2027,6 +2134,7 @@ source "board/isee/igep003x/Kconfig"
 source "board/kontron/sl28/Kconfig"
 source "board/myir/mys_6ulx/Kconfig"
 source "board/seeed/npi_imx6ull/Kconfig"
+source "board/socionext/developerbox/Kconfig"
 source "board/spear/spear300/Kconfig"
 source "board/spear/spear310/Kconfig"
 source "board/spear/spear320/Kconfig"
diff --git a/arch/arm/cpu/armv7/iproc-common/armpll.c b/arch/arm/cpu/armv7/iproc-common/armpll.c
index efa3d9e5a9..8c3a323f06 100644
--- a/arch/arm/cpu/armv7/iproc-common/armpll.c
+++ b/arch/arm/cpu/armv7/iproc-common/armpll.c
@@ -19,19 +19,22 @@ struct armpll_parameters {
 };
 
 struct armpll_parameters armpll_clk_tab[] = {
-	{   25, 64,      1, 1, 0},
-	{  100, 64,      1, 1, 2},
-	{  400, 64,      1, 1, 6},
-	{  448, 71, 713050, 1, 6},
-	{  500, 80,      1, 1, 6},
-	{  560, 89, 629145, 1, 6},
-	{  600, 96,      1, 1, 6},
-	{  800, 64,      1, 1, 7},
-	{  896, 71, 713050, 1, 7},
-	{ 1000, 80,      1, 1, 7},
-	{ 1100, 88,      1, 1, 7},
-	{ 1120, 89, 629145, 1, 7},
-	{ 1200, 96,      1, 1, 7},
+	{   25,  64,      1, 1, 0},
+	{  100,  64,      1, 1, 2},
+	{  400,  64,      1, 1, 6},
+	{  448,  71, 713050, 1, 6},
+	{  500,  80,      1, 1, 6},
+	{  560,  89, 629145, 1, 6},
+	{  600,  96,      1, 1, 6},
+	{  800,  64,      1, 1, 7},
+	{  896,  71, 713050, 1, 7},
+	{ 1000,  80,      1, 1, 7},
+	{ 1100,  88,      1, 1, 7},
+	{ 1120,  89, 629145, 1, 7},
+	{ 1200,  96,      1, 1, 7},
+	{ 1300, 104,      1, 1, 7},
+	{ 1350, 108,      1, 1, 7},
+	{ 1400, 112,      1, 1, 7},
 };
 
 uint32_t armpll_config(uint32_t clkmhz)
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index eef94c4706..59d8078558 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -249,6 +249,7 @@ dtb-$(CONFIG_ARCH_MVEBU) +=			\
 	cn9130-crb-A.dtb			\
 	cn9130-crb-B.dtb
 
+dtb-$(CONFIG_ARCH_SYNQUACER) += synquacer-sc2a11-developerbox.dtb
 dtb-$(CONFIG_ARCH_UNIPHIER_LD11) += \
 	uniphier-ld11-global.dtb \
 	uniphier-ld11-ref.dtb
@@ -1116,6 +1117,8 @@ dtb-$(CONFIG_TARGET_PRESIDIO_ASIC) += ca-presidio-engboard.dtb
 
 dtb-$(CONFIG_TARGET_IMX8MM_CL_IOT_GATE) += imx8mm-cl-iot-gate.dtb
 
+dtb-$(CONFIG_TARGET_EA_LPC3250DEVKITV2) += lpc3250-ea3250.dtb
+
 targets += $(dtb-y)
 
 # Add any required device tree compiler flags here
diff --git a/arch/arm/dts/dragonboard410c.dts b/arch/arm/dts/dragonboard410c.dts
index fa348bc621..7e56140df2 100644
--- a/arch/arm/dts/dragonboard410c.dts
+++ b/arch/arm/dts/dragonboard410c.dts
@@ -8,6 +8,7 @@
 /dts-v1/;
 
 #include "skeleton64.dtsi"
+#include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/pinctrl/pinctrl-snapdragon.h>
 
 / {
@@ -91,7 +92,7 @@
 			gpio-controller;
 			gpio-count = <122>;
 			gpio-bank-name="soc";
-			#gpio-cells = <1>;
+			#gpio-cells = <2>;
 		};
 
 		ehci@78d9000 {
@@ -123,6 +124,7 @@
 			bus-width = <0x4>;
 			clock = <&clkc 1>;
 			clock-frequency = <200000000>;
+			cd-gpios = <&soc_gpios 38 GPIO_ACTIVE_LOW>;
 		};
 
 		wcnss {
diff --git a/arch/arm/dts/lpc3250-ea3250-u-boot.dtsi b/arch/arm/dts/lpc3250-ea3250-u-boot.dtsi
new file mode 100644
index 0000000000..0c82e512c6
--- /dev/null
+++ b/arch/arm/dts/lpc3250-ea3250-u-boot.dtsi
@@ -0,0 +1,15 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2021 Trevor Woerner <twoerner@gmail.com>
+ */
+
+/{
+	model = "Embedded Artists LPC3250 DevKit v2 board based on the NXP LPC3250 SoC";
+	chosen {
+		stdout-path = &uart5;
+	};
+};
+
+&uart5 {
+	compatible = "nxp,lpc3220-uart", "ns16550a";
+};
diff --git a/arch/arm/dts/lpc3250-ea3250.dts b/arch/arm/dts/lpc3250-ea3250.dts
new file mode 100644
index 0000000000..63c6f17bb7
--- /dev/null
+++ b/arch/arm/dts/lpc3250-ea3250.dts
@@ -0,0 +1,273 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Embedded Artists LPC3250 board
+ *
+ * Copyright 2012 Roland Stigge <stigge@antcom.de>
+ */
+
+/dts-v1/;
+#include "lpc32xx.dtsi"
+
+/ {
+	model = "Embedded Artists LPC3250 board based on NXP LPC3250";
+	compatible = "ea,ea3250", "nxp,lpc3250";
+
+	memory@80000000 {
+		device_type = "memory";
+		reg = <0x80000000 0x4000000>;
+	};
+
+	gpio-keys {
+		compatible = "gpio-keys";
+		autorepeat;
+
+		button {
+			label = "Interrupt Key";
+			linux,code = <103>;
+			gpios = <&gpio 4 1 0>; /* GPI_P3 1 */
+		};
+
+		key1 {
+			label = "KEY1";
+			linux,code = <1>;
+			gpios = <&pca9532 0 0>;
+		};
+
+		key2 {
+			label = "KEY2";
+			linux,code = <2>;
+			gpios = <&pca9532 1 0>;
+		};
+
+		key3 {
+			label = "KEY3";
+			linux,code = <3>;
+			gpios = <&pca9532 2 0>;
+		};
+
+		key4 {
+			label = "KEY4";
+			linux,code = <4>;
+			gpios = <&pca9532 3 0>;
+		};
+
+		joy0 {
+			label = "Joystick Key 0";
+			linux,code = <10>;
+			gpios = <&gpio 2 0 0>; /* P2.0 */
+		};
+
+		joy1 {
+			label = "Joystick Key 1";
+			linux,code = <11>;
+			gpios = <&gpio 2 1 0>; /* P2.1 */
+		};
+
+		joy2 {
+			label = "Joystick Key 2";
+			linux,code = <12>;
+			gpios = <&gpio 2 2 0>; /* P2.2 */
+		};
+
+		joy3 {
+			label = "Joystick Key 3";
+			linux,code = <13>;
+			gpios = <&gpio 2 3 0>; /* P2.3 */
+		};
+
+		joy4 {
+			label = "Joystick Key 4";
+			linux,code = <14>;
+			gpios = <&gpio 2 4 0>; /* P2.4 */
+		};
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		/* LEDs on OEM Board */
+
+		led1 {
+			gpios = <&gpio 5 14 1>; /* GPO_P3 14, GPIO 93, active low */
+			linux,default-trigger = "timer";
+			default-state = "off";
+		};
+
+		led2 {
+			gpios = <&gpio 2 10 1>; /* P2.10, active low */
+			default-state = "off";
+		};
+
+		led3 {
+			gpios = <&gpio 2 11 1>; /* P2.11, active low */
+			default-state = "off";
+		};
+
+		led4 {
+			gpios = <&gpio 2 12 1>; /* P2.12, active low */
+			default-state = "off";
+		};
+
+		/* LEDs on Base Board */
+
+		lede1 {
+			gpios = <&pca9532 8 0>;
+			default-state = "off";
+		};
+		lede2 {
+			gpios = <&pca9532 9 0>;
+			default-state = "off";
+		};
+		lede3 {
+			gpios = <&pca9532 10 0>;
+			default-state = "off";
+		};
+		lede4 {
+			gpios = <&pca9532 11 0>;
+			default-state = "off";
+		};
+		lede5 {
+			gpios = <&pca9532 12 0>;
+			default-state = "off";
+		};
+		lede6 {
+			gpios = <&pca9532 13 0>;
+			default-state = "off";
+		};
+		lede7 {
+			gpios = <&pca9532 14 0>;
+			default-state = "off";
+		};
+		lede8 {
+			gpios = <&pca9532 15 0>;
+			default-state = "off";
+		};
+	};
+};
+
+/* 3-axis accelerometer X,Y,Z (or AD-IN instead of Z) */
+&adc {
+	status = "okay";
+};
+
+&i2c1 {
+	clock-frequency = <100000>;
+
+	uda1380: uda1380@18 {
+		compatible = "nxp,uda1380";
+		reg = <0x18>;
+		power-gpio = <&gpio 3 10 0>;
+		reset-gpio = <&gpio 3 2 0>;
+		dac-clk = "wspll";
+	};
+
+	eeprom@50 {
+		compatible = "atmel,24c256";
+		reg = <0x50>;
+	};
+
+	eeprom@57 {
+		compatible = "atmel,24c64";
+		reg = <0x57>;
+	};
+
+	pca9532: pca9532@60 {
+		compatible = "nxp,pca9532";
+		gpio-controller;
+		#gpio-cells = <2>;
+		reg = <0x60>;
+	};
+};
+
+&i2c2 {
+	clock-frequency = <100000>;
+};
+
+&i2cusb {
+	clock-frequency = <100000>;
+
+	isp1301: usb-transceiver@2d {
+		compatible = "nxp,isp1301";
+		reg = <0x2d>;
+	};
+};
+
+&mac {
+	phy-mode = "rmii";
+	use-iram;
+	status = "okay";
+};
+
+/* Here, choose exactly one from: ohci, usbd */
+&ohci /* &usbd */ {
+	transceiver = <&isp1301>;
+	status = "okay";
+};
+
+&sd {
+	wp-gpios = <&pca9532 5 0>;
+	cd-gpios = <&pca9532 4 0>;
+	cd-inverted;
+	bus-width = <4>;
+	status = "okay";
+};
+
+/* 128MB Flash via SLC NAND controller */
+&slc {
+	status = "okay";
+
+	nxp,wdr-clks = <14>;
+	nxp,wwidth = <260000000>;
+	nxp,whold = <104000000>;
+	nxp,wsetup = <200000000>;
+	nxp,rdr-clks = <14>;
+	nxp,rwidth = <34666666>;
+	nxp,rhold = <104000000>;
+	nxp,rsetup = <200000000>;
+	nand-on-flash-bbt;
+	gpios = <&gpio 5 19 1>; /* GPO_P3 19, active low */
+
+	partitions {
+		compatible = "fixed-partitions";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		mtd0@0 {
+			label = "ea3250-boot";
+			reg = <0x00000000 0x00080000>;
+			read-only;
+		};
+
+		mtd1@80000 {
+			label = "ea3250-uboot";
+			reg = <0x00080000 0x000c0000>;
+			read-only;
+		};
+
+		mtd2@140000 {
+			label = "ea3250-kernel";
+			reg = <0x00140000 0x00400000>;
+		};
+
+		mtd3@540000 {
+			label = "ea3250-rootfs";
+			reg = <0x00540000 0x07ac0000>;
+		};
+	};
+};
+
+&uart1 {
+	status = "okay";
+};
+
+&uart3 {
+	status = "okay";
+};
+
+&uart5 {
+	status = "okay";
+};
+
+&uart6 {
+	status = "okay";
+};
diff --git a/arch/arm/dts/lpc32xx.dtsi b/arch/arm/dts/lpc32xx.dtsi
new file mode 100644
index 0000000000..c87066d6c9
--- /dev/null
+++ b/arch/arm/dts/lpc32xx.dtsi
@@ -0,0 +1,508 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * NXP LPC32xx SoC
+ *
+ * Copyright (C) 2015-2019 Vladimir Zapolskiy <vz@mleia.com>
+ * Copyright 2012 Roland Stigge <stigge@antcom.de>
+ */
+
+#include <dt-bindings/clock/lpc32xx-clock.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+	#address-cells = <1>;
+	#size-cells = <1>;
+	compatible = "nxp,lpc3220";
+	interrupt-parent = <&mic>;
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			compatible = "arm,arm926ej-s";
+			device_type = "cpu";
+			reg = <0x0>;
+		};
+	};
+
+	clocks {
+		xtal_32k: xtal_32k {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <32768>;
+			clock-output-names = "xtal_32k";
+		};
+
+		xtal: xtal {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <13000000>;
+			clock-output-names = "xtal";
+		};
+	};
+
+	ahb {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "simple-bus";
+		ranges = <0x00000000 0x00000000 0x10000000>,
+			 <0x20000000 0x20000000 0x30000000>,
+			 <0xe0000000 0xe0000000 0x04000000>;
+
+		iram: sram@8000000 {
+			compatible = "mmio-sram";
+			reg = <0x08000000 0x20000>;
+
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0x00000000 0x08000000 0x20000>;
+		};
+
+		/*
+		 * Enable either SLC or MLC
+		 */
+		slc: flash@20020000 {
+			compatible = "nxp,lpc3220-slc";
+			reg = <0x20020000 0x1000>;
+			clocks = <&clk LPC32XX_CLK_SLC>;
+			status = "disabled";
+		};
+
+		mlc: flash@200a8000 {
+			compatible = "nxp,lpc3220-mlc";
+			reg = <0x200a8000 0x11000>;
+			interrupts = <11 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clk LPC32XX_CLK_MLC>;
+			status = "disabled";
+		};
+
+		dma: dma@31000000 {
+			compatible = "arm,pl080", "arm,primecell";
+			reg = <0x31000000 0x1000>;
+			interrupts = <28 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clk LPC32XX_CLK_DMA>;
+			clock-names = "apb_pclk";
+		};
+
+		usb {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			compatible = "simple-bus";
+			ranges = <0x0 0x31020000 0x00001000>;
+
+			/*
+			 * Enable either ohci or usbd (gadget)!
+			 */
+			ohci: ohci@0 {
+				compatible = "nxp,ohci-nxp", "usb-ohci";
+				reg = <0x0 0x300>;
+				interrupt-parent = <&sic1>;
+				interrupts = <27 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&usbclk LPC32XX_USB_CLK_HOST>;
+				status = "disabled";
+			};
+
+			usbd: usbd@0 {
+				compatible = "nxp,lpc3220-udc";
+				reg = <0x0 0x300>;
+				interrupt-parent = <&sic1>;
+				interrupts = <29 IRQ_TYPE_LEVEL_HIGH>,
+					     <30 IRQ_TYPE_LEVEL_HIGH>,
+					     <28 IRQ_TYPE_LEVEL_HIGH>,
+					     <26 IRQ_TYPE_LEVEL_LOW>;
+				clocks = <&usbclk LPC32XX_USB_CLK_DEVICE>;
+				status = "disabled";
+			};
+
+			i2cusb: i2c@300 {
+				compatible = "nxp,pnx-i2c";
+				reg = <0x300 0x100>;
+				interrupt-parent = <&sic1>;
+				interrupts = <31 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&usbclk LPC32XX_USB_CLK_I2C>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+			};
+
+			usbclk: clock-controller@f00 {
+				compatible = "nxp,lpc3220-usb-clk";
+				reg = <0xf00 0x100>;
+				#clock-cells = <1>;
+			};
+		};
+
+		clcd: clcd@31040000 {
+			compatible = "arm,pl111", "arm,primecell";
+			reg = <0x31040000 0x1000>;
+			interrupts = <14 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clk LPC32XX_CLK_LCD>, <&clk LPC32XX_CLK_LCD>;
+			clock-names = "clcdclk", "apb_pclk";
+			status = "disabled";
+		};
+
+		mac: ethernet@31060000 {
+			compatible = "nxp,lpc-eth";
+			reg = <0x31060000 0x1000>;
+			interrupts = <29 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clk LPC32XX_CLK_MAC>;
+			status = "disabled";
+		};
+
+		emc: memory-controller@31080000 {
+			compatible = "arm,pl175", "arm,primecell";
+			reg = <0x31080000 0x1000>;
+			clocks = <&clk LPC32XX_CLK_DDRAM>, <&clk LPC32XX_CLK_DDRAM>;
+			clock-names = "mpmcclk", "apb_pclk";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			ranges = <0 0xe0000000 0x01000000>,
+				 <1 0xe1000000 0x01000000>,
+				 <2 0xe2000000 0x01000000>,
+				 <3 0xe3000000 0x01000000>;
+			status = "disabled";
+		};
+
+		apb {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			compatible = "simple-bus";
+			ranges = <0x20000000 0x20000000 0x30000000>;
+
+			/*
+			 * ssp0 and spi1 are shared pins;
+			 * enable one in your board dts, as needed.
+			 */
+			ssp0: spi@20084000 {
+				compatible = "arm,pl022", "arm,primecell";
+				reg = <0x20084000 0x1000>;
+				interrupts = <20 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk LPC32XX_CLK_SSP0>;
+				clock-names = "apb_pclk";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+			};
+
+			spi1: spi@20088000 {
+				compatible = "nxp,lpc3220-spi";
+				reg = <0x20088000 0x1000>;
+				clocks = <&clk LPC32XX_CLK_SPI1>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+			};
+
+			/*
+			 * ssp1 and spi2 are shared pins;
+			 * enable one in your board dts, as needed.
+			 */
+			ssp1: spi@2008c000 {
+				compatible = "arm,pl022", "arm,primecell";
+				reg = <0x2008c000 0x1000>;
+				interrupts = <21 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk LPC32XX_CLK_SSP1>;
+				clock-names = "apb_pclk";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+			};
+
+			spi2: spi@20090000 {
+				compatible = "nxp,lpc3220-spi";
+				reg = <0x20090000 0x1000>;
+				clocks = <&clk LPC32XX_CLK_SPI2>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+			};
+
+			i2s0: i2s@20094000 {
+				compatible = "nxp,lpc3220-i2s";
+				reg = <0x20094000 0x1000>;
+				status = "disabled";
+			};
+
+			sd: sd@20098000 {
+				compatible = "arm,pl18x", "arm,primecell";
+				reg = <0x20098000 0x1000>;
+				interrupts = <15 IRQ_TYPE_LEVEL_HIGH>,
+					     <13 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk LPC32XX_CLK_SD>;
+				clock-names = "apb_pclk";
+				status = "disabled";
+			};
+
+			i2s1: i2s@2009c000 {
+				compatible = "nxp,lpc3220-i2s";
+				reg = <0x2009c000 0x1000>;
+				status = "disabled";
+			};
+
+			/* UART5 first since it is the default console, ttyS0 */
+			uart5: serial@40090000 {
+				/* actually, ns16550a w/ 64 byte fifos! */
+				compatible = "nxp,lpc3220-uart";
+				reg = <0x40090000 0x1000>;
+				interrupts = <9 IRQ_TYPE_LEVEL_HIGH>;
+				reg-shift = <2>;
+				clocks = <&clk LPC32XX_CLK_UART5>;
+				status = "disabled";
+			};
+
+			uart3: serial@40080000 {
+				compatible = "nxp,lpc3220-uart";
+				reg = <0x40080000 0x1000>;
+				interrupts = <7 IRQ_TYPE_LEVEL_HIGH>;
+				reg-shift = <2>;
+				clocks = <&clk LPC32XX_CLK_UART3>;
+				status = "disabled";
+			};
+
+			uart4: serial@40088000 {
+				compatible = "nxp,lpc3220-uart";
+				reg = <0x40088000 0x1000>;
+				interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
+				reg-shift = <2>;
+				clocks = <&clk LPC32XX_CLK_UART4>;
+				status = "disabled";
+			};
+
+			uart6: serial@40098000 {
+				compatible = "nxp,lpc3220-uart";
+				reg = <0x40098000 0x1000>;
+				interrupts = <10 IRQ_TYPE_LEVEL_HIGH>;
+				reg-shift = <2>;
+				clocks = <&clk LPC32XX_CLK_UART6>;
+				status = "disabled";
+			};
+
+			i2c1: i2c@400a0000 {
+				compatible = "nxp,pnx-i2c";
+				reg = <0x400a0000 0x100>;
+				interrupt-parent = <&sic1>;
+				interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				clocks = <&clk LPC32XX_CLK_I2C1>;
+			};
+
+			i2c2: i2c@400a8000 {
+				compatible = "nxp,pnx-i2c";
+				reg = <0x400a8000 0x100>;
+				interrupt-parent = <&sic1>;
+				interrupts = <18 IRQ_TYPE_LEVEL_LOW>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				clocks = <&clk LPC32XX_CLK_I2C2>;
+			};
+
+			mpwm: mpwm@400e8000 {
+				compatible = "nxp,lpc3220-motor-pwm";
+				reg = <0x400e8000 0x78>;
+				status = "disabled";
+				#pwm-cells = <2>;
+			};
+		};
+
+		fab {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			compatible = "simple-bus";
+			ranges = <0x20000000 0x20000000 0x30000000>;
+
+			/* System Control Block */
+			scb {
+				compatible = "simple-bus";
+				ranges = <0x0 0x040004000 0x00001000>;
+				#address-cells = <1>;
+				#size-cells = <1>;
+
+				clk: clock-controller@0 {
+					compatible = "nxp,lpc3220-clk";
+					reg = <0x00 0x114>;
+					#clock-cells = <1>;
+
+					clocks = <&xtal_32k>, <&xtal>;
+					clock-names = "xtal_32k", "xtal";
+				};
+			};
+
+			mic: interrupt-controller@40008000 {
+				compatible = "nxp,lpc3220-mic";
+				reg = <0x40008000 0x4000>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+			};
+
+			sic1: interrupt-controller@4000c000 {
+				compatible = "nxp,lpc3220-sic";
+				reg = <0x4000c000 0x4000>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+
+				interrupt-parent = <&mic>;
+				interrupts = <0 IRQ_TYPE_LEVEL_LOW>,
+					     <30 IRQ_TYPE_LEVEL_LOW>;
+				};
+
+			sic2: interrupt-controller@40010000 {
+				compatible = "nxp,lpc3220-sic";
+				reg = <0x40010000 0x4000>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+
+				interrupt-parent = <&mic>;
+				interrupts = <1 IRQ_TYPE_LEVEL_LOW>,
+					     <31 IRQ_TYPE_LEVEL_LOW>;
+			};
+
+			uart1: serial@40014000 {
+				compatible = "nxp,lpc3220-hsuart";
+				reg = <0x40014000 0x1000>;
+				interrupts = <26 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+
+			uart2: serial@40018000 {
+				compatible = "nxp,lpc3220-hsuart";
+				reg = <0x40018000 0x1000>;
+				interrupts = <25 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+
+			uart7: serial@4001c000 {
+				compatible = "nxp,lpc3220-hsuart";
+				reg = <0x4001c000 0x1000>;
+				interrupts = <24 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+
+			rtc: rtc@40024000 {
+				compatible = "nxp,lpc3220-rtc";
+				reg = <0x40024000 0x1000>;
+				interrupt-parent = <&sic1>;
+				interrupts = <20 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk LPC32XX_CLK_RTC>;
+			};
+
+			gpio: gpio@40028000 {
+				compatible = "nxp,lpc3220-gpio";
+				reg = <0x40028000 0x1000>;
+				gpio-controller;
+				#gpio-cells = <3>; /* bank, pin, flags */
+			};
+
+			timer4: timer@4002c000 {
+				compatible = "nxp,lpc3220-timer";
+				reg = <0x4002c000 0x1000>;
+				interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
+				clocks = <&clk LPC32XX_CLK_TIMER4>;
+				clock-names = "timerclk";
+				status = "disabled";
+			};
+
+			timer5: timer@40030000 {
+				compatible = "nxp,lpc3220-timer";
+				reg = <0x40030000 0x1000>;
+				interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
+				clocks = <&clk LPC32XX_CLK_TIMER5>;
+				clock-names = "timerclk";
+				status = "disabled";
+			};
+
+			watchdog: watchdog@4003c000 {
+				compatible = "nxp,pnx4008-wdt";
+				reg = <0x4003c000 0x1000>;
+				clocks = <&clk LPC32XX_CLK_WDOG>;
+			};
+
+			timer0: timer@40044000 {
+				compatible = "nxp,lpc3220-timer";
+				reg = <0x40044000 0x1000>;
+				clocks = <&clk LPC32XX_CLK_TIMER0>;
+				clock-names = "timerclk";
+				interrupts = <16 IRQ_TYPE_LEVEL_LOW>;
+			};
+
+			/*
+			 * TSC vs. ADC: Since those two share the same
+			 * hardware, you need to choose from one of the
+			 * following two and do 'status = "okay";' for one of
+			 * them
+			 */
+
+			adc: adc@40048000 {
+				compatible = "nxp,lpc3220-adc";
+				reg = <0x40048000 0x1000>;
+				interrupt-parent = <&sic1>;
+				interrupts = <7 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk LPC32XX_CLK_ADC>;
+				status = "disabled";
+			};
+
+			tsc: tsc@40048000 {
+				compatible = "nxp,lpc3220-tsc";
+				reg = <0x40048000 0x1000>;
+				interrupt-parent = <&sic1>;
+				interrupts = <7 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk LPC32XX_CLK_ADC>;
+				status = "disabled";
+			};
+
+			timer1: timer@4004c000 {
+				compatible = "nxp,lpc3220-timer";
+				reg = <0x4004c000 0x1000>;
+				interrupts = <17 IRQ_TYPE_LEVEL_LOW>;
+				clocks = <&clk LPC32XX_CLK_TIMER1>;
+				clock-names = "timerclk";
+			};
+
+			key: key@40050000 {
+				compatible = "nxp,lpc3220-key";
+				reg = <0x40050000 0x1000>;
+				clocks = <&clk LPC32XX_CLK_KEY>;
+				interrupt-parent = <&sic1>;
+				interrupts = <22 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+
+			timer2: timer@40058000 {
+				compatible = "nxp,lpc3220-timer";
+				reg = <0x40058000 0x1000>;
+				interrupts = <18 IRQ_TYPE_LEVEL_LOW>;
+				clocks = <&clk LPC32XX_CLK_TIMER2>;
+				clock-names = "timerclk";
+				status = "disabled";
+			};
+
+			pwm1: pwm@4005c000 {
+				compatible = "nxp,lpc3220-pwm";
+				reg = <0x4005c000 0x4>;
+				clocks = <&clk LPC32XX_CLK_PWM1>;
+				assigned-clocks = <&clk LPC32XX_CLK_PWM1>;
+				assigned-clock-parents = <&clk LPC32XX_CLK_PERIPH>;
+				status = "disabled";
+			};
+
+			pwm2: pwm@4005c004 {
+				compatible = "nxp,lpc3220-pwm";
+				reg = <0x4005c004 0x4>;
+				clocks = <&clk LPC32XX_CLK_PWM2>;
+				assigned-clocks = <&clk LPC32XX_CLK_PWM2>;
+				assigned-clock-parents = <&clk LPC32XX_CLK_PERIPH>;
+				status = "disabled";
+			};
+
+			timer3: timer@40060000 {
+				compatible = "nxp,lpc3220-timer";
+				reg = <0x40060000 0x1000>;
+				interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
+				clocks = <&clk LPC32XX_CLK_TIMER3>;
+				clock-names = "timerclk";
+				status = "disabled";
+			};
+		};
+	};
+};
diff --git a/arch/arm/dts/synquacer-sc2a11-caches.dtsi b/arch/arm/dts/synquacer-sc2a11-caches.dtsi
new file mode 100644
index 0000000000..177ddf8c2b
--- /dev/null
+++ b/arch/arm/dts/synquacer-sc2a11-caches.dtsi
@@ -0,0 +1,73 @@
+/** @file
+ * Copyright (c) 2018, Linaro Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-2-Clause-Patent
+ */
+
+#define __L1(cpuref, l2ref)                 \
+cpuref {                                    \
+    i-cache-size = <0x8000>;                \
+    i-cache-line-size = <64>;               \
+    i-cache-sets = <256>;                   \
+    d-cache-size = <0x8000>;                \
+    d-cache-line-size = <64>;               \
+    d-cache-sets = <128>;                   \
+    l2-cache = <l2ref>;                     \
+};
+
+#define __L2(idx)                           \
+L2_##idx: l2-cache##idx {                   \
+    cache-size = <0x40000>;                 \
+    cache-line-size = <64>;                 \
+    cache-sets = <256>;                     \
+    cache-unified;                          \
+    next-level-cache = <&L3>;               \
+};
+
+/ {
+    __L2(0)
+    __L2(1)
+    __L2(2)
+    __L2(3)
+    __L2(4)
+    __L2(5)
+    __L2(6)
+    __L2(7)
+    __L2(8)
+    __L2(9)
+    __L2(10)
+    __L2(11)
+
+    L3: l3-cache {
+        cache-level = <3>;
+        cache-size = <0x400000>;
+        cache-line-size = <64>;
+        cache-sets = <4096>;
+        cache-unified;
+    };
+};
+
+__L1(&CPU0, &L2_0)
+__L1(&CPU1, &L2_0)
+__L1(&CPU2, &L2_1)
+__L1(&CPU3, &L2_1)
+__L1(&CPU4, &L2_2)
+__L1(&CPU5, &L2_2)
+__L1(&CPU6, &L2_3)
+__L1(&CPU7, &L2_3)
+__L1(&CPU8, &L2_4)
+__L1(&CPU9, &L2_4)
+__L1(&CPU10, &L2_5)
+__L1(&CPU11, &L2_5)
+__L1(&CPU12, &L2_6)
+__L1(&CPU13, &L2_6)
+__L1(&CPU14, &L2_7)
+__L1(&CPU15, &L2_7)
+__L1(&CPU16, &L2_8)
+__L1(&CPU17, &L2_8)
+__L1(&CPU18, &L2_9)
+__L1(&CPU19, &L2_9)
+__L1(&CPU20, &L2_10)
+__L1(&CPU21, &L2_10)
+__L1(&CPU22, &L2_11)
+__L1(&CPU23, &L2_11)
diff --git a/arch/arm/dts/synquacer-sc2a11-developerbox-u-boot.dtsi b/arch/arm/dts/synquacer-sc2a11-developerbox-u-boot.dtsi
new file mode 100644
index 0000000000..2f13a42235
--- /dev/null
+++ b/arch/arm/dts/synquacer-sc2a11-developerbox-u-boot.dtsi
@@ -0,0 +1,75 @@
+// SPDX-License-Identifier: BSD-2-Clause-Patent
+//
+// Copyright (c) 2021, Linaro Limited. All rights reserved.
+//
+
+/ {
+	aliases {
+		spi_nor = &spi_nor;
+		i2c0 = &i2c0;
+	};
+
+	spi_nor: spi@54800000 {
+		compatible = "socionext,synquacer-spi";
+		reg = <0x00 0x54800000 0x00 0x1000>;
+		interrupts = <0x00 0x9c 0x04 0x00 0x9d 0x04 0x00 0x9e 0x04>;
+		clocks = <&clk_alw_1_8>;
+		clock-names = "iHCLK";
+		socionext,use-rtm;
+		socionext,set-aces;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "okay";
+		active_clk_edges;
+		chipselect_num = <1>;
+
+		spi-flash@0 {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			compatible = "jedec,spi-nor";
+			reg = <0>; /* Chip select 0 */
+			spi-max-frequency = <31250000>;
+			spi-rx-bus-width = <0x1>;
+			spi-tx-bus-width = <0x1>;
+		};
+	};
+
+	i2c0: i2c@51200000 {
+		compatible = "socionext,synquacer-i2c";
+		reg = <0x0 0x51200000 0x0 0x1000>;
+		interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&clk_i2c>;
+		clock-names = "pclk";
+		clock-frequency = <400000>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "okay";
+
+		pcf8563: rtc@51 {
+			compatible = "nxp,pcf8563";
+			reg = <0x51>;
+		};
+	};
+
+	firmware {
+		optee {
+			status = "okay";
+		};
+	};
+};
+
+&smmu {
+	status = "okay";
+};
+
+&pcie0 {
+	status = "okay";
+};
+
+&pcie1 {
+	status = "okay";
+};
+
+&sdhci {
+	status = "okay";
+};
diff --git a/arch/arm/dts/synquacer-sc2a11-developerbox.dts b/arch/arm/dts/synquacer-sc2a11-developerbox.dts
new file mode 100644
index 0000000000..42b6cbbb82
--- /dev/null
+++ b/arch/arm/dts/synquacer-sc2a11-developerbox.dts
@@ -0,0 +1,56 @@
+/** @file
+ * Copyright (c) 2017, Linaro Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-2-Clause-Patent
+ */
+
+/dts-v1/;
+
+#include "synquacer-sc2a11.dtsi"
+
+#define KEY_POWER     116
+
+/ {
+    model = "Socionext Developer Box";
+    compatible = "socionext,developer-box", "socionext,synquacer";
+
+    gpio-keys {
+        compatible = "gpio-keys";
+        interrupt-parent = <&exiu>;
+
+        power {
+            label = "Power Button";
+            linux,code = <KEY_POWER>;
+            interrupts = <GIC_SPI 120 IRQ_TYPE_EDGE_FALLING>;
+            wakeup-source;
+        };
+    };
+};
+
+#ifdef TPM2_ENABLE
+&tpm {
+    status = "okay";
+};
+#endif
+
+&gpio {
+    gpio-line-names = "DSW3-PIN1",  "DSW3-PIN2",  "DSW3-PIN3",    "DSW3-PIN4",
+                      "DSW3-PIN5",  "DSW3-PIN6",  "DSW3-PIN7",    "DSW3-PIN8",
+                      "PSIN#",      "PWROFF#",    "GPIO-A",       "GPIO-B",
+                      "GPIO-C",     "GPIO-D",     "PCIE1EXTINT",  "PCIE0EXTINT",
+                      "PHY2-INT#",  "PHY1-INT#",  "GPIO-E",       "GPIO-F",
+                      "GPIO-G",     "GPIO-H",     "GPIO-I",       "GPIO-J",
+                      "GPIO-K",     "GPIO-L",     "PEC-PD26",     "PEC-PD27",
+                      "PEC-PD28",   "PEC-PD29",   "PEC-PD30",     "PEC-PD31";
+};
+
+&netsec {
+    phy-mode = "rgmii-id";
+};
+
+&mdio_netsec {
+    phy_netsec: ethernet-phy@7 {
+        compatible = "ethernet-phy-ieee802.3-c22";
+        reg = <7>;
+    };
+};
diff --git a/arch/arm/dts/synquacer-sc2a11.dtsi b/arch/arm/dts/synquacer-sc2a11.dtsi
new file mode 100644
index 0000000000..1fe7d214b9
--- /dev/null
+++ b/arch/arm/dts/synquacer-sc2a11.dtsi
@@ -0,0 +1,595 @@
+/** @file
+ * Copyright (c) 2017 - 2018, Linaro Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-2-Clause-Patent
+ */
+
+/* These are added for U-Boot to avoid compilation error */
+#define PcdNetsecEepromBase	0x08080000
+#define FixedPcdGet32(n)	n
+
+#define GIC_SPI                 0
+#define GIC_PPI                 1
+
+#define IRQ_TYPE_NONE           0
+#define IRQ_TYPE_EDGE_RISING    1
+#define IRQ_TYPE_EDGE_FALLING   2
+#define IRQ_TYPE_EDGE_BOTH      (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)
+#define IRQ_TYPE_LEVEL_HIGH     4
+#define IRQ_TYPE_LEVEL_LOW      8
+
+#define GPIO_ACTIVE_HIGH        0
+#define GPIO_ACTIVE_LOW         1
+
+/ {
+    #address-cells = <2>;
+    #size-cells = <2>;
+    interrupt-parent = <&gic>;
+
+    aliases {
+        serial0 = &soc_uart0;
+        serial1 = &fuart;
+    };
+
+    chosen {
+        stdout-path = "serial0:115200n8";
+    };
+
+    cpus {
+        #address-cells = <1>;
+        #size-cells = <0>;
+
+        CPU0: cpu@0 {
+            device_type = "cpu";
+            compatible = "arm,cortex-a53","arm,armv8";
+            reg = <0x0>;
+            enable-method = "psci";
+            cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+        };
+        CPU1: cpu@1 {
+            device_type = "cpu";
+            compatible = "arm,cortex-a53","arm,armv8";
+            reg = <0x1>;
+            enable-method = "psci";
+            cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+        };
+        CPU2: cpu@100 {
+            device_type = "cpu";
+            compatible = "arm,cortex-a53","arm,armv8";
+            reg = <0x100>;
+            enable-method = "psci";
+            cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+        };
+        CPU3: cpu@101 {
+            device_type = "cpu";
+            compatible = "arm,cortex-a53","arm,armv8";
+            reg = <0x101>;
+            enable-method = "psci";
+            cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+        };
+        CPU4: cpu@200 {
+            device_type = "cpu";
+            compatible = "arm,cortex-a53","arm,armv8";
+            reg = <0x200>;
+            enable-method = "psci";
+            cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+        };
+        CPU5: cpu@201 {
+            device_type = "cpu";
+            compatible = "arm,cortex-a53","arm,armv8";
+            reg = <0x201>;
+            enable-method = "psci";
+            cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+        };
+        CPU6: cpu@300 {
+            device_type = "cpu";
+            compatible = "arm,cortex-a53","arm,armv8";
+            reg = <0x300>;
+            enable-method = "psci";
+            cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+        };
+        CPU7: cpu@301 {
+            device_type = "cpu";
+            compatible = "arm,cortex-a53","arm,armv8";
+            reg = <0x301>;
+            enable-method = "psci";
+            cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+        };
+        CPU8: cpu@400 {
+            device_type = "cpu";
+            compatible = "arm,cortex-a53","arm,armv8";
+            reg = <0x400>;
+            enable-method = "psci";
+            cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+        };
+        CPU9: cpu@401 {
+            device_type = "cpu";
+            compatible = "arm,cortex-a53","arm,armv8";
+            reg = <0x401>;
+            enable-method = "psci";
+            cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+        };
+        CPU10: cpu@500 {
+            device_type = "cpu";
+            compatible = "arm,cortex-a53","arm,armv8";
+            reg = <0x500>;
+            enable-method = "psci";
+            cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+        };
+        CPU11: cpu@501 {
+            device_type = "cpu";
+            compatible = "arm,cortex-a53","arm,armv8";
+            reg = <0x501>;
+            enable-method = "psci";
+            cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+        };
+        CPU12: cpu@600 {
+            device_type = "cpu";
+            compatible = "arm,cortex-a53","arm,armv8";
+            reg = <0x600>;
+            enable-method = "psci";
+            cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+        };
+        CPU13: cpu@601 {
+            device_type = "cpu";
+            compatible = "arm,cortex-a53","arm,armv8";
+            reg = <0x601>;
+            enable-method = "psci";
+            cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+        };
+        CPU14: cpu@700 {
+            device_type = "cpu";
+            compatible = "arm,cortex-a53","arm,armv8";
+            reg = <0x700>;
+            enable-method = "psci";
+            cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+        };
+        CPU15: cpu@701 {
+            device_type = "cpu";
+            compatible = "arm,cortex-a53","arm,armv8";
+            reg = <0x701>;
+            enable-method = "psci";
+            cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+        };
+        CPU16: cpu@800 {
+            device_type = "cpu";
+            compatible = "arm,cortex-a53","arm,armv8";
+            reg = <0x800>;
+            enable-method = "psci";
+            cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+        };
+        CPU17: cpu@801 {
+            device_type = "cpu";
+            compatible = "arm,cortex-a53","arm,armv8";
+            reg = <0x801>;
+            enable-method = "psci";
+            cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+        };
+        CPU18: cpu@900 {
+            device_type = "cpu";
+            compatible = "arm,cortex-a53","arm,armv8";
+            reg = <0x900>;
+            enable-method = "psci";
+            cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+        };
+        CPU19: cpu@901 {
+            device_type = "cpu";
+            compatible = "arm,cortex-a53","arm,armv8";
+            reg = <0x901>;
+            enable-method = "psci";
+            cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+        };
+        CPU20: cpu@a00 {
+            device_type = "cpu";
+            compatible = "arm,cortex-a53","arm,armv8";
+            reg = <0xa00>;
+            enable-method = "psci";
+            cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+        };
+        CPU21: cpu@a01 {
+            device_type = "cpu";
+            compatible = "arm,cortex-a53","arm,armv8";
+            reg = <0xa01>;
+            enable-method = "psci";
+            cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+        };
+        CPU22: cpu@b00 {
+            device_type = "cpu";
+            compatible = "arm,cortex-a53","arm,armv8";
+            reg = <0xb00>;
+            enable-method = "psci";
+            cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+        };
+        CPU23: cpu@b01 {
+            device_type = "cpu";
+            compatible = "arm,cortex-a53","arm,armv8";
+            reg = <0xb01>;
+            enable-method = "psci";
+            cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+        };
+
+        cpu-map {
+            cluster0 {
+                core0 {
+                    cpu = <&CPU0>;
+                };
+                core1 {
+                    cpu = <&CPU1>;
+                };
+            };
+             cluster1 {
+                core0 {
+                    cpu = <&CPU2>;
+                };
+                core1 {
+                    cpu = <&CPU3>;
+                };
+            };
+            cluster2 {
+                core0 {
+                    cpu = <&CPU4>;
+                };
+                core1 {
+                    cpu = <&CPU5>;
+                };
+            };
+            cluster3 {
+                core0 {
+                    cpu = <&CPU6>;
+                };
+                core1 {
+                    cpu = <&CPU7>;
+                };
+            };
+            cluster4 {
+                core0 {
+                    cpu = <&CPU8>;
+                };
+                core1 {
+                    cpu = <&CPU9>;
+                };
+            };
+            cluster5 {
+                core0 {
+                    cpu = <&CPU10>;
+                };
+                core1 {
+                    cpu = <&CPU11>;
+                };
+            };
+            cluster6 {
+                core0 {
+                    cpu = <&CPU12>;
+                };
+                core1 {
+                    cpu = <&CPU13>;
+                };
+            };
+            cluster7 {
+                core0 {
+                    cpu = <&CPU14>;
+                };
+                core1 {
+                    cpu = <&CPU15>;
+                };
+            };
+            cluster8 {
+                core0 {
+                    cpu = <&CPU16>;
+                };
+                core1 {
+                    cpu = <&CPU17>;
+                };
+            };
+            cluster9 {
+                core0 {
+                    cpu = <&CPU18>;
+                };
+                core1 {
+                    cpu = <&CPU19>;
+                };
+            };
+            cluster10 {
+                core0 {
+                    cpu = <&CPU20>;
+                };
+                core1 {
+                    cpu = <&CPU21>;
+                };
+            };
+            cluster11 {
+                core0 {
+                    cpu = <&CPU22>;
+                };
+                core1 {
+                    cpu = <&CPU23>;
+                };
+            };
+        };
+    };
+
+    idle-states {
+        entry-method = "arm,psci";
+
+        CPU_SLEEP_0: cpu-sleep-0 {
+            compatible = "arm,idle-state";
+            arm,psci-suspend-param = <0x0010000>;
+            entry-latency-us = <300>;
+            exit-latency-us = <1200>;
+            min-residency-us = <2000>;
+            local-timer-stop;
+        };
+
+        CLUSTER_SLEEP_0: cluster-sleep-0 {
+            compatible = "arm,idle-state";
+            arm,psci-suspend-param = <0x1010000>;
+            entry-latency-us = <400>;
+            exit-latency-us = <1200>;
+            min-residency-us = <2500>;
+            local-timer-stop;
+        };
+    };
+
+    gic: interrupt-controller@30000000 {
+        compatible = "arm,gic-v3";
+        reg = <0x0 0x30000000 0x0 0x10000>,      // GICD
+              <0x0 0x30400000 0x0 0x300000>,     // GICR
+              <0x0 0x2c000000 0x0 0x2000>,       // GICC
+              <0x0 0x2c010000 0x0 0x1000>,       // GICH
+              <0x0 0x2c020000 0x0 0x10000>;      // GICV
+        #interrupt-cells = <3>;
+        #address-cells = <2>;
+        #size-cells = <2>;
+        ranges;
+        interrupt-controller;
+        interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
+
+        its: gic-its@30020000 {
+            compatible = "arm,gic-v3-its";
+            reg = <0x0 0x30020000 0x0 0x20000>;
+            #msi-cells = <1>;
+            msi-controller;
+            socionext,synquacer-pre-its = <0x58000000 0x200000>;
+        };
+    };
+
+    timer {
+        compatible = "arm,armv8-timer";
+        interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,   // secure
+                     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,   // non-secure
+                     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,   // virtual
+                     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;   // HYP
+    };
+
+    mmio-timer@2a810000 {
+        compatible = "arm,armv7-timer-mem";
+        reg = <0x0 0x2a810000 0x0 0x10000>;
+        #address-cells = <2>;
+        #size-cells = <2>;
+        ranges;
+        frame@2a830000 {
+            frame-number = <0>;
+            interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
+            reg = <0x0 0x2a830000 0x0 0x10000>;
+        };
+    };
+
+    pmu {
+        compatible = "arm,cortex-a53-pmu";
+        interrupts =  <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
+    };
+
+    psci {
+        compatible = "arm,psci-1.0";
+        method = "smc";
+    };
+
+    clk_uart: refclk62500khz {
+        compatible = "fixed-clock";
+        #clock-cells = <0>;
+        clock-frequency = <62500000>;
+        clock-output-names = "uartclk";
+    };
+
+    clk_apb: refclk100mhz {
+        compatible = "fixed-clock";
+        #clock-cells = <0>;
+        clock-frequency = <100000000>;
+        clock-output-names = "apb_pclk";
+    };
+
+    soc_uart0: uart@2a400000 {
+        compatible = "arm,pl011", "arm,primecell";
+        reg = <0x0 0x2a400000 0x0 0x1000>;
+        interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
+        clocks = <&clk_uart>, <&clk_apb>;
+        clock-names = "uartclk", "apb_pclk";
+    };
+
+    fuart: uart@51040000 {
+        compatible = "snps,dw-apb-uart";
+        reg = <0x0 0x51040000 0x0 0x1000>;
+        interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
+        clocks = <&clk_uart>, <&clk_apb>;
+        clock-names = "baudclk", "apb_pclk";
+        reg-io-width = <4>;
+        reg-shift = <2>;
+    };
+
+    clk_netsec: refclk250mhz {
+        compatible = "fixed-clock";
+        clock-frequency = <250000000>;
+        #clock-cells = <0>;
+    };
+
+    netsec: ethernet@522d0000 {
+        compatible = "socionext,synquacer-netsec";
+        reg = <0 0x522d0000 0x0 0x10000>,
+              <0 FixedPcdGet32 (PcdNetsecEepromBase) 0x0 0x10000>;
+        interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
+        clocks = <&clk_netsec>;
+        clock-names = "phy_ref_clk";
+        max-speed = <1000>;
+        max-frame-size = <9000>;
+        phy-handle = <&phy_netsec>;
+        dma-coherent;
+
+        mdio_netsec: mdio {
+            #address-cells = <1>;
+            #size-cells = <0>;
+        };
+    };
+
+    smmu: iommu@582c0000 {
+        compatible = "arm,mmu-500", "arm,smmu-v2";
+        reg = <0x0 0x582c0000 0x0 0x10000>;
+        #global-interrupts = <1>;
+        interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
+                     <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
+                     <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
+        #iommu-cells = <1>;
+        status = "disabled";
+    };
+
+    pcie0: pcie@60000000 {
+        compatible = "socionext,synquacer-pcie-ecam", "snps,dw-pcie-ecam";
+        device_type = "pci";
+        reg = <0x0 0x60000000 0x0 0x7f00000>;
+        bus-range = <0x0 0x7e>;
+        #address-cells = <3>;
+        #size-cells = <2>;
+        ranges = <0x1000000 0x00 0x00000000 0x00 0x67f00000 0x0 0x00010000>,
+                 <0x2000000 0x00 0x68000000 0x00 0x68000000 0x0 0x08000000>,
+                 <0x3000000 0x3e 0x00000000 0x3e 0x00000000 0x1 0x00000000>;
+
+        #interrupt-cells = <0x1>;
+        interrupt-map-mask = <0x0 0x0 0x0 0x0>;
+        interrupt-map = <0x0 0x0 0x0 0x0 &gic 0x0 0x0 GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
+
+        msi-map = <0x000 &its 0x0 0x7f00>;
+        dma-coherent;
+        status = "disabled";
+    };
+
+    pcie1: pcie@70000000 {
+        compatible = "socionext,synquacer-pcie-ecam", "snps,dw-pcie-ecam";
+        device_type = "pci";
+        reg = <0x0 0x70000000 0x0 0x7f00000>;
+        bus-range = <0x0 0x7e>;
+        #address-cells = <3>;
+        #size-cells = <2>;
+        ranges = <0x1000000 0x00 0x00000000 0x00 0x77f00000 0x0 0x00010000>,
+                 <0x2000000 0x00 0x78000000 0x00 0x78000000 0x0 0x08000000>,
+                 <0x3000000 0x3f 0x00000000 0x3f 0x00000000 0x1 0x00000000>;
+
+        #interrupt-cells = <0x1>;
+        interrupt-map-mask = <0x0 0x0 0x0 0x0>;
+        interrupt-map = <0x0 0x0 0x0 0x0 &gic 0x0 0x0 GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>;
+
+        msi-map = <0x0 &its 0x10000 0x7f00>;
+        dma-coherent;
+        status = "disabled";
+    };
+
+    gpio: gpio@51000000 {
+        compatible = "socionext,synquacer-gpio", "fujitsu,mb86s70-gpio";
+        reg = <0x0 0x51000000 0x0 0x100>;
+        gpio-controller;
+        #gpio-cells = <2>;
+        clocks = <&clk_apb>;
+        base = <0>;
+    };
+
+    exiu: interrupt-controller@510c0000 {
+        compatible = "socionext,synquacer-exiu";
+        reg = <0x0 0x510c0000 0x0 0x20>;
+        interrupt-controller;
+        interrupt-parent = <&gic>;
+        #interrupt-cells = <3>;
+        socionext,spi-base = <112>;
+    };
+
+    clk_alw_b_0: bclk200 {
+        compatible = "fixed-clock";
+        #clock-cells = <0>;
+        clock-frequency = <200000000>;
+        clock-output-names = "sd_bclk";
+    };
+
+    clk_alw_c_0: sd4clk800 {
+        compatible = "fixed-clock";
+        #clock-cells = <0>;
+        clock-frequency = <800000000>;
+        clock-output-names = "sd_sd4clk";
+    };
+
+    sdhci: sdhci@52300000 {
+        compatible = "socionext,synquacer-sdhci", "fujitsu,mb86s70-sdhci-3.0";
+        reg = <0 0x52300000 0x0 0x1000>;
+        interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
+                     <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
+        bus-width = <8>;
+        cap-mmc-highspeed;
+        fujitsu,cmd-dat-delay-select;
+        clocks = <&clk_alw_c_0 &clk_alw_b_0>;
+        clock-names = "core", "iface";
+        dma-coherent;
+        status = "disabled";
+    };
+
+    clk_alw_1_8: spi_ihclk {
+        compatible = "fixed-clock";
+        #clock-cells = <0>;
+        clock-frequency = <125000000>;
+        clock-output-names = "iHCLK";
+    };
+
+    spi: spi@54810000 {
+        compatible = "socionext,synquacer-spi";
+        reg = <0x0 0x54810000 0x0 0x1000>;
+        interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
+                     <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
+                     <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
+        clocks = <&clk_alw_1_8>;
+        clock-names = "iHCLK";
+        socionext,use-rtm;
+        socionext,set-aces;
+        #address-cells = <1>;
+        #size-cells = <0>;
+        status = "disabled";
+    };
+
+    clk_i2c: i2c_pclk {
+        compatible = "fixed-clock";
+        #clock-cells = <0>;
+        clock-frequency = <62500000>;
+        clock-output-names = "pclk";
+    };
+
+    i2c: i2c@51210000 {
+        compatible = "socionext,synquacer-i2c";
+        reg = <0x0 0x51210000 0x0 0x1000>;
+        interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
+        clocks = <&clk_i2c>;
+        clock-names = "pclk";
+        clock-frequency = <400000>;
+        #address-cells = <1>;
+        #size-cells = <0>;
+    };
+
+    tpm: tpm_tis@10000000 {
+        compatible = "socionext,synquacer-tpm-mmio";
+        reg = <0x0 0x10000000 0x0 0x5000>;
+        status = "disabled";
+    };
+
+    firmware {
+        optee {
+            compatible = "linaro,optee-tz";
+            method = "smc";
+            status = "disabled";
+        };
+    };
+};
+
+#include "synquacer-sc2a11-caches.dtsi"
diff --git a/arch/arm/include/asm/arch-lpc32xx/config.h b/arch/arm/include/asm/arch-lpc32xx/config.h
index 0836091af2..45e46f9946 100644
--- a/arch/arm/include/asm/arch-lpc32xx/config.h
+++ b/arch/arm/include/asm/arch-lpc32xx/config.h
@@ -12,8 +12,8 @@
 /* Basic CPU architecture */
 
 /* UART configuration */
-#if	(CONFIG_SYS_LPC32XX_UART == 1) || (CONFIG_SYS_LPC32XX_UART == 2) || \
-	(CONFIG_SYS_LPC32XX_UART == 7)
+#if	(CONFIG_CONS_INDEX == 1) || (CONFIG_CONS_INDEX == 2) || \
+	(CONFIG_CONS_INDEX == 7)
 #if !defined(CONFIG_LPC32XX_HSUART)
 #define CONFIG_LPC32XX_HSUART
 #endif
diff --git a/arch/arm/include/asm/gpio.h b/arch/arm/include/asm/gpio.h
index 7609367884..650783ae73 100644
--- a/arch/arm/include/asm/gpio.h
+++ b/arch/arm/include/asm/gpio.h
@@ -1,10 +1,4 @@
-#if !defined(CONFIG_ARCH_UNIPHIER) && !defined(CONFIG_ARCH_STI) && \
-	!defined(CONFIG_ARCH_K3) && !defined(CONFIG_ARCH_BCM68360) && \
-	!defined(CONFIG_ARCH_BCM6858) && !defined(CONFIG_ARCH_BCM63158) && \
-	!defined(CONFIG_ARCH_ROCKCHIP) && !defined(CONFIG_ARCH_ASPEED) && \
-	!defined(CONFIG_ARCH_U8500) && !defined(CONFIG_CORTINA_PLATFORM) && \
-	!defined(CONFIG_TARGET_BCMNS3) && !defined(CONFIG_TARGET_TOTAL_COMPUTE) && \
-	!defined(CONFIG_ARCH_QEMU)
+#ifdef CONFIG_GPIO_EXTRA_HEADER
 #include <asm/arch/gpio.h>
 #endif
 #include <asm-generic/gpio.h>
diff --git a/arch/arm/mach-lpc32xx/Kconfig b/arch/arm/mach-lpc32xx/Kconfig
index 986ad738ac..185bda41c2 100644
--- a/arch/arm/mach-lpc32xx/Kconfig
+++ b/arch/arm/mach-lpc32xx/Kconfig
@@ -12,9 +12,13 @@ config TARGET_DEVKIT3250
 config TARGET_WORK_92105
 	bool "Work Microwave Work_92105"
 
+config TARGET_EA_LPC3250DEVKITV2
+	bool "Embedded Artists LPC3250 Developer's Kit v2"
+
 endchoice
 
 source "board/timll/devkit3250/Kconfig"
 source "board/work-microwave/work_92105/Kconfig"
+source "board/ea/ea-lpc3250devkitv2/Kconfig"
 
 endif
diff --git a/arch/arm/mach-lpc32xx/devices.c b/arch/arm/mach-lpc32xx/devices.c
index e1e2e0d094..0a4fef295a 100644
--- a/arch/arm/mach-lpc32xx/devices.c
+++ b/arch/arm/mach-lpc32xx/devices.c
@@ -23,8 +23,7 @@ void lpc32xx_uart_init(unsigned int uart_id)
 		return;
 
 	/* Disable loopback mode, if it is set by S1L bootloader */
-	clrbits_le32(&ctrl->loop,
-		     UART_LOOPBACK(CONFIG_SYS_LPC32XX_UART));
+	clrbits_le32(&ctrl->loop, UART_LOOPBACK(uart_id));
 
 	if (uart_id < 3 || uart_id > 6)
 		return;
diff --git a/arch/arm/mach-snapdragon/clock-snapdragon.c b/arch/arm/mach-snapdragon/clock-snapdragon.c
index fbe0b5212f..2b76371718 100644
--- a/arch/arm/mach-snapdragon/clock-snapdragon.c
+++ b/arch/arm/mach-snapdragon/clock-snapdragon.c
@@ -56,15 +56,15 @@ void clk_enable_vote_clk(phys_addr_t base, const struct vote_clk *vclk)
 	} while ((val != BRANCH_ON_VAL) && (val != BRANCH_NOC_FSM_ON_VAL));
 }
 
-#define APPS_CMD_RGCR_UPDATE BIT(0)
+#define APPS_CMD_RCGR_UPDATE BIT(0)
 
-/* Update clock command via CMD_RGCR */
-void clk_bcr_update(phys_addr_t apps_cmd_rgcr)
+/* Update clock command via CMD_RCGR */
+void clk_bcr_update(phys_addr_t apps_cmd_rcgr)
 {
-	setbits_le32(apps_cmd_rgcr, APPS_CMD_RGCR_UPDATE);
+	setbits_le32(apps_cmd_rcgr, APPS_CMD_RCGR_UPDATE);
 
 	/* Wait for frequency to be updated. */
-	while (readl(apps_cmd_rgcr) & APPS_CMD_RGCR_UPDATE)
+	while (readl(apps_cmd_rcgr) & APPS_CMD_RCGR_UPDATE)
 		;
 }
 
diff --git a/arch/arm/mach-snapdragon/include/mach/sysmap-apq8016.h b/arch/arm/mach-snapdragon/include/mach/sysmap-apq8016.h
index 520e2e6bd7..d9a3b1af98 100644
--- a/arch/arm/mach-snapdragon/include/mach/sysmap-apq8016.h
+++ b/arch/arm/mach-snapdragon/include/mach/sysmap-apq8016.h
@@ -8,7 +8,7 @@
 #define _MACH_SYSMAP_APQ8016_H
 
 #define GICD_BASE			(0x0b000000)
-#define GICC_BASE			(0x0a20c000)
+#define GICC_BASE			(0x0b002000)
 
 /* Clocks: (from CLK_CTL_BASE)  */
 #define GPLL0_STATUS			(0x2101C)
diff --git a/arch/powerpc/cpu/mpc83xx/pci.c b/arch/powerpc/cpu/mpc83xx/pci.c
index 5c289d0022..507ab3417b 100644
--- a/arch/powerpc/cpu/mpc83xx/pci.c
+++ b/arch/powerpc/cpu/mpc83xx/pci.c
@@ -27,6 +27,7 @@ DECLARE_GLOBAL_DATA_PTR;
 static struct pci_controller pci_hose[MAX_BUSES];
 static int pci_num_buses;
 
+#if !defined(CONFIG_DM_PCI)
 static void pci_init_bus(int bus, struct pci_region *reg)
 {
 	volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
@@ -184,6 +185,7 @@ void mpc83xx_pcislave_unlock(int bus)
 	hose->last_busno = pci_hose_scan(hose);
 }
 #endif
+#endif /* CONFIG_DM_PCI */
 
 #if defined(CONFIG_OF_LIBFDT)
 void ft_pci_setup(void *blob, struct bd_info *bd)
diff --git a/arch/powerpc/dts/mpc8379erdb.dts b/arch/powerpc/dts/mpc8379erdb.dts
index b1881b161c..2e7c8f103c 100644
--- a/arch/powerpc/dts/mpc8379erdb.dts
+++ b/arch/powerpc/dts/mpc8379erdb.dts
@@ -69,6 +69,58 @@
 			device_type = "ipic";
 		};
 
+		usb@23000 {
+			compatible = "fsl-usb2-dr";
+			reg = <0x23000 0x1000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			interrupt-parent = <&ipic>;
+			interrupts = <38 0x8>;
+			phy_type = "ulpi";
+		};
+
+		enet0: ethernet@24000 {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			cell-index = <0>;
+			device_type = "network";
+			model = "eTSEC";
+			compatible = "fsl,etsec2";
+			reg = <0x24000 0x1000>;
+			ranges = <0x0 0x24000 0x1000>;
+			local-mac-address = [ 00 00 00 00 00 00 ];
+			interrupts = <32 0x8 33 0x8 34 0x8>;
+			phy-connection-type = "mii";
+			interrupt-parent = <&ipic>;
+			fixed-link = <1 0 1000 0 0>;
+			phy-handle = <&phy>;
+			fsl,magic-packet;
+
+			mdio@520 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "fsl,etsec2-mdio";
+				reg = <0x520 0x20>;
+
+				phy: ethernet-phy@2 {
+					interrupt-parent = <&ipic>;
+					interrupts = <17 0x8>;
+					reg = <0x2>;
+					device_type = "ethernet-phy";
+				};
+			};
+		};
+
+		pci0: pci@e0008300 {
+	                #address-cells = <3>;
+	                #size-cells = <2>;
+	                #interrupt-cells = <1>;
+	                device_type = "pci";
+	                reg = <0x0 0xe0008300 0x0 0x00000fff>;
+			compatible = "fsl,mpc837x-pci";
+	                clock-frequency = <0>;
+		};
+
 	};
 
 };