Merge tag 'u-boot-atmel-2021.01-b' of https://gitlab.denx.de/u-boot/custodians/u-boot-atmel

Second set of u-boot-atmel features for 2021.01 cycle:

This feature set brings the rework of the clock tree for sam9x60 SoC.
This makes the clock tree fully compatible with Common Clock Framework
and allows full clock configuration in U-Boot. This means that the
sam9x60 boards can boot now using U-Boot.
This also includes the definitions for sam9x60 SiPs and a divisor fix
for the clock on sama7g5 SoC.

5 files changed, 64 insertions, 198 deletions

diff --git a/arch/arm/dts/sam9x60.dtsi b/arch/arm/dts/sam9x60.dtsi
index 41ac1f164c..7f3eae3f5d 100644
--- a/arch/arm/dts/sam9x60.dtsi
+++ b/arch/arm/dts/sam9x60.dtsi
@@ -12,7 +12,7 @@
 #include <dt-bindings/pinctrl/at91.h>
 #include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/clock/at91.h>
+#include <dt-bindings/clk/at91.h>
 
 /{
 	model = "Microchip SAM9X60 SoC";
@@ -27,16 +27,26 @@
 	};
 
 	clocks {
+		slow_rc_osc: slow_rc_osc {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <18500>;
+		};
+
+		main_rc: main_rc {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <12000000>;
+		};
+
 		slow_xtal: slow_xtal {
 			compatible = "fixed-clock";
 			#clock-cells = <0>;
-			clock-frequency = <0>;
 		};
 
 		main_xtal: main_xtal {
 			compatible = "fixed-clock";
 			#clock-cells = <0>;
-			clock-frequency = <0>;
 		};
 	};
 
@@ -49,8 +59,11 @@
 		sdhci0: sdhci-host@80000000 {
 			compatible = "microchip,sam9x60-sdhci";
 			reg = <0x80000000 0x300>;
-			clocks = <&sdhci0_clk>, <&sdhci0_gclk>, <&main>;
-			clock-names = "hclock", "multclk", "baseclk";
+			clocks = <&pmc PMC_TYPE_PERIPHERAL 12>, <&pmc PMC_TYPE_GCK 12>;
+			clock-names = "hclock", "multclk";
+			assigned-clocks = <&pmc PMC_TYPE_GCK 12>;
+			assigned-clock-rates = <100000000>;
+			assigned-clock-parents = <&pmc PMC_TYPE_CORE 10>; /* ID_PLL_A_DIV */
 			bus-width = <4>;
 			pinctrl-names = "default";
 			pinctrl-0 = <&pinctrl_sdhci0>;
@@ -66,7 +79,7 @@
 				compatible = "microchip,sam9x60-qspi";
 				reg = <0xf0014000 0x100>, <0x70000000 0x10000000>;
 				reg-names = "qspi_base", "qspi_mmap";
-				clocks =  <&qspi_clk>, <&qspick>;
+				clocks =  <&pmc PMC_TYPE_PERIPHERAL 35>, <&pmc PMC_TYPE_SYSTEM 18>; /* ID_QSPI */
 				clock-names = "pclk", "qspick";
 				#address-cells = <1>;
 				#size-cells = <0>;
@@ -76,7 +89,7 @@
 			flx0: flexcom@f801c600 {
 				compatible = "atmel,sama5d2-flexcom";
 				reg = <0xf801c000 0x200>;
-				clocks = <&flx0_clk>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 5>;
 				#address-cells = <1>;
 				#size-cells = <1>;
 				ranges = <0x0 0xf801c000 0x800>;
@@ -89,7 +102,7 @@
 				pinctrl-names = "default";
 				pinctrl-0 = <&pinctrl_macb0_rmii>;
 				clock-names = "hclk", "pclk";
-				clocks = <&macb0_clk>, <&macb0_clk>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 24>, <&pmc PMC_TYPE_PERIPHERAL 24>;
 				status = "disabled";
 			};
 
@@ -98,7 +111,7 @@
 				reg = <0xfffff200 0x200>;
 				pinctrl-names = "default";
 				pinctrl-0 = <&pinctrl_dbgu>;
-				clocks = <&dbgu_clk>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 47>;
 				clock-names = "usart";
 			};
 
@@ -155,7 +168,7 @@
 				reg = <0xfffff400 0x200>;
 				#gpio-cells = <2>;
 				gpio-controller;
-				clocks = <&pioA_clk>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 2>;
 			};
 
 			pioB: gpio@fffff600 {
@@ -163,7 +176,7 @@
 				reg = <0xfffff600 0x200>;
 				#gpio-cells = <2>;
 				gpio-controller;
-				clocks = <&pioB_clk>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 3>;
 			};
 
 			pioD: gpio@fffffa00 {
@@ -171,143 +184,29 @@
 				reg = <0xfffffa00 0x200>;
 				#gpio-cells = <2>;
 				gpio-controller;
-				clocks = <&pioD_clk>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 44>;
 			};
 
 			pmc: pmc@fffffc00 {
-				compatible = "atmel,at91sam9x5-pmc";
+				compatible = "microchip,sam9x60-pmc";
 				reg = <0xfffffc00 0x200>;
-				#address-cells = <1>;
-				#size-cells = <0>;
-
-				main: mainck {
-					compatible = "atmel,at91sam9x5-clk-main";
-					#clock-cells = <0>;
-				};
-
-				plla: pllack {
-					compatible = "microchip,sam9x60-clk-pll";
-					#clock-cells = <0>;
-					clocks = <&main>;
-					reg = <0>;
-					atmel,clk-input-range = <8000000 24000000>;
-					#atmel,pll-clk-output-range-cells = <4>;
-					atmel,pll-clk-output-ranges = <140000000 1200000000 0 0>;
-				};
-
-				mck: masterck {
-					compatible = "atmel,at91sam9x5-clk-master";
-					#clock-cells = <0>;
-					clocks = <&md_slck>, <&main>, <&plla>;
-					atmel,clk-output-range = <140000000 200000000>;
-					atmel,clk-divisors = <1 2 4 6>;
-				};
-
-				system: systemck {
-					compatible = "atmel,at91rm9200-clk-system";
-					#address-cells = <1>;
-					#size-cells = <0>;
-
-					qspick: qspick {
-						#clock-cells = <0>;
-						reg = <19>;
-						clocks = <&mck>;
-					};
-				};
-
-				periph: periphck {
-					compatible = "microchip,sam9x60-clk-peripheral";
-					#address-cells = <1>;
-					#size-cells = <0>;
-					clocks = <&mck>;
-
-					pioA_clk: pioA_clk {
-						#clock-cells = <0>;
-						reg = <2>;
-					};
-
-					pioB_clk: pioB_clk {
-						#clock-cells = <0>;
-						reg = <3>;
-					};
-
-					flx0_clk: flx0_clk {
-						#clock-cells = <0>;
-						reg = <5>;
-					};
-
-					pioD_clk: pioD_clk {
-						#clock-cells = <0>;
-						reg = <44>;
-					};
-
-					sdhci0_clk: sdhci0_clk {
-						#clock-cells = <0>;
-						reg = <12>;
-					};
-
-					dbgu_clk: dbgu_clk {
-						#clock-cells = <0>;
-						reg = <47>;
-					};
-
-					macb0_clk: macb0_clk {
-						#clock-cells = <0>;
-						reg = <24>;
-					};
-
-					qspi_clk: qspi_clk {
-						#clock-cells = <0>;
-						reg = <35>;
-					};
-				};
-
-				generic: gck {
-					compatible = "microchip,sam9x60-clk-generated";
-					#address-cells = <1>;
-					#size-cells = <0>;
-					clocks = <&md_slck>, <&td_slck>, <&main>, <&mck>, <&plla>;
-
-					sdhci0_gclk: sdhci0_gclk {
-						#clock-cells = <0>;
-						reg = <12>;
-					};
-				};
+				#clock-cells = <2>;
+				clocks = <&clk32 1>, <&clk32 0>, <&main_xtal>, <&main_rc>;
+				clock-names = "td_slck", "md_slck", "main_xtal", "main_rc";
+				status = "okay";
 			};
 
 			pit: timer@fffffe40 {
 				compatible = "atmel,at91sam9260-pit";
 				reg = <0xfffffe40 0x10>;
-				clocks = <&mck>;
+				clocks = <&pmc PMC_TYPE_CORE 11>; /* ID_MCK. */
 			};
 
-			slowckc: sckc@fffffe50 {
-				compatible = "atmel,at91sam9x5-sckc";
+			clk32: sckc@fffffe50 {
+				compatible = "microchip,sam9x60-sckc";
 				reg = <0xfffffe50 0x4>;
-
-				slow_osc: slow_osc {
-					compatible = "atmel,at91sam9x5-clk-slow-osc";
-					#clock-cells = <0>;
-					clocks = <&slow_xtal>;
-				};
-
-				slow_rc_osc: slow_rc_osc {
-					compatible = "atmel,at91sam9x5-clk-slow-rc-osc";
-					#clock-cells = <0>;
-					clock-frequency = <32768>;
-				};
-
-				td_slck: td_slck {
-					compatible = "atmel,at91sam9x5-clk-slow";
-					#clock-cells = <0>;
-					clocks = <&slow_rc_osc>, <&slow_osc>;
-				};
-
-				md_slck: md_slck {
-					compatible = "atmel,at91sam9x5-clk-slow";
-					#clock-cells = <0>;
-					clocks = <&slow_rc_osc>;
-				};
+				clocks = <&slow_rc_osc>, <&slow_xtal>;
+				#clock-cells = <1>;
 			};
 		};
 	};
diff --git a/arch/arm/dts/sam9x60ek-u-boot.dtsi b/arch/arm/dts/sam9x60ek-u-boot.dtsi
index 93cf1262f6..8c63ed869c 100644
--- a/arch/arm/dts/sam9x60ek-u-boot.dtsi
+++ b/arch/arm/dts/sam9x60ek-u-boot.dtsi
@@ -23,7 +23,7 @@
 	};
 };
 
-&sdhci0 {
+&clk32 {
 	u-boot,dm-pre-reloc;
 };
 
@@ -31,7 +31,11 @@
 	u-boot,dm-pre-reloc;
 };
 
-&qspi {
+&main_rc {
+	u-boot,dm-pre-reloc;
+};
+
+&main_xtal {
 	u-boot,dm-pre-reloc;
 };
 
@@ -59,74 +63,18 @@
 	u-boot,dm-pre-reloc;
 };
 
-&main {
-	u-boot,dm-pre-reloc;
-};
-
-&plla {
-	u-boot,dm-pre-reloc;
-};
-
-&mck {
-	u-boot,dm-pre-reloc;
-};
-
-&system {
-	u-boot,dm-pre-reloc;
-};
-
-&qspick {
-	u-boot,dm-pre-reloc;
-};
-
-&periph {
-	u-boot,dm-pre-reloc;
-};
-
-&pioA_clk {
-	u-boot,dm-pre-reloc;
-};
-
-&pioB_clk {
-	u-boot,dm-pre-reloc;
-};
-
-&sdhci0_clk {
-	u-boot,dm-pre-reloc;
-};
-
-&dbgu_clk {
-	u-boot,dm-pre-reloc;
-};
-
-&qspi_clk {
-	u-boot,dm-pre-reloc;
-};
-
-&generic {
-	u-boot,dm-pre-reloc;
-};
-
-&sdhci0_gclk {
+&qspi {
 	u-boot,dm-pre-reloc;
 };
 
-&slowckc {
+&sdhci0 {
 	u-boot,dm-pre-reloc;
 };
 
-&slow_osc {
+&slow_xtal {
 	u-boot,dm-pre-reloc;
 };
 
 &slow_rc_osc {
 	u-boot,dm-pre-reloc;
 };
-
-&td_slck {
-	u-boot,dm-pre-reloc;
-};
-
-&md_slck {
-	u-boot,dm-pre-reloc;
-};
diff --git a/arch/arm/dts/sam9x60ek.dts b/arch/arm/dts/sam9x60ek.dts
index 8767de98b8..96914b3ea2 100644
--- a/arch/arm/dts/sam9x60ek.dts
+++ b/arch/arm/dts/sam9x60ek.dts
@@ -18,6 +18,16 @@
 		i2c0 = &flx0;
 	};
 
+	clocks {
+		slow_xtal: slow_xtal {
+			clock-frequency = <32768>;
+		};
+
+		main_xtal: main_xtal {
+			clock-frequency = <24000000>;
+		};
+	};
+
 	onewire_tm: onewire {
 		gpios = <&pioD 14 0>;
 		pinctrl-names = "default";
@@ -57,7 +67,7 @@
 					pinctrl-0 = <&pinctrl_flx0>;
 					#address-cells = <1>;
 					#size-cells = <0>;
-					clocks = <&flx0_clk>;
+					clocks = <&pmc PMC_TYPE_PERIPHERAL 5>;
 					status = "okay";
 
 					eeprom@53 {
diff --git a/arch/arm/mach-at91/arm926ejs/sam9x60_devices.c b/arch/arm/mach-at91/arm926ejs/sam9x60_devices.c
index d463bbc788..e3d3dd880c 100644
--- a/arch/arm/mach-at91/arm926ejs/sam9x60_devices.c
+++ b/arch/arm/mach-at91/arm926ejs/sam9x60_devices.c
@@ -44,6 +44,12 @@ char *get_cpu_name(void)
 		switch (extension_id) {
 		case ARCH_EXID_SAM9X60:
 			return "SAM9X60";
+		case ARCH_EXID_SAM9X60_D6K:
+			return "SAM9X60 8MiB SDRAM SiP";
+		case ARCH_EXID_SAM9X60_D5M:
+			return "SAM9X60 64MiB DDR2 SiP";
+		case ARCH_EXID_SAM9X60_D1G:
+			return "SAM9X60 128MiB DDR2 SiP";
 		default:
 			return "Unknown CPU type";
 		}
diff --git a/arch/arm/mach-at91/include/mach/sam9x60.h b/arch/arm/mach-at91/include/mach/sam9x60.h
index 0f00a9ae87..b7f43226b7 100644
--- a/arch/arm/mach-at91/include/mach/sam9x60.h
+++ b/arch/arm/mach-at91/include/mach/sam9x60.h
@@ -128,6 +128,9 @@
 #define ARCH_ID_SAM9X60		0x819b35a0
 #define ARCH_ID_VERSION_MASK	0x1f
 #define ARCH_EXID_SAM9X60	0x00000000
+#define ARCH_EXID_SAM9X60_D6K	0x00000011
+#define ARCH_EXID_SAM9X60_D5M	0x00000001
+#define ARCH_EXID_SAM9X60_D1G	0x00000010
 
 #define cpu_is_sam9x60()	(get_chip_id() == ARCH_ID_SAM9X60)